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path: root/drivers/gpu/drm/i915/intel_cdclk.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-06-29drm/i915: reintroduce VLV/CHV PFI programming power domain workaroundGabriel Krisman Bertazi1-0/+20
2017-06-12drm/i915/cnl: Allow dynamic cdclk changes on CNLRodrigo Vivi1-4/+56
2017-06-12drm/i915/cnl: Implement CNL display init/unit sequenceVille Syrjälä1-1/+107
2017-06-12drm/i915/cnl: Implement .set_cdclk() for CNLVille Syrjälä1-0/+106
2017-06-12drm/i915/cnl: Implement .get_display_clock_speed() for CNLVille Syrjälä1-1/+55
2017-06-02drm/i915/cnp: Get/set proper Raw clock frequency on CNP.Rodrigo Vivi1-1/+28
2017-05-05drm/i915: Fix rawclk readout for g4xVille Syrjälä1-4/+2
2017-04-06drm/i915/glk: limit pixel clock to 99% of cdclk workaroundMadhav Chauhan1-3/+13
2017-03-22drm/i915: Implement cdclk restrictions based on Azalia BCLKPandiyan, Dhinakaran1-0/+12
2017-03-22drm/i915/glk: Apply cdclk workaround for DP audioPandiyan, Dhinakaran1-6/+11
2017-03-13drm/i915: Use new atomic iterator macros in cdclkMaarten Lankhorst1-1/+1
2017-03-07drm/i915: remove potentially confusing IS_G4X checksPaulo Zanoni1-2/+2
2017-02-08drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cdclk() hookVille Syrjälä1-46/+33
2017-02-08drm/i915: Nuke the VLV/CHV PFI programming power domain workaroundVille Syrjälä1-14/+0
2017-02-08drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()Ville Syrjälä1-1/+4
2017-02-08drm/i915: Pass the cdclk state to the set_cdclk() functionsVille Syrjälä1-30/+48
2017-02-08drm/i915: Pass dev_priv to remainder of the cdclk functionsVille Syrjälä1-15/+10
2017-02-08drm/i915: Track full cdclk state for the logical and actual cdclk frequenciesVille Syrjälä1-45/+78
2017-02-08drm/i915: Start moving the cdclk stuff into a distinct state structureVille Syrjälä1-156/+226
2017-02-08drm/i915: Pass computed vco to bxt_set_cdclk()Ville Syrjälä1-14/+19
2017-02-08drm/i915: Move most cdclk/rawclk related code to intel_cdclk.cVille Syrjälä1-0/+1794
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