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path: root/drivers/gpu/drm/i915/intel_ddi.c (follow)
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2016-08-04drm/i915: Track active streams also for DP SSTVille Syrjälä1-0/+10
2016-08-04drm/i915: Avoid mixing up SST and MST in DDI setupVille Syrjälä1-18/+3
2016-08-02drm/i915: Extract bdw_get_buf_trans_edp()Ville Syrjälä1-7/+13
2016-08-02drm/i915: Simplify intel_ddi_get_encoder_port()Ville Syrjälä1-28/+8
2016-08-02drm/i915: Get the iboost setting based on the port typeVille Syrjälä1-4/+3
2016-08-02drm/i915: Split DP/eDP/FDI and HDMI/DVI DDI buffer programming apartVille Syrjälä1-29/+46
2016-08-02drm/i915: Explicitly use ddi buf trans entry 9 for hdmiVille Syrjälä1-2/+2
2016-08-02drm/i915: Move bxt_ddi_vswing_sequence() call into intel_ddi_pre_enable() for HDMIVille Syrjälä1-11/+4
2016-08-02drm/i915: Program iboost settings for HDMI/DVI on SKLVille Syrjälä1-11/+40
2016-08-02drm/i915: Name the "iboost bit"Ville Syrjälä1-1/+1
2016-08-02drm/i915: Fix iboost setting for DDI with 4 lanes on SKLVille Syrjälä1-13/+23
2016-07-07drm/i915: s/INTEL_OUTPUT_DISPLAYPORT/INTEL_OUTPUT_DP/Ville Syrjälä1-8/+8
2016-07-07drm/i915: Kill has_dp_encoder from pipe_configVille Syrjälä1-2/+1
2016-07-04drm/i915: Mass convert dev->dev_private to to_i915(dev)Chris Wilson1-18/+18
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-1/+4
2016-06-13drm/i915/bxt: Sanitiy check the PHY lane power down statusImre Deak1-0/+25
2016-06-13drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixesImre Deak1-7/+6
2016-06-13drm/i915/bxt: Set DDI PHY lane latency optimization during modesetImre Deak1-43/+80
2016-06-13drm/i915/bxt: Move DDI PHY enabling/disabling to the power well codeImre Deak1-37/+9
2016-06-13drm/i915/bxt: Wait for PHY1 GRC calibration synchronouslyImre Deak1-12/+3
2016-05-30drm/i915: Give encoders useful namesVille Syrjälä1-1/+1
2016-05-13drm/i915: Remove intel_clock_t typedefAnder Conselvan de Oliveira1-1/+1
2016-05-09drm/i915: Enable/disable TMDS output buffers in DP++ adaptor as neededVille Syrjälä1-0/+12
2016-05-03Revert "drm/i915: start adding dp mst audio"Lyude1-19/+5
2016-04-29drm/i915: Set crtc_state->lane_count for HDMIAnder Conselvan de Oliveira1-1/+3
2016-04-22drm/i915/bxt: Force reprogramming a PHY with invalid HW stateImre Deak1-5/+14
2016-04-22drm/i915/bxt: Wait for PHY1 GRC done if PHY0 was already enabledImre Deak1-3/+18
2016-04-22drm/i915/bxt: Use PHY0 GRC value for HW state verificationImre Deak1-1/+1
2016-04-20drm/i915: Fix eDP low vswing for BroadwellMika Kahola1-2/+10
2016-04-19drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resumeImre Deak1-7/+3
2016-04-15drm/i915/bxt: Add HW state verification for DDI PHY and CDCLKImre Deak1-2/+122
2016-04-15drm/i915/bxt: Don't reprogram an already enabled DDI PHYImre Deak1-0/+40
2016-04-15drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninitImre Deak1-3/+4
2016-04-15drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpersImre Deak1-6/+4
2016-04-15drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-onlyImre Deak1-0/+3
2016-04-04drm/i915/ddi: Silence compiler warning for unknown output typeChris Wilson1-3/+3
2016-04-01drm/i915: Disable FDI RX before DDI_BUF_CTLVille Syrjälä1-6/+12
2016-04-01drm/i915: use for_each_port_masked in bxt phy init for clarityJani Nikula1-3/+7
2016-04-01drm/i915: BXT DDI PHY sequence BUNVandana Kannan1-2/+11
2016-03-29drm/i915: move edp low vswing config to vbt dataJani Nikula1-2/+2
2016-03-29drm/i915: use a substruct in vbt data for edpJani Nikula1-4/+4
2016-03-21drm/i915/bxt: add dsi transcodersJani Nikula1-0/+6
2016-03-09drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll codeAnder Conselvan de Oliveira1-21/+0
2016-03-09drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interfaceAnder Conselvan de Oliveira1-11/+7
2016-03-09drm/i915: Move BXT pll configuration logic to intel_dpll_mgr.cAnder Conselvan de Oliveira1-140/+1
2016-03-09drm/i915: Move SKL/KLB pll selection logic to intel_dpll_mgr.cAnder Conselvan de Oliveira1-300/+1
2016-03-09drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.cAnder Conselvan de Oliveira1-260/+11
2016-03-09drm/i915: Store a direct pointer to shared dpll in intel_crtc_stateAnder Conselvan de Oliveira1-1/+3
2016-03-09drm/i915: Move ddi shared dpll code to intel_dpll_mgr.cAnder Conselvan de Oliveira1-472/+0
2016-03-07drm/i915: Fix bogus dig_port_map[] assignment for pre-HSWTakashi Iwai1-1/+0
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