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path: root/drivers/gpu/drm/i915/intel_pm.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2017-06-01drm/i915/glk: Fix dotclock calculation in skl_check_pipe_max_pixel_rateMaarten Lankhorst1-4/+8
2017-06-01drm/i915/skl+: consider max supported plane pixel rate while scalingMahesh Kumar1-0/+87
2017-06-01drm/i915/skl: New ddb allocation algorithmKumar, Mahesh1-98/+159
2017-06-01drm/i915: Always recompute watermarks when distrust_bios_wm is set, v2.Maarten Lankhorst1-0/+9
2017-05-17drm/i915/skl+: use linetime latency if ddb size is not availableKumar, Mahesh1-9/+33
2017-05-17drm/i915/skl+: Perform wm level calculations in separate functionKumar, Mahesh1-24/+24
2017-05-17drm/i915/skl+: Watermark calculation cleanupKumar, Mahesh1-34/+19
2017-05-17drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocationKumar, Mahesh1-2/+11
2017-05-17drm/i915/skl+: no need to memset againKumar, Mahesh1-3/+1
2017-05-17drm/i915/skl: Fail the flip if no FB for WM calculationKumar, Mahesh1-1/+2
2017-05-17drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed pointKumar, Mahesh1-19/+19
2017-05-17drm/i915: Use fixed_16_16 wrapper for division operationKumar, Mahesh1-2/+2
2017-05-17drm/i915: fix naming of fixed_16_16 wrapper.Kumar, Mahesh1-3/+3
2017-05-10drm/i915: Add g4x watermark tracepointVille Syrjälä1-0/+5
2017-05-10drm/i915: Enable HPLL watermarks on g4xVille Syrjälä1-1/+2
2017-05-10drm/i915: Two stage watermarks for g4xVille Syrjälä1-216/+724
2017-05-10drm/i915: Apply the g4x TLB miss w/a to SR watermarks as wellVille Syrjälä1-6/+9
2017-05-10drm/i915: Refactor wm calculationsVille Syrjälä1-72/+149
2017-05-10drm/i915: Refactor the g4x TLB miss w/a to a helperVille Syrjälä1-7/+20
2017-05-10drm/i915: Fix the g4x watermark TLB miss workaroundVille Syrjälä1-5/+6
2017-05-10drm/i915: Fix cursor 'cpp' in watermark calculatins for old platformsVille Syrjälä1-5/+5
2017-05-10drm/i915: Document CxSRVille Syrjälä1-0/+37
2017-05-10drm/i915: Make vlv/chv watermark debug print less crypticVille Syrjälä1-1/+1
2017-05-10drm/i915: Rename bunch of vlv_ watermark structures to g4x_Ville Syrjälä1-7/+7
2017-05-10drm/i915: s/vlv_num_wm_levels/intel_wm_num_levels/Ville Syrjälä1-9/+9
2017-05-10drm/i915: Drop the debug message from vlv_get_fifo_size()Ville Syrjälä1-7/+0
2017-05-10drm/i915: s/vlv_plane_wm_compute/vlv_raw_plane_wm_compute/ etc.Ville Syrjälä1-11/+11
2017-04-11drm/i915: Use __intel_uncore_wait_for_register_fw for sandybride_pcode_readChris Wilson1-6/+6
2017-04-05drm/i915: Use intel_wm_plane_visible() on VLV/CHV as wellVille Syrjälä1-2/+2
2017-04-05drm/i915: Check for id==PLANE_CURSOR instead of type==DRM_PLANE_TYPE_CURSORVille Syrjälä1-1/+1
2017-03-29drm/i915: Move WARN_ON/MISSING_CASE macros to i915_utils.hMichal Wajdeczko1-1/+1
2017-03-27drm/i915: Limit number of reads to stabilize rc6 counter readsChris Wilson1-1/+2
2017-03-22drm/i915: Fix SKL cursor watermarksVille Syrjälä1-13/+31
2017-03-22drm/i915: Extract intel_wm_plane_visible()Ville Syrjälä1-12/+27
2017-03-17drm/i915: Squelch WARN for VLV_COUNTER_CONTROLChris Wilson1-6/+13
2017-03-17drm/i915: Remove superfluous i915_add_request_no_flush() helperChris Wilson1-1/+1
2017-03-16drm/i915: Use coarse grained residency counter with bytMika Kuoppala1-6/+3
2017-03-16drm/i915: Extend vlv/chv residency resolutionMika Kuoppala1-9/+51
2017-03-16drm/i915: Return residency as microsecondsMika Kuoppala1-6/+6
2017-03-16drm/i915: Move residency calculation into intel_pm.cMika Kuoppala1-0/+31
2017-03-13drm/i915: Optimize VLV/CHV display FIFO updatesVille Syrjälä1-15/+24
2017-03-13drm/i915: Use new atomic iterator macros in wm codeMaarten Lankhorst1-4/+4
2017-03-10drm/i915: Stop using RP_DOWN_EI on BaytrailChris Wilson1-2/+3
2017-03-03drm/i915: Add cxsr toggle tracepointVille Syrjälä1-0/+2
2017-03-03drm/i915: Add VLV/CHV watermark/FIFO programming tracepointsVille Syrjälä1-0/+4
2017-03-03drm/i915: Kill level 0 wm hack for VLV/CHVVille Syrjälä1-4/+0
2017-03-03drm/i915: Workaround VLV/CHV sprite1->sprite0 enable underrunVille Syrjälä1-1/+23
2017-03-03drm/i915: Sanitize VLV/CHV watermarks properlyVille Syrjälä1-1/+49
2017-03-03drm/i915: Nuke crtc->wm.cxsr_allowedVille Syrjälä1-7/+7
2017-03-03drm/i915: Compute proper intermediate wms for vlv/cvhVille Syrjälä1-1/+58