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path: root/drivers/gpu/drm/i915 (follow)
AgeCommit message (Expand)AuthorFilesLines
2015-06-01drm/i915/hsw: Fix workaround for server AUX channel clock divisorJim Bride1-3/+2
2015-05-29drm/i915: limit PPGTT size to 2GB in 32-bit platformsMichel Thierry1-0/+7
2015-05-29Merge branch 'for-linus' into for-nextTakashi Iwai5-9/+39
2015-05-29drm/i915: Another fbdev hack to avoid PSR on fbcon.Rodrigo Vivi1-1/+27
2015-05-29drm/i915: Return the frontbuffer flip to enable intel_crtc_enable_planes.Rodrigo Vivi1-0/+11
2015-05-28drm/i915: disable IPS while getting the sink CRCsPaulo Zanoni1-21/+45
2015-05-28drm/i915: Disable 12bpc hdmi for nowDaniel Vetter1-1/+2
2015-05-28drm/i915: Adjust sideband locking a bit for CHV/VLVVille Syrjälä1-5/+5
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä10-81/+81
2015-05-28drm/i915: Kill intel_flush_primary_plane()Ville Syrjälä4-41/+11
2015-05-28drm/i915: Throw out WIP CHV power well definitionsVille Syrjälä2-98/+4
2015-05-28drm/i915: Use the default 600ns LDO programming sequence delayVille Syrjälä2-0/+6
2015-05-27drm/i915: Remove unnecessary null check in execlists_context_unqueueMichel Thierry1-1/+1
2015-05-26drm/i915: Use spinlocks for checking when to waitboostChris Wilson5-35/+45
2015-05-26Revert "drm/i915: Force clean compilation with -Werror"Daniel Vetter3-15/+0
2015-05-22drm/i915: Update DRIVER_DATE to 20150522Daniel Vetter1-1/+1
2015-05-22drm/i915: Introduce DRM_I915_THROTTLE_JIFFIESChris Wilson3-2/+8
2015-05-22drm/i915: Use the correct destructor for freeing requests on errorChris Wilson1-8/+8
2015-05-22drm/i915/skl: don't fail colorkey + scaler requestChandra Konduru2-14/+30
2015-05-22drm/i915: Enable GTT caching on gen8Ville Syrjälä2-0/+15
2015-05-22drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()Ville Syrjälä2-3/+10
2015-05-22drm/i915: Use ilk_init_lp_watermarks() on BDWVille Syrjälä1-3/+1
2015-05-21drm/i915: Disable FDI RX/TX before the portsVille Syrjälä1-2/+3
2015-05-21drm/i915: Disable CRT port after pipe on PCH platformsVille Syrjälä1-1/+14
2015-05-21drm/i915: Disable SDVO port after the pipe on PCH platformsVille Syrjälä1-8/+17
2015-05-21drm/i915: Disable HDMI port after the pipe on PCH platformsVille Syrjälä1-4/+29
2015-05-21drm/i915: Fix the IBX transcoder B workaroundsVille Syrjälä3-68/+60
2015-05-21drm/i915: Write the SDVO reg twice on IBXVille Syrjälä1-0/+8
2015-05-21drm/i915: Fix DP enhanced framing for CPTVille Syrjälä2-2/+10
2015-05-21drm/i915: Clean up the CPT DP .get_hw_state() port readoutVille Syrjälä2-21/+6
2015-05-21drm/i915: Clarfify the DP code platform checksVille Syrjälä1-23/+23
2015-05-21drm/i915: Remove the double register write from intel_disable_hdmi()Ville Syrjälä1-8/+0
2015-05-21drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()Ville Syrjälä1-8/+0
2015-05-21drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau6-2/+223
2015-05-21drm/i915: Free RPS boosts for all laggardsChris Wilson3-6/+19
2015-05-21drm/i915: Don't downclock whilst we have clients waiting for GPU resultsChris Wilson2-0/+35
2015-05-21drm/i915: Convert RPS tracking to a intel_rps_client structChris Wilson5-27/+38
2015-05-21drm/i915: Limit mmio flip RPS boostsChris Wilson5-1/+7
2015-05-21drm/i915: Limit ring synchronisation (sw sempahores) RPS boostsChris Wilson4-18/+25
2015-05-21drm/i915: Inline check required for object syncing prior to execbufChris Wilson2-6/+13
2015-05-21drm/i915: Implement inter-engine read-read optimisationsChris Wilson10-325/+416
2015-05-21drm/i915: s/\<rq\>/req/gDaniel Vetter5-37/+37
2015-05-21drm/i915/skl: enable WaForceContextSaveRestoreNonCoherentImre Deak1-7/+8
2015-05-21drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+Imre Deak2-2/+6
2015-05-21drm/i915: Force clean compilation with -WerrorChris Wilson3-0/+15
2015-05-20drm/i915: Kill the dev variable in intel_suspend_complete()Damien Lespiau1-5/+4
2015-05-20drm/i915: Add a space after ', ' and don't capitalize mid-sentenceDamien Lespiau1-1/+2
2015-05-20drm/i915/bxt: Also add bxt_resume_prepare() to the S3/S4 pathDamien Lespiau1-2/+5
2015-05-20drm/i915/skl: Swapping 90 and 270 to be compliant with XrandrSonika Jindal1-2/+6
2015-05-20drm/i915: Update comment in clear_intel_crtc_state()Ander Conselvan de Oliveira1-1/+5
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