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path: root/drivers/gpu/drm/nouveau/nouveau_chan.c (follow)
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2013-11-14drm/nv10-: we no longer need to create nvsw object on user channelsBen Skeggs1-8/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs1-2/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-20drm/nv84-/fence: prepare for emit/sync support of sysram sequencesBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-02-20drm/nouveau: report channel owner in error messagesMarcin Slusarz1-1/+2
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nouveau: unpin pushbuffer bo before destroying itMarcin Slusarz1-0/+2
Fixes GART leak (as accounted by nouveau_drm.gem.gart_available). Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nve0: allow specification of channel engine type in abi16 callBen Skeggs1-1/+1
Previously, if either vram/gart handles were specified as ~0, the ioctl call would fail. In order to hack engine selection into the ioctl for kepler, we now define (fb_ctxdma_handle == ~0) to mean "engine mask is in tt_ctxdma_handle". This approach also allows new userspace to detect lack of support for non-PGRAPH channels on older kernels. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-11-29drm/nv50/dmaobj: extend class to allow gpu-specific attributes to be definedBen Skeggs1-1/+1
disp is going to need to be able to create more specific dma objects than was previously possible. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: log channel debug/error messages from client object rather than drm clientBen Skeggs1-5/+5
This will make it more obvious which application caused particular messages. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: quiet some static-related sparse noiseMarcin Slusarz1-1/+1
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fifo: use defines instead of hardcoded class idsBen Skeggs1-2/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fifo: version the dma channel class structBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau/fifo: separate object classes for dma channelsBen Skeggs1-2/+3
Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nve0: use async copy engine for ttm buffer moves if availableBen Skeggs1-16/+19
Kepler PFIFO lost the ability to address multiple engines from a single channel, so we need a separate one for the copy engine. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - regression fix: restore hw accelerated buffer copies Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nve0/fifo: support engine selection when creating fifo channelsBen Skeggs1-1/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-10-03drm/nouveau: port all engines to new engine module formatBen Skeggs1-0/+387
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <marcin.slusarz@gmail.com> - fix find/replace bug in license header v3: Ben Skeggs <bskeggs@redhat.com> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <marcin.slusarz@gmail.com> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <bskeggs@redhat.com> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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