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path: root/drivers/gpu/drm/radeon/radeon.h (follow)
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2013-08-15drm/radeon: fix WREG32_OR macro setting bits in a registerRafał Miłecki1-1/+1
This bug (introduced in 3.10) in WREG32_OR made commit d3418eacad403033e95e49dc14afa37c2112c134 "drm/radeon/evergreen: setup HDMI before enabling it" cause a regression. Sometimes audio over HDMI wasn't working, sometimes display was corrupted. This fixes: https://bugzilla.kernel.org/show_bug.cgi?id=60687 https://bugzilla.kernel.org/show_bug.cgi?id=60709 https://bugs.freedesktop.org/show_bug.cgi?id=67767 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07drm/radeon/cik: use a mutex to properly lock srbm instanced registersAlex Deucher1-0/+2
We need proper locking in the driver when accessing instanced registers on CIK. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07drm/radeon: only save UVD bo when we have open handlesChristian König1-1/+1
Otherwise just reinitialize from scratch on resume, and so make it more likely to succeed. Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07drm/gem: create drm_gem_dumb_destroyDaniel Vetter1-3/+0
All the gem based kms drivers really want the same function to destroy a dumb framebuffer backing storage object. So give it to them and roll it out in all drivers. This still leaves the option open for kms drivers which don't use GEM for backing storage, but it does decently simplify matters for gem drivers. Acked-by: Inki Dae <inki.dae@samsung.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org> Cc: Ben Skeggs <skeggsb@gmail.com> Reviwed-by: Rob Clark <robdclark@gmail.com> Cc: Alex Deucher <alexdeucher@gmail.com> Acked-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-17drm/radeon: add a module parameter to disable aspmAlex Deucher1-0/+1
Can cause hangs when enabled in certain motherboards. Set radeon.aspm=0 to disable aspm. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-15drm/radeon: align VM PTBs (Page Table Blocks) to 32KAlex Deucher1-0/+5
Covers requirements of all current asics. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-07-14drm/radeon: allow selection of alignment in the sub-allocatorAlex Deucher1-0/+1
There are cases where we need more than 4k alignment. No functional change with this commit. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-07-14drm/radeon: never unpin UVD bo v3Christian König1-1/+2
Changing the UVD BOs offset on suspend/resume doesn't work because the VCPU internally keeps pointers to it. Just keep it always pinned and save the content manually. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66425 v2: fix compiler warning v3: fix CIK support Note: a version of this patch needs to go to stable. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: add checks against vblank timeAlex Deucher1-0/+2
If the vblank time is too short to adjust mclk, assume multiple displays (no mclk adjustments). Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: add infrastructure to force performance levelsAlex Deucher1-0/+10
This allows you to force specific power levels within a power state. Due to hardware restrictions between generations, the interface is limited to the following 3 selections: auto: all levels enabled low: forced to the lowest power level high: forced to the highest power level Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon: add support for 3d perf states on older asicsAlex Deucher1-0/+1
Certain older rv770 asics have both a performance and a 3D performance state rather than just multiple performance levels in the state power state. The current code would select the performance state rather than the 3D performance state when the "performance" profile was selected. This change switches to the "balanced" profile by default which ends up being the internal performance profile. When the user selects the "performance" profile, it selects the internal 3D performance state so the user can select the higher performance modes. For most asics this changes nothing. For certain rv770 asics with static performance and 3D performance states, this allows you to select between then using by selecting the "balanced" and "performance" dpm profiles. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add infrastructure to support debugfs infoAlex Deucher1-0/+2
This lays the frameworks to report realtime power level feedback. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/ttm: make ttm reservation calls behave like reservation callsMaarten Lankhorst1-0/+1
This commit converts the source of the val_seq counter to the ww_mutex api. The reservation objects are converted later, because there is still a lockdep splat in nouveau that has to resolved first. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-06-27drm/radeon/kms: add dpm support for SI (v7)Alex Deucher1-0/+1
This adds dpm support for SI asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2/gen3 switching - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: enable hainan support, rebase v3: guard acpi stuff v4: fix 64 bit math v5: fix 64 bit div harder v6: fix thermal interrupt check noticed by Jerome v7: attempt fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: validate voltages against dispclk requirementsAlex Deucher1-0/+2
Validate the voltages against the voltage requirements of the dispclk. We currently don't adjust the disp clock so it never changes, but we need to filter out voltage levels that are too low none the less. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: pull in ppm info from atomAlex Deucher1-0/+14
Used by SI dpm. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: pull in phase shedding limits from atomAlex Deucher1-0/+12
Required for dpm on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: add an enum for pcie gen selectionAlex Deucher1-0/+7
This makes it easier the understand what the code is doing. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add indirect accessors for UVD CTX registersAlex Deucher1-0/+17
These are needed for certain UVD power saving features. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add atom get leakage vddc functionAlex Deucher1-0/+3
Required for DPM on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add accessors of pif_phy indirect register spaceAlex Deucher1-0/+34
Required for accessing certain pcie related registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update radeon_atom_get_voltage_table() for SIAlex Deucher1-1/+1
SI uses a new atom table revision. Required for DPM on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: update radeon_atom_is_voltage_gpio() for SIAlex Deucher1-1/+2
SI uses a new atom table. Required for DPM on SI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/atom: add helper to calcuate mpll paramsAlex Deucher1-0/+4
There's a new table for calculating the memory pll parameters on SI. Required for SI DPM support. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: implement apci perf requestAlex Deucher1-1/+1
These functions use acpi methods to adjust the pcie gen speed. Used by DPM. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: remove broken dyn state remnantsAlex Deucher1-1/+0
Now that the proper fix has been implemented I can remove the last remnants of the initial implementation. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: add new pre/post_set_power_state callbacksAlex Deucher1-0/+4
Needed to properly handle dynamic state adjustment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: fixup dynamic state adjust for btc (v2)Alex Deucher1-0/+13
Use a dedicated copy of the current power state since we may have to adjust it on the fly. v2: fix up redundant state sets Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: fixup dynamic state adjust for sumoAlex Deucher1-0/+1
Use a dedicated copy of the current power state since we may have to adjust it on the fly. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: track whether we are on AC or batteryAlex Deucher1-0/+1
Driver needs this information to validate power states. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/dpm: add helpers for extended power tables (v2)Alex Deucher1-0/+70
This data will be needed for dpm on newer asics. v2: fix typo in rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: enable UVD as needed (v9)Alex Deucher1-0/+1
When using UVD, the driver must switch to a special UVD power state. In the CS ioctl, switch to the power state and schedule work to change the power state back, when the work comes up, check if uvd is still busy and if not, switch back to the user state, otherwise, reschedule the work. Note: We really need some better way to decide when to switch out of the uvd power state. Switching power states while playback is active make uvd angry. V2: fix locking. V3: switch from timer to delayed work V4: check fence driver for UVD jobs, reduce timeout to 1 second and rearm timeout on activity v5: rebase on new dpm tree v6: rebase on interim uvd on demand changes v7: fix UVD when DPM is disabled v8: unify non-DPM and DPM UVD handling v9: remove leftover idle work struct Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2013-06-27drm/radeon/kms: add dpm support for evergreen (v4)Alex Deucher1-0/+13
This adds dpm support for evergreen asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage, rename ulv struct v3: fix thermal interrupt check notices by Jerome v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add dpm support for rv7xx (v4)Alex Deucher1-0/+1
This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add dpm support for rv6xx (v3)Alex Deucher1-0/+3
This adds dpm support for rv6xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: remove duplicate line v3: fix thermal interrupt check noticed by Jerome Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-27drm/radeon/kms: add common r600 dpm functionsAlex Deucher1-0/+13
These are shared by rs780/rs880, rv6xx, and newer chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add common dpm infrastructureAlex Deucher1-1/+99
This adds the common dpm (dynamic power management) infrastructure: - dpm callbacks - dpm init/fini/suspend/resume - dpm power state selection No device specific code is enabled yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add atom helper functions for dpm (v3)Alex Deucher1-0/+33
dpm needs access to atombios data and command tables for setup and calculation of a number of parameters. v2: endian fix v3: fix mc reg table bug Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: properly set up the RLC on ON/LN/TN (v3)Alex Deucher1-3/+10
This is required for certain advanced functionality. v2: save/restore list takes dword offsets v3: rebase on gpu reset changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: make get_temperature functions a callbackAlex Deucher1-5/+2
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/evergreen: add indirect register accessors for CG registersAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/kms: add accessors for RCU indirect spaceAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: add cik tile mode array queryAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon/cik: Add support for compute queues (v4)Alex Deucher1-0/+19
On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: implement simple doorbell page allocatorAlex Deucher1-0/+21
The doorbell aperture is a PCI BAR whose pages can be mapped to compute resources for things like wptrs for userspace queues. This patch maps the BAR and sets up a simple allocator to allocate pages from the BAR. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27drm/radeon: use callbacks for ring pointer handling (v3)Alex Deucher1-0/+7
Add callbacks to the radeon_asic struct to handle rptr/wptr fetchs and wptr updates. We currently use one version for all rings, but this allows us to override with a ring specific versions. Needed for compute rings on CIK. v2: udpate as per Christian's comments v3: fix some rebase cruft Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: add indirect register accessors for SMC registersAlex Deucher1-0/+17
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon/cik: add hw cursor support (v2)Alex Deucher1-0/+7
CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26drm/radeon: handle the integrated thermal controller on CIAlex Deucher1-0/+1
No support for reading the temperature yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher1-0/+1
CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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