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2020-11-04drm/msm/gem: Move locking in shrinker pathRob Clark3-45/+35
Move grabbing the bo lock into shrinker, with a msm_gem_trylock() to skip over bo's that are already locked. This gets rid of the nested lock classes. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/gem: Add some _locked() helpersRob Clark2-20/+75
When we cut-over to using dma_resv_lock/etc instead of msm_obj->lock, we'll need these for the submit path (where resv->lock is already held). Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/gem: Move prototypes to msm_gem.hRob Clark6-54/+60
Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/gem: Rename internal get_iova_locked helperRob Clark1-3/+3
We'll need to introduce a _locked() version of msm_gem_get_iova(), so we need to make that name available. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/gem: Add obj->lock wrappersRob Clark2-53/+74
This will make it easier to transition over to obj->resv locking for everything that is per-bo locking. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm: Fix a couple incorrect usages of get_vaddr_active()Rob Clark2-2/+2
The microcode bo's should never be madvise(WONTNEED), so these should not be using msm_gem_get_vaddr_active(). Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dsi: do not try reading 28nm vco rate if it's not enabledDmitry Baryshkov1-1/+4
Reading VCO rate for this PLL can cause boot stalls, if it is not enabled. Guard clk_hw_get_rate with a call to dsi_pll_28nm_clk_is_enabled(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-05drm/mediatek: mtk_dpi: Fix unused variable 'mtk_dpi_encoder_funcs'Enric Balletbo i Serra1-9/+0
Commit f89c696e7f63 ("drm/mediatek: mtk_dpi: Convert to bridge driver") introduced the following build warning with W=1 drivers/gpu/drm/mediatek/mtk_dpi.c:530:39: warning: unused variable 'mtk_dpi_encoder_funcs' [-Wunused-const-variable] static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = { This struct is and the 'mtk_dpi_encoder_destroy()' are not needed anymore, so remove them. Fixes: f89c696e7f63 ("drm/mediatek: mtk_dpi: Convert to bridge driver") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2020-11-04drm/amdgpu/display: FP fixes for DCN3.x (v4)Alex Deucher5-7/+104
Add proper FP_START/END handling and adjust Makefiles per previous asics. v2: fix up harder. v3: fix clkmgr Makefile for dcn30 v4: fix old gcc handling is only required for x86 Build-tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> (v1) Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher77-601/+79
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/amdgpu: Enable arcturus devices to access the method kgd_gfx_v9_get_cu_occupancy that is already definedRamesh Errabolu3-1/+4
[Why] Allow user to know number of compute units (CU) that are in use at any given moment. [How] Remove the keyword static for the method kgd_gfx_v9_get_cu_occupancy Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: fix psr panel lightupRoman Li1-1/+1
[Why] The change for correct asic type check caused a psr regression due to incorrect chip family id for Raven. [How] Use correct family id. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()Kevin Wang1-2/+0
Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/amdgpu: switch on/off vcn power profile modeKenneth Feng1-1/+12
switch to vcn power profile mode when a video is playing. this can optimize the power/performance when the workload is on the vcn. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: update module paramter doc of amdgpu_dpmKevin Wang1-1/+1
the vega20 isn't supported swsmu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: do not initialise global variables to 0 or NULLDeepak R Varma2-23/+23
Initializing global variable to 0 or NULL is not necessary and should be avoided. Issue reported by checkpatch script as: ERROR: do not initialise globals to 0 (or NULL). Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: set LDS_CONFIG=0x20 on Navy Flounder to fix a GPU hang (v2)Marek Olšák1-1/+4
v2: squash in build fix Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: Change the way to determine framebuffer typeGang Ba1-13/+7
Determine FRAMEBUFFER_PUBLIC/PRIVATE only based host-accessibility, not peer-accesssibility Signed-off-by: Gang Ba <gaba@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: fix off by one in amdgpu_vm_handle_faultChristian König1-1/+1
The value is inclusive, not exclusive. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: enable GFXOFF for dimgrey_cavefishTao Zhou2-0/+2
GFXOFF has been supported by PMFW, enable it directly in driver for dimgrey_cavefish. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: resolved ASD loading issue on siennaJohn Clements1-0/+1
updated fw header v2 parser to set asd fw memory Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: Enable FGCG for VangoghJinzhou.Su1-0/+1
Add flags AMD_CG_SUPPORT_GFX_FGCG for Vangogh Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: Add Fine Grain Clock Gating for GFX10Jinzhou.Su1-0/+45
1. Add FGCG for gfx10 2. Get FGCG status for pm info debugfs Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: Add GFX Fine Grain Clock Gating flagJinzhou.Su2-0/+2
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm: unify formatting for color management documentationSimon Ser1-2/+2
Other properties are documented with a colon character after the property name. Consistently using a colon character allows the docs to be machine-readable. Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Daniel Vetter <daniel@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/7dhjUKqlDC0IiRRON0VhWnkuoxcRDLG4EFKzyhcEA@cp7-web-043.plabs.ch
2020-11-04drm/msm: Fix duplicate gpu node in icc summaryAkhil P Oommen3-35/+38
The dev_pm_opp_of_add_table() api initializes the icc nodes for gpu indirectly. So we can avoid using of_icc_get() api in the common probe path. To improve this, move of_icc_get() to target specific code where it is required. This patch helps to fix duplicate gpu node listed in the interconnect summary from the debugfs. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: fix clock scaling on non-sc7180 boardDmitry Baryshkov1-3/+3
c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for display") has added support for handling bandwidth voting in kms path in addition to old mdss path. However this broke all other platforms since _dpu_core_perf_crtc_update_bus() will now error out instead of properly calculating bandwidth and core clocks. Fix _dpu_core_perf_crtc_update_bus() to just skip bandwidth setting instead of returning an error in case kms->num_paths == 0 (MDSS is used for bandwidth management). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: c33b7c0389e1 ("drm/msm/dpu: add support for clk and bw scaling for display") Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: enable merge_3d support on sm8150/sm8250Dmitry Baryshkov3-0/+14
Handle new merge_3d block setup in dpu encoder code. Pass correct mode and id. Note, that merge_3d blocks are not handled via usual RM reservation mechanism, as each merge_3d block is tied to two PPs, so by reserving PP you get merge_3d automatically. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: setup merge modes in merge_3d blockDmitry Baryshkov2-0/+25
Handle setting up merge mode in merge_3d hardware block. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: handle merge_3d configuration in hw_ctl blockDmitry Baryshkov2-0/+28
Active HW CTL blocks need separate handling for merge_3d flushes. Implement necessary merge_3d configuration and flushing. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: initial support for merge3D hardware blockDmitry Baryshkov8-14/+231
Add initial support for merge3D hardware block on SM8[12]50. Merge3D is reposible for merging contents of two LMs (two PPs) into single interface. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: simplify interface flush handlingDmitry Baryshkov4-68/+23
Instead of calling 4 callbacks to set pending masks, call just one to update both pending_flush_mask and pending_intf_flush mask. Note, that CMD mode support incorrectly did not update pending_intf_flush mask, breaking CMD support on SC7180/SM8x50. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm: Implement shutdown callback for adrenoAkhil P Oommen1-0/+6
Implement the shutdown callback for adreno gpu platform device to safely shutdown it before a system reboot. This helps to avoid futher transactions from gpu after the smmu is moved to bypass mode. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dp: add opp_table corner voting support base on dp_ink_clk rateKuogee Hsieh4-6/+70
Set link rate by using OPP set rate api so that CX level will be set accordingly based on the link rate. Changes in v2: -- remove dev from dp_ctrl_put() parameters -- Add more information to commit message Changes in v3: -- return when dev_pm_opp_set_clkname() failed Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm: Remove redundant null checkTian Tao1-5/+2
clk_prepare_enable() and clk_disable_unprepare() will check NULL clock parameter, so It is not necessary to add additional checks. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dsi_phy_10nm: implement PHY disablingDmitry Baryshkov1-0/+22
Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: ff73ff194060 ("drm/msm/dsi: Populate the 10nm PHY funcs") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dsi_phy_7nm: implement PHY disablingDmitry Baryshkov1-1/+22
Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dsi_pll_10nm: restore VCO rate during restore_stateDmitry Baryshkov1-0/+8
PHY disable/enable resets PLL registers to default values. Thus in addition to restoring several registers we also need to restore VCO rate settings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: c6659785dfb3 ("drm/msm/dsi/pll: call vco set rate explicitly") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dsi_pll_7nm: restore VCO rate during restore_stateDmitry Baryshkov1-0/+8
PHY disable/enable resets PLL registers to default values. Thus in addition to restoring several registers we also need to restore VCO rate settings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dpu: Add newline to printksStephen Boyd1-2/+2
Printk messages need newlines. Add it here. Cc: Abhinav Kumar <abhinavk@codeaurora.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm/dp: DisplayPort PHY compliance tests fixupTanmay Shah4-4/+13
Bandwidth code was being used as test link rate. Fix this by converting bandwidth code to test link rate Do not reset voltage and pre-emphasis level during IRQ HPD attention interrupt. Also fix pre-emphasis parsing during test link status process Signed-off-by: Tanmay Shah <tanmay@codeaurora.org> Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/msm: Add missing struct identifierTian Tao1-3/+4
fix warnings reported by make W=1 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:195: warning: cannot understand function prototype: 'const struct dpu_intr_reg dpu_intr_set[] = ' drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:252: warning: cannot understand function prototype: 'const struct dpu_irq_type dpu_irq_map[] = ' Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-11-04drm/i915/tgl: Fix typo during output setupImre Deak1-1/+1
Fix a typo that led to some MST short pulse event handling issue (the short pulse event was handled for both encoder instances, each having its own state). Fixes: 1d8ca002456b6 ("drm/i915: Add PORT_TCn aliases to enum port") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201104010000.4165574-1-imre.deak@intel.com
2020-11-04drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher5-20/+0
No need for a separate config option at this point. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: Add green_sardine support to DMRoman Li1-0/+12
Display Manager support for green_sardine Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amd/display: Add green_sardine support to DCRoman Li4-0/+25
Display Core support for green_sardine Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: enable vcn support for green_sardine (v2)Thong Thai1-1/+7
Enable Green_Sardine VCN support and VCN firmware loading v2: use apu flags Signed-off-by: Thong Thai <thong.thai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: enable green_sardine_asd.bin loading (v2)Aaron Liu1-1/+5
This patch enable green_sardine_asd.bin loading. v2: use apu flags Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu/sdma: add sdma engine support for green_sardine (v2)Prike Liang1-1/+5
Initialize the SDMA IP for green_sardine. v2: use apu flags Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-04drm/amdgpu: add gfx support for green_sardine (v2)Prike Liang1-1/+11
Enable the gfx base HW function of green_sardine. v2: use apu flags Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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