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2022-06-01drm/amd/display: revert Blank eDP on disable/enable drvLeung, Martin9-19/+44
why and how: Revert this change. It was causing a black screen with certain blocks Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Leung, Martin <Martin.Leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-01drm/amd/display: Read Golden Settings Table from VBIOSSherry Wang1-3/+1
[Why] Dmub read AUX_DPHY_RX_CONTROL0 from Golden Setting Table, but driver will set it to default value 0x103d1110, which causes issue in some case [How] Remove the driver code, use the value set by dmub in dp_aux_init Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Sherry Wang <YAO.WANG1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-01drm/i915: Treat DMRRS as static DRRSVille Syrjälä1-4/+20
Some machines declare DRRS type = seamless, DRRS = no, DMRRS = yes. I *think* DMRRS stands for "dynamcic media refresh rate", and I suspect the way it's meant to work is that it lets the driver switch refresh rates to match the frame rate for media playback. Obviously for us all that kind of policy stuff is entirely up to userspace, so the only thing we may do is make the extra refresh rate(s) available. So let's treat this case as just static DRRS for now. In the future We might want to differentiate the "seamless w/ downclocking" vs. "seamless w/o downclocking" cases so that we could do seamless refresh rate changes for systems that only claim to support DMRRS. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125 Acked-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-7-ville.syrjala@linux.intel.com
2022-06-01drm/i915/bios: Define more BDB contentsVille Syrjälä1-7/+43
Add a bunch of new struff we're missing in various BDB blocks. TODO: Bunch of these might actually need to be taken into use... v2: s/lfp_features/lfp_power/features/ (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-6-ville.syrjala@linux.intel.com
2022-06-01drm/i915/bios: Fix aggressiveness typosVille Syrjälä1-4/+4
Fix various typos around "aggressiveness". Note that the VBT spec also sometimes missspells it as "agressiveness" so I guess that's where some of the typos came from. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-5-ville.syrjala@linux.intel.com
2022-06-01drm/i915: Accept more fixed modes with VRR panelsVille Syrjälä5-16/+44
It seem that when dealing with VRR capable eDP panels we need to accept fixed modes with variable vblank length (which is what VRR varies dynamically). Typically the preferred mode seems to be a non-VRR more (lowish dotclock/refresh rate + short vblank). We also have examples where it looks like even the hblank length is a bit different between the preferred mode vs. VRR mode(s). So let's just accept anything that has matching hdisp+vdisp+flags. v2: Document that is_alt_drrs_mode() is a subset of is_alt_vrr_mode() (Jani) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/125 Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-4-ville.syrjala@linux.intel.com
2022-06-01drm/i915: Print out rejected fixed modesVille Syrjälä1-0/+4
To help with debugging DRRS/VRR panel init let's dump out all the fixed modes we rejected for whatever reason. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-3-ville.syrjala@linux.intel.com
2022-06-01drm/i915: Parse VRR capability from VBTVille Syrjälä3-6/+23
VBT seems to have an extra flag for VRR vs. not. Let's consult that for eDP panels. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531191844.11313-2-ville.syrjala@linux.intel.com
2022-06-01drm/i915/display: stop using BUG()Jani Nikula3-19/+26
Avoid bringing the entire machine down even if there's a bug that shouldn't happen, but won't corrupt the system either. Log them loudly and limp on. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220531162527.1062319-1-jani.nikula@intel.com
2022-05-31drm/i915/pvc: Add initial PVC workaroundsStuart Summers4-12/+73
Bspec: 64027 Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220527163348.1936146-3-matthew.d.roper@intel.com
2022-05-31drm/i915/pvc: Extract stepping information from PCI revidMatt Roper3-2/+85
For PVC, the base die and compute tile have separate stepping values that we need to track; we'll use the existing graphics_step field to represent the compute tile stepping and add a new 'basedie_step' field. Unlike past platforms, steppings for these components are represented by specific bitfields within the PCI revision ID, and we shouldn't make assumptions about the non-CT, non-BD bits staying 0. Let's update our stepping code accordingly. Bspec: 44484 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220527163348.1936146-2-matthew.d.roper@intel.com
2022-05-31drm/nouveau/fifo/gv100-: set gv100_fifo_runlist storage-class to staticTom Rix1-1/+1
sparse reports drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c:56:1: warning: symbol 'gv100_fifo_runlist' was not declared. Should it be static? gv100_fifo_runlist is only used in gv100.c, so change it to static. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220528141836.4155970-1-trix@redhat.com
2022-05-31drm/i915: Require an exact DP link freq match for the DG2 PLLVille Syrjälä1-1/+1
No idea why the DG2 PLL DP link frequency calculation is allowing a non-exact match. That makes no sense so get rid of it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Matt Roper <matthew.d.roper@intel.com>
2022-05-31drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare()Ville Syrjälä1-2/+4
Don't see a real reson not to check hw.active and hw.enable in intel_pipe_config_compare(). We do have some checks for them at a higher level, but I think better check them also in intel_pipe_config_compare() in case something else doesn't do a thorough enough job. Also shuffle the mst_master_transcoder check next to the cpu_transcoder check for a bit of consistency. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-21-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: Improve modeset debugsVille Syrjälä1-8/+14
Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs so we know more about what has happened during the modeset state computation. Also tweak the connector bpp debug message a bit to make it less confusing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: s/pipe_config/crtc_state/Ville Syrjälä1-31/+31
Rename some of the 'pipe_config's to the more modern 'crtc_state'. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: Adjust intel_modeset_pipe_config() & co. calling conventionVille Syrjälä1-23/+25
Use the state+crtc calling convention for intel_modeset_pipe_config() and othere related functions. Many of these need the full atomic state anyway so passing it all the way through is just nicer than having to worry about whether it can actually be extracted from eg. the crtc state passed in. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: Extract PIPE_CONF_CHECK_RECT()Ville Syrjälä1-10/+10
Deduplicate the drm_rect comparisons. We also drop the redundant pch_pfit.enabled check since the pch_pfit.dst rectanble will be zeroed anyway when the pfit is not enabled. v2: Document why we drop the enabled check (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()Ville Syrjälä1-27/+18
Deduplicate the crtc_ timings comparisons. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915: Clean up DPLL related debugsVille Syrjälä2-88/+35
The debugs in lower level DPLL code don't really provide any useful extra information AFAICS. Better just streamline the code and just put the necessary debugs (to identify at which step the modeset failed) into the higher level code. In addition we'll get the full state dump as well, which should hopefully have enough information to figure out what went wrong. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-4-ville.syrjala@linux.intel.com
2022-05-31drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä3-68/+230
Split the DPLL state computation into a separate function from the current .get_dplls() which currently serves a dual duty by also reserving the shared DPLLs. v2: s/false/-EINVAL/ (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-31drm/i915/tc: Don't default disconnected legacy Type-C ports to TBT mode (v2)Vivek Kasireddy1-1/+2
Commit 30e114ef4b16 ("drm/i915/tc: Check for DP-alt, legacy sinks before taking PHY ownership") defaults any disconnected Type-C ports to TBT-alt mode which presents a problem (which could most likely result in a system hang) when userspace forces a modeset on a Type-C port that is wired for legacy HDMI. The following warning is seen when Weston forces a modeset on a disconnected legacy Type-C port (HDMI) on a TGL based Gigabyte system: (https://www.gigabyte.com/Mini-PcBarebone/GB-BSi3-1115G4-rev-10#ov) Missing case (clock == 173000) WARNING: CPU: 1 PID: 438 at drivers/gpu/drm/i915/display/intel_ddi.c:245 icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915] CPU: 1 PID: 438 Comm: kworker/u8:3 Tainted: G U W E 5.18.0-rc5-drm-tip+ #20 Hardware name: GIGABYTE GB-BSi3-1115G4/GB-BSi3-1115G4, BIOS F9 10/16/2021 Workqueue: i915_modeset intel_atomic_commit_work [i915] RIP: 0010:icl_ddi_tc_enable_clock.cold+0x16a/0x1cf [i915] Code: 74 6c 7f 10 81 fd d0 78 02 00 74 6d 81 fd b0 1e 04 00 74 70 48 63 d5 48 c7 c6 c0 7b ab c0 48 c7 c7 20 75 ab c0 e8 b8 b5 c1 f0 <0f> 0b 45 31 ed e9 fb fe ff ff 49 63 d5 48 c7 c6 80 7b ab c0 48 c7 RSP: 0018:ffff8882522c78f0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000000 RDX: 0000000000000027 RSI: 0000000000000004 RDI: ffffed104a458f10 RBP: 0000000000011558 R08: ffffffffb078de4e R09: ffff888269ca748b R10: ffffed104d394e91 R11: 0000000000000000 R12: ffff888255a318f8 R13: 0000000000000002 R14: ffff888255a30000 R15: ffff88823ef00348 FS: 0000000000000000(0000) GS:ffff888269c80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fd7afa42000 CR3: 0000000255c02004 CR4: 00000000007706e0 PKRU: 55555554 Call Trace: <TASK> intel_ddi_pre_enable.cold+0x96/0x5bf [i915] intel_encoders_pre_enable+0x10e/0x140 [i915] hsw_crtc_enable+0x207/0x99d [i915] ? ilk_crtc_enable.cold+0x2a/0x2a [i915] ? prepare_to_wait_exclusive+0x120/0x120 intel_enable_crtc+0x9a/0xf0 [i915] skl_commit_modeset_enables+0x466/0x820 [i915] ? intel_commit_modeset_enables+0xd0/0xd0 [i915] ? intel_mbus_dbox_update+0x1ed/0x250 [i915] intel_atomic_commit_tail+0xf2d/0x3040 [i915] _raw_spin_lock_irqsave+0x87/0xe0 _raw_read_unlock_irqrestore+0x40/0x40 __update_load_avg_cfs_rq+0x70/0x5c0 __i915_sw_fence_complete+0x85/0x3b0 [i915] ? intel_get_crtc_new_encoder+0x190/0x190 [i915] ? sysvec_irq_work+0x13/0x90 ? asm_sysvec_irq_work+0x12/0x20 ? _raw_spin_lock_irq+0x82/0xd0 ? read_word_at_a_time+0xe/0x20 ? process_one_work+0x393/0x690 process_one_work+0x393/0x690 worker_thread+0x2b7/0x620 ? process_one_work+0x690/0x690 kthread+0x15a/0x190 ? kthread_complete_and_exit+0x20/0x20 ret_from_fork+0x1f/0x30 Continuing with the modeset without setting the DDI clock results in more warnings and eventually a system hang. This does not seem to happen with disconnected legacy or DP-alt DP ports because the clock rate defaults to 162000 (which is a valid TBT clock) during the link training process. Therefore, to fix this issue, this patch avoids setting disconnected Type-C legacy ports to TBT-alt mode which prevents the selection of TBT PLL when a modeset is forced. v2: (Imre) - Retain the check for legacy hotplug live status to account for incorrect VBTs. Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220526001939.4031112-2-vivek.kasireddy@intel.com
2022-05-30drm/hyperv : Removing the restruction of VRAM allocation with PCI bar sizeSaurabh Sengar1-71/+3
There were two different approaches getting used in this driver to allocate vram: 1. VRAM allocation from PCI region for Gen1 2. VRAM alloaction from MMIO region for Gen2 First approach limilts the vram to PCI BAR size, which is 64 MB in most legacy systems. This limits the maximum resolution to be restricted to 64 MB size, and with recent conclusion on fbdev issue its concluded to have similar allocation strategy for both Gen1 and Gen2. This patch unifies the Gen1 and Gen2 vram allocation strategy. Signed-off-by: Saurabh Sengar <ssengar@linux.microsoft.com> Reviewed-by: Deepak Rawat <drawat.floss@gmail.com> Signed-off-by: Deepak Rawat <drawat.floss@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/1653143019-20032-1-git-send-email-ssengar@linux.microsoft.com
2022-05-30drm: use dma_fence_unwrap_merge() in drm_syncobjChristian König1-50/+7
The unwrap merge function is now intended for this use case. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20220518135844.3338-6-christian.koenig@amd.com
2022-05-30drm/mipi-dbi: align max_chunk to 2 in spi_transferYunhao Tian1-0/+7
In __spi_validate, there's a validation that no partial transfers are accepted (xfer->len % w_size must be zero). When max_chunk is not a multiple of bpw (e.g. max_chunk = 65535, bpw = 16), the transfer will be rejected. This patch aligns max_chunk to 2 bytes (the maximum value of bpw is 16), so that no partial transfer will occur. Fixes: d23d4d4dac01 ("drm/tinydrm: Move tinydrm_spi_transfer()") Signed-off-by: Yunhao Tian <t123yh.xyz@gmail.com> Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220510030219.2486687-1-t123yh.xyz@gmail.com
2022-05-28Merge tag 'hyperv-next-signed-20220528' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linuxLinus Torvalds2-17/+11
Pull hyperv updates from Wei Liu: - Harden hv_sock driver (Andrea Parri) - Harden Hyper-V PCI driver (Andrea Parri) - Fix multi-MSI for Hyper-V PCI driver (Jeffrey Hugo) - Fix Hyper-V PCI to reduce boot time (Dexuan Cui) - Remove code for long EOL'ed Hyper-V versions (Michael Kelley, Saurabh Sengar) - Fix balloon driver error handling (Shradha Gupta) - Fix a typo in vmbus driver (Julia Lawall) - Ignore vmbus IMC device (Michael Kelley) - Add a new error message to Hyper-V DRM driver (Saurabh Sengar) * tag 'hyperv-next-signed-20220528' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: (28 commits) hv_balloon: Fix balloon_probe() and balloon_remove() error handling scsi: storvsc: Removing Pre Win8 related logic Drivers: hv: vmbus: fix typo in comment PCI: hv: Fix synchronization between channel callback and hv_pci_bus_exit() PCI: hv: Add validation for untrusted Hyper-V values PCI: hv: Fix interrupt mapping for multi-MSI PCI: hv: Reuse existing IRTE allocation in compose_msi_msg() drm/hyperv: Remove support for Hyper-V 2008 and 2008R2/Win7 video: hyperv_fb: Remove support for Hyper-V 2008 and 2008R2/Win7 scsi: storvsc: Remove support for Hyper-V 2008 and 2008R2/Win7 Drivers: hv: vmbus: Remove support for Hyper-V 2008 and Hyper-V 2008R2/Win7 x86/hyperv: Disable hardlockup detector by default in Hyper-V guests drm/hyperv: Add error message for fb size greater than allocated PCI: hv: Do not set PCI_COMMAND_MEMORY to reduce VM boot time PCI: hv: Fix hv_arch_irq_unmask() for multi-MSI Drivers: hv: vmbus: Refactor the ring-buffer iterator functions Drivers: hv: vmbus: Accept hv_sock offers in isolated guests hv_sock: Add validation for untrusted Hyper-V values hv_sock: Copy packets sent by Hyper-V out of the ring buffer hv_sock: Check hv_pkt_iter_first_raw()'s return value ...
2022-05-27drm/i915/bios: Determine panel type via PNPID matchVille Syrjälä7-19/+95
Apparently when the VBT panel_type==0xff we should trawl through the PNPID table and check for a match against the EDID. If a match is found the index gives us the panel_type. Tried to match the Windows behaviour here with first looking for an exact match, and if one isn't found we fall back to looking for a match w/o the mfg year/week. v2: Rebase due to vlv_dsi changes v3: Adjust to .get_panel_type() vfunc Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5545 Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-14-ville.syrjala@linux.intel.com
2022-05-27drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä21-331/+391
Move the panel specific VBT parsing to happen during the output probing stage. Needs to be done because the VBT parsing will need to look at the EDID to determine the correct panel_type on some machines. We split the parsed VBT data (i915->vbt) along the same boundary. For the moment we just hoist all the panel specific stuff into connector->panel.vbt since that seems like the most convenient place for eg. the backlight code. Note that we simply drop the drrs type check from intel_drrs_frontbuffer_update() since that operates on the whole device rather than a specific connector/encoder. But the check was just a micro optimization so removing it doesn't actually mattter for correctness. TODO: Lot's of cleanup to be done in the future. Eg. most of the DSI stuff could probably be eliminated entirely and just parsed on demand during DSI init. v2: Note the intel_drrs_frontbuffer_update() change Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-13-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/bios: Split VBT parsing to global vs. panel specific partsVille Syrjälä3-11/+17
Parsing the panel specific data (anything that depends on panel_type) from VBT is currently happening too early. Split the whole thing into global vs. panel specific parts so that we can start doing the panel specific parsing at a later time. v2: Clarify that this is about panel_type (Jani) Split out the leak checks (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-12-ville.syrjala@linux.intel.com
2022-05-27drm/i915/bios: Split parse_driver_features() into two partsVille Syrjälä1-0/+11
We use the "driver features" block for two different kinds of data: global data, and per panel data. Split the function into two parts along that line so that we can start doing the parsing in two different locations. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-11-ville.syrjala@linux.intel.com
2022-05-27drm/i915/pps: Keep VDD enabled during eDP probeVille Syrjälä2-0/+11
Disable the delayed VDD off work during the eDP probe. If we never turn off the VDD then we can't violate the panel's power sequencing delays despite not having read them out yet from the VBT. This is mostly a belt+suspenders type of thing since the the timeout we'd use for the delayed work should be long enough that this won't normally happen. But I don't really like relying on timeouts for correctless so might as well make sure. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Reinit PPS delays after VBT has been fully parsedVille Syrjälä1-0/+5
During the eDP probe we may not yet know the panel_type used to index the VBT panel tables. So the initial eDP probe will have to be done without that, and thus we won't yet have the PPS delays from the VBT. Once the VBT has been fully parse we should reinit the PPS delays to make sure it's fully accounted for. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Split PPS init+sanitize in twoVille Syrjälä3-5/+28
Split the PPS init to something we do at the start of the eDP probe and a second part we do at the end. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Stash away original BIOS programmed PPS delaysVille Syrjälä2-5/+9
In order to do the panel VBT parsing after the EDID read (needed to determine panel_type from PNPID) we need to stash away the original BIOS programmed PPS delays so that we can consult them again when we reinit the PPS delays after the VBT parsing has been done. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Don't apply quirks/etc. to the VBT PPS delays if they haven't been initializedVille Syrjälä1-0/+3
Skip QUIRK_INCREASE_T12_DELAY and the t11_t12 adjustment of the VBT PPS delays if we've not yet initialized them. Will be important later when the PPS delay init can happen before VBT parsing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Introduce pps_delays_valid()Ville Syrjälä1-1/+7
Add a small helper that determines if the PPS delays have been initialized or not. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/pps: Split pps_init_delays() into distinct partsVille Syrjälä1-18/+48
Split each of the hw/vbt/spec PPS delay initialization into separate functions to make the whole thing less cluttered. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915: Extract intel_edp_fixup_vbt_bpp()Ville Syrjälä4-40/+30
We have the same "override eDP VBT bpp with the current bpp" code duplciated in two places. Extract it to a helper function. TODO: Having this in .get_config() is pretty ugly. Should probably try to move it somewhere else (setup_hw_state()/etc.)... Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915: Pass intel_connector to intel_vrr_is_capable()Ville Syrjälä3-10/+10
Pass intel_connector instead of drm_connector to intel_vrr_is_capable(). Will result in less ugly casts. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220510104242.6099-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2022-05-27drm/i915/display/adl_p: Updates to HDMI combo PHY voltage swing tableBalasubramani Vivekanandan1-21/+1
New updates to HDMI combo PHY voltage swing tables. Actually with this update (bspec updated on 08/17/2021), the values are reverted back to be same as icelake for HDMI combo PHY. Bspec: 49291 Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220526064935.969225-1-balasubramani.vivekanandan@intel.com
2022-05-27drm/i915: Individualize fences before adding to dma_resv objNirmoy Das2-21/+30
_i915_vma_move_to_active() can receive > 1 fences for multiple batch buffers submission. Because dma_resv_add_fence() can only accept one fence at a time, change _i915_vma_move_to_active() to be aware of multiple fences so that it can add individual fences to the dma resv object. v6: fix multi-line comment. v5: remove double fence reservation for batch VMAs. v4: Reserve fences for composite_fence on multi-batch contexts and also reserve fence slots to composite_fence for each VMAs. v3: dma_resv_reserve_fences is not cumulative so pass num_fences. v2: make sure to reserve enough fence slots before adding. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614 Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf") Cc: <stable@vger.kernel.org> # v5.16+ Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220525095955.15371-1-nirmoy.das@intel.com
2022-05-26Merge tag 'mm-stable-2022-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mmLinus Torvalds3-3/+3
Pull MM updates from Andrew Morton: "Almost all of MM here. A few things are still getting finished off, reviewed, etc. - Yang Shi has improved the behaviour of khugepaged collapsing of readonly file-backed transparent hugepages. - Johannes Weiner has arranged for zswap memory use to be tracked and managed on a per-cgroup basis. - Munchun Song adds a /proc knob ("hugetlb_optimize_vmemmap") for runtime enablement of the recent huge page vmemmap optimization feature. - Baolin Wang contributes a series to fix some issues around hugetlb pagetable invalidation. - Zhenwei Pi has fixed some interactions between hwpoisoned pages and virtualization. - Tong Tiangen has enabled the use of the presently x86-only page_table_check debugging feature on arm64 and riscv. - David Vernet has done some fixup work on the memcg selftests. - Peter Xu has taught userfaultfd to handle write protection faults against shmem- and hugetlbfs-backed files. - More DAMON development from SeongJae Park - adding online tuning of the feature and support for monitoring of fixed virtual address ranges. Also easier discovery of which monitoring operations are available. - Nadav Amit has done some optimization of TLB flushing during mprotect(). - Neil Brown continues to labor away at improving our swap-over-NFS support. - David Hildenbrand has some fixes to anon page COWing versus get_user_pages(). - Peng Liu fixed some errors in the core hugetlb code. - Joao Martins has reduced the amount of memory consumed by device-dax's compound devmaps. - Some cleanups of the arch-specific pagemap code from Anshuman Khandual. - Muchun Song has found and fixed some errors in the TLB flushing of transparent hugepages. - Roman Gushchin has done more work on the memcg selftests. ... and, of course, many smaller fixes and cleanups. Notably, the customary million cleanup serieses from Miaohe Lin" * tag 'mm-stable-2022-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm: (381 commits) mm: kfence: use PAGE_ALIGNED helper selftests: vm: add the "settings" file with timeout variable selftests: vm: add "test_hmm.sh" to TEST_FILES selftests: vm: check numa_available() before operating "merge_across_nodes" in ksm_tests selftests: vm: add migration to the .gitignore selftests/vm/pkeys: fix typo in comment ksm: fix typo in comment selftests: vm: add process_mrelease tests Revert "mm/vmscan: never demote for memcg reclaim" mm/kfence: print disabling or re-enabling message include/trace/events/percpu.h: cleanup for "percpu: improve percpu_alloc_percpu event trace" include/trace/events/mmflags.h: cleanup for "tracing: incorrect gfp_t conversion" mm: fix a potential infinite loop in start_isolate_page_range() MAINTAINERS: add Muchun as co-maintainer for HugeTLB zram: fix Kconfig dependency warning mm/shmem: fix shmem folio swapoff hang cgroup: fix an error handling path in alloc_pagecache_max_30M() mm: damon: use HPAGE_PMD_SIZE tracing: incorrect isolate_mote_t cast in mm_vmscan_lru_isolate nodemask.h: fix compilation error with GCC12 ...
2022-05-26drm/amdgpu: add drm-client-id to fdinfo v2Christian König1-8/+7
This is enough to get gputop working :) v2: rebase and some addition cleanup Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdgpu: Convert to common fdinfo format v5Christian König3-121/+125
Convert fdinfo format to one documented in drm-usage-stats.rst. It turned out that the existing implementation was actually completely nonsense. The calculated percentages indeed represented the usage of the engine, but with varying time slices. So 10% usage for application A could mean something completely different than 10% usage for application B. Completely nuke that and just use the now standardized nanosecond interface. v2: drop the documentation change for now, nuke percentage calculation v3: only account for each hw_ip, move the time_spend to the ctx mgr. v4: move general ctx changes into separate patch, rework the fdinfo to ctx_mgr interface so that all usages are calculated at once, drop some unecessary and dangerous refcount dance. v5: add one more comment how we calculate the time spend Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdgpu: bump minor version numberChristian König1-2/+3
Increase the minor version number to indicate that the new flags are available. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdgpu: add AMDGPU_VM_NOALLOC v2Christian König3-1/+10
Add the AMDGPU_VM_NOALLOC flag to let userspace control MALL allocation. v2: also add the flag to the allowed flags. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdgpu: add AMDGPU_GEM_CREATE_DISCARDABLEChristian König5-5/+5
Add a AMDGPU_GEM_CREATE_DISCARDABLE flag to note that the content of a BO doesn't needs to be preserved during eviction. KFD was already using a similar functionality for SVM BOs so replace the internal flag with the new UAPI. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdgpu: add beige goby PCI IDAlex Deucher1-0/+1
Add a beige goby PCI ID. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2022-05-26drm/amd/pm: Return auto perf level, if unsupportedLijo Lazar1-0/+3
When powerplay is not enabled, return AUTO as default level. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-05-26drm/amdkfd: fix typo in commentJulia Lawall1-1/+1
Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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