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2014-09-25Merge branch 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux into drm-fixesDave Airlie8-26/+63
- fix a backlight regression resulting in dark screen - add a PX quirk to avoid a hang with runtime pm - fix an init issue on the CIK compute rings - fix IH ring buffer overflows gracefully * 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux: drm/radeon/cik: use a separate counter for CP init timeout drm/radeon: add PX quirk for asus K53TK drm/radeon: add a backlight quirk for Amilo Xi 2550 drm/radeon: add a module parameter for backlight control (v2) drm/radeon: Update IH_RB_RPTR register after each processed interrupt drm/radeon: Make IH ring overflow debugging output more useful drm/radeon: Clear RB_OVERFLOW bit earlier
2014-09-24drm/i915: Avoid re-configure panel on every PSR re-enable.Rodrigo Vivi1-4/+4
The panel has to be reconfigured only when it really loose the power. The traditional enable/disable sequence already take care of this so we can minimize the time spend on every re-enable. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24PCI: Move PCI_VENDOR_ID_VMWARE to pci_ids.hFrancesco Ruggeri1-1/+0
Move PCI_VENDOR_ID_VMWARE from device-specific files to pci_ids.h. It is useful to always have access to it, especially when accessing subsystem_vendor_id on emulated devices. [bhelgaas: keep pci_ids.h sorted and use lower-case hex] Signed-off-by: Francesco Ruggeri <fruggeri@arista.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau1-3/+3
Gen9 is different enough (for instance, fetching the memory latency values is different from ILK+) to not take the HAS_PCH_SPLIT() branch, so let's prefer a clean separation. v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Introduce intel_num_planes()Damien Lespiau1-0/+8
It can be handy to get the number of planes for this pipe, ie including the primary plane to loop over them. Introduce a little function to do so. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Introduce a I915_MAX_PLANES macroDamien Lespiau1-0/+8
This can be useful to declare structures around pipes and planes and don't have to go back auditing the code if the next platorm bump that number. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Adjust assert_sprites_disabled()Damien Lespiau1-1/+8
Let's put to good use the new PLANE_CTL macros. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement drm_plane vfuncsDamien Lespiau2-1/+234
SKL Uses the same hardware for all planes now, so called "universal" planes. Ie both the primary planes and sprite planes share the same logic. This patch implements the drm_plane vfuncs for "sprites" ie planes that aren't the primary plane. v2: Couple of fixes: - Actually enabled the planes and fix the plane number Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake has 2 "sprite" planes per pipeDamien Lespiau1-1/+1
On Skylake, we use plane1 as primary plane and plane2/3 as sprite planes. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau2-0/+11
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau1-0/+4
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau1-0/+8
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Sunrise Point PCH detectionSatheeshakrishna M2-0/+14
This patch implements detection of SPT and SPT-LP PCH devices. v2: Added HAS_PCH_SPT macro Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Adjust the display engine interruptsDamien Lespiau2-9/+41
To accomodate the extra planes, the bit definitions were shuffled around a bit. v2: Rebase on top of the for_each_pipe() change adding dev_priv as first argument. v3: Rebase after yet another change int that area (done with wiggle) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M1-1/+1
Extending BDW implementation to gen9. Pipe B/C interrupt restoration after exiting LPSP. v2: Fix minor rebasing conflict. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL backlight enablingSatheeshakrishna M1-1/+1
Extending the BDW backlight implementation to SKL. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: vfuncs for skl eld and global resourceSatheeshakrishna M1-0/+4
Set gen 9 function pointers for eld write and global resource. Implementation remains same as HSW. v2: Rebase on top of Sonika's untangling of the if/else ladder (Damien) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL pipe misc programmingSatheeshakrishna M1-1/+1
Pipe misc programming in gen9 is similar to BDW. Extending the BDW implementation to gen 9. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL shares the same underrun interrupt as BDWDamien Lespiau1-1/+1
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Report the PDP regs as in gen8Damien Lespiau1-0/+1
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: report the same INSTDONE registers as gen8Damien Lespiau1-0/+1
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMPDamien Lespiau1-1/+1
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Initialize PPGTT like gen8Damien Lespiau1-1/+1
gen9 uses very similar memory management to what gen8 has. Just follow the flow. v2: Fix trivial conflict (Damien) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylakeDamien Lespiau2-1/+20
Skylake doesn't use the pre-charge field now, but, instead, we need to specify the total number of SYNC pulses for the SYNC phase (pre-charge + SYNC pattern pules). Let's use the default value (32) for that. v3: increase DP AUX TX timeout as 400us is not to be used on SKL apparently (Jesse). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement the get_aux_clock_divider() DP vfuncDamien Lespiau1-1/+13
We need to provide a vfunc that will make the code in intel_dp_aux_ch() loop once to start the AUX transaction. The return value (clock divider) is unused on SKL, so just return 1. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+Damien Lespiau1-0/+1
Temporary plug a BUG() while waiting for a better solution. See: http://lists.freedesktop.org/archives/intel-gfx/2014-January/038132.html However Chris was looking at cleaning-up this as well, so went for the easy intermediate solution instead. Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add the additional graphics stolen sizesDamien Lespiau1-1/+16
Skylake introduces new stolen memory sizes starting at 0xf0 (4MB) and growing by 4MB increments from there. v2: Rebase on top of the early-quirk changes from Ville. v3: Rebase on top of the PCI_IDS/IDS macro rename Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake moves AUX_CTL from PCH to CPUDamien Lespiau1-1/+10
So we can apply the old aux_ctl = dp_ctl + 0x10 rule again. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add support for DP voltage swings and pre-emphasisDamien Lespiau1-3/+16
They are similar to Haswell. v2: Rebased on top of drm-intel-nightly v3: Rebased on top of Sonika's DP train defines renaming Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Program the DDI buffer translation tablesDamien Lespiau1-2/+38
A couple of things have changed compared to Broadwell: - Entry 9 is used for eDP - No more FDI v2: Update the translation values to latest specs. v3: Rebase on top of the BDW HDMI translation patch v4: Remove the low voltage edp tables, Rebase on top of the patch not writing the HDMI entry on eDP/FDI DDIs (Satheesh, Paulo). v5: Apply the / 2 fix for the number of HDMI entries (Satheesh) v6: Rebase on top of Jani's clean up for the DDI_BUF_TRANS tables v7: Restore the commit message that was mangled by error Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Don't try to read out the PCH transcoder state if not presentDamien Lespiau1-1/+2
When the platform doesn't have a FDI link, don't try to read out the state of a potential PCH transcoder. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Don't open-code HAS_FDI if there's only one place that needs it. Acked by Damien on irc.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Don't create a VGA connector on SkylakeDamien Lespiau1-0/+3
v2: Rebase on top of the intel_crt_present() addition v3: Fix rebase error (we were patching the wrong function) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Implement the new update_plane() for primary planesDamien Lespiau2-3/+199
Skylake makes primary planes the same as sprite planes and call the result "universal planes". This commit emulates a primary plane with plane 0, taking the opportunity to redefine primary and sprite registers to be identical now that the underlying hardware is. It also makes sense as plenty of fields have changed. v2: Rebase on top of the vma code. v3: Follow upstream evolution: - Drop return values. - Remove pipe checks since redudant and BUG instead. - Remove tiling checks and BUG instead. - Drop commented out DISP_MODIFY usage. v4: s/plane/primary_plane/ v5: Misc fixes: - Fix the fields we need to clear up - Disable trickle feed - Correctly use PLANE_OFFSET for the panning v6: (Jesse) Use pipe src size when programming plane size. This makes cloned configs work correctly w/o the use of a panel fitter. v7: Rebase on top of Ville's rmw elimination series v8: Remove clearing the trickle feed bit now that we don't do a RMW (Rodrigo, Damien) Add a comment about the stride unit (Rodrigo) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1,5,6,7) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2,3) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: i915_swizzle_info gen9 fixRobert Beckett1-1/+1
Fix ARB_MODE register read for gen >= 8 in i915_swizzle_info Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Robert Beckett <robert.beckett@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-24drm/i915/skl: Framebuffers need to be aligned to 256KB on SkylakeDamien Lespiau1-3/+9
v2: Also align X tiled fbs to 256KB (Thomas) Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+Imre Deak1-1/+1
The following sets the AsyncFlip performance mode for everything above Gen6: commit 4790cb36b3eede8fb0cca529dc1d31b9936fa24b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jan 20 16:11:20 2013 +0000 drm/i915: Disable AsyncFlip performance optimisations Starting from Gen9 the MI_MODE register layout changes and doesn't include the above bit. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Skylake shares the interrupt logic with BroadwellDamien Lespiau1-1/+1
Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau1-0/+6
v2: Rebase on top of the broadwell_init_clock_gating() name change Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Fence registers on SKL are the same as SNBDamien Lespiau2-0/+2
v2: Rebased on top of the i915_gpu_error.c extraction. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: SKL FBC enablementDaisy Sun1-0/+1
Enable FBC feature on Skylake Issue: VIZ-3788 Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daisy Sun <daisy.sun@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add an IS_SKYLAKE macroSatheeshakrishna M2-0/+3
Adding new macro IS_SKYLAKE for skylake specific implementation. Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add an IS_GEN9() defineDamien Lespiau1-0/+1
Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/i915/skl: Add the Skylake PCI idsDamien Lespiau1-1/+13
v2: Squash in 2nd patch from Damien for more ids (Daniel) v3: info->has*ring -> info->ring_mask conversion. Also add VEBOX support. v4: Fold in update from Damien v5: Rebase and add GEN_DEFAULT_PIPEOFFSETS v6: Add more PCI ID (Vandana) v7: Rebase and add IVB_CURSOR_OFFSETS v8: Renamed the macro from _PCI_IDS to _IDS for consistency Reviewed-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/udl: use container_of to resolve udl_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/ast: use container_of to resolve ast_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/gma500: use container_of to resolve psb_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/qxl: use container_of to resolve qxl_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/nouveau: use container_of to resolve nouveau_plane from drm_planeFabian Frederick1-5/+10
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/nouveau: use container_of to resolve nouveau_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-24drm/radeon: use container_of to resolve radeon_fbdev from drm_fb_helperFabian Frederick1-1/+2
Use container_of instead of casting first structure member. Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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