aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2020-08-03drm/ast: Separate DRM driver from PCI codeThomas Zimmermann1-28/+31
Putting the DRM driver to the top of the file and the PCI code to the bottom makes ast_drv.c more readable. While at it, the patch prefixes file-scope variables with ast_. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200730135206.30239-3-tzimmermann@suse.de
2020-08-03drm/ast: Embed CRTC and connector in struct ast_privateThomas Zimmermann2-41/+26
Only single instances of CRTC and connector are supported per device. Embed both in ast's structure and remove the individual memory allocations. DRM's CRTC cleanup helpers replace the rsp. destroy function in ast. While at it, also convert to_ast_connector() to a function. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200730135206.30239-2-tzimmermann@suse.de
2020-08-02drm/syncobj: Tune down unordered timeline DRM_ERRORDaniel Vetter1-1/+1
Userspace can provoke this, we generally don't allow userspace to spam dmesg. Tune it down to debug. Unfortunately we don't have easy access to the drm_device here (not at all without changing a few things), so leave it as old style dmesg output for now. References: https://patchwork.freedesktop.org/series/80146/ Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "Christian König" <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200801092625.1107609-1-daniel.vetter@ffwll.ch
2020-08-02drm/vkms: fix xrgb on compute crcMelissa Wen1-1/+1
The previous memset operation was not correctly zeroing the alpha channel to compute the crc, and as a result, the IGT subtest kms_cursor_crc/pipe-A-cursor-alpha-transparent fails. Fixes: db7f419c06d7c ("drm/vkms: Compute CRC with Cursor Plane") Signed-off-by: Melissa Wen <melissa.srw@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20200730202524.5upzuh4irboru7my@smtp.gmail.com
2020-08-02drm/panel: simple: Add Chefree CH101OLHLWH-002 panelMarek Vasut1-0/+33
Add support for the Chefree CH101OLHLWH-002 10.1" (1280x800) color TFT LCD panel, connected over LVDS. Timings are taken from the datasheet version P0.5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: dri-devel@lists.freedesktop.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: devicetree@vger.kernel.org Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200728201242.4336-3-marex@denx.de
2020-08-02drm/panel: remove return value of function drm_panel_addBernard Zhao43-110/+81
The function "int drm_panel_add(struct drm_panel *panel)" always returns 0, this return value is meaningless. Also, there is no need to check return value which calls "drm_panel_add and", error branch code will never run. Signed-off-by: Bernard Zhao <bernard@vivo.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200801120216.8488-1-bernard@vivo.com
2020-08-01vgaarb: mark vga_tryget staticChristoph Hellwig1-2/+1
This symbols isn't used anywhere outside of vgaarb.c. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20200801061713.307434-1-hch@lst.de
2020-08-01drm: xlnx: zynqmp: Use switch - case for link rate downshiftHyun Kwon1-13/+16
Use switch - case to downshift from the current link rate. It's a small loop now, so fine to be replaced with switch - case. With a loop, it is confusing and hard to follow as reported below. The patch d76271d22694: "drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem" from Jul 7, 2018, leads to the following static checker warning: drivers/gpu/drm/xlnx/zynqmp_dp.c:594 zynqmp_dp_mode_configure() error: iterator underflow 'bws' (-1)-2 Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/1596065445-4630-1-git-send-email-hyun.kwon@xilinx.com
2020-07-31Merge remote-tracking branch 'asoc/for-5.9' into asoc-nextMark Brown7-18/+28
2020-07-31drm/ttm: remove the init_mem_type callbackChristian König7-47/+0
It is a very strange concept to call a function which just calls back the caller for the functions parameters. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382085/
2020-07-31drm/vram-helper: stop implementing init_mem_typeChristian König1-12/+4
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382086/
2020-07-31drm/qxl: stop implementing init_mem_typeChristian König1-19/+16
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382083/
2020-07-31drm/nouveau: stop implementing init_mem_typeChristian König2-52/+57
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382081/
2020-07-31drm/vmwgfx: stop implementing init_mem_type v2Christian König2-28/+20
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. v2: keep extra system domain handling Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382082/
2020-07-31drm/amdgpu: stop implementing init_mem_typeChristian König1-53/+43
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382084/
2020-07-31drm/radeon: stop implementing init_mem_typeChristian König1-35/+35
Instead just initialize the memory type parameters before calling ttm_bo_init_mm. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382080/
2020-07-31drm/ttm: remove TTM_MEMTYPE_FLAG_FIXED v2Christian König8-26/+21
Instead use a boolean field in the memory manager structure. Also invert the meaning of the field since the use of a TT structure is the special case here. v2: cleanup zero init. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/382079/
2020-07-31drm/ttm: initialize the system domain with defaults v2Christian König7-16/+2
Instead of repeating that in each driver. v2: keep the caching limitation for VMWGFX for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/382078/
2020-07-31drm/msm: use kthread_create_worker instead of kthread_runBernard3-15/+8
Use kthread_create_worker to simplify the code and optimise the manager struct: msm_drm_thread. With this change, we could remove struct element (struct task_struct *thread & struct kthread_worker worker), instead, use one point (struct kthread_worker *worker). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/mdp5: Add MDP5 configuration for SDM636/660Konrad Dybcio1-0/+105
This commit adds support for the MDP5 IP on Snapdragon 636/660. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dsi: Add DSI configuration for SDM660Konrad Dybcio2-0/+22
This also applies to sdm630/636 and their SDA counterparts. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/mdp5: Add MDP5 configuration for SDM630Konrad Dybcio1-0/+93
This commit adds support for the MDP5 IP on Snapdragon 630. The configuration is different from SDM660's, as the latter one has two DSI outputs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dsi: Add phy configuration for SDM630/636/660Konrad Dybcio3-0/+21
These SoCs make use of the 14nm phy, but at different addresses than other 14nm units. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add A640/A650 hwcgJonathan Marek3-4/+117
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: hwcg tables in gpulistJonathan Marek3-14/+20
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8250 to hw catalogJonathan Marek2-0/+109
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8150 to hw catalogJonathan Marek2-0/+149
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: intf timing path for displayportJonathan Marek1-5/+15
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3Jonathan Marek1-18/+2
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845Jonathan Marek3-15/+27
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: move some sspp caps to dpu_capsJonathan Marek3-27/+17
This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: update UBWC config for sm8150 and sm8250Jonathan Marek6-90/+42
Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250Jonathan Marek1-3/+2
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: set ubwc config for A640 and A650Jonathan Marek1-6/+32
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: un-open-code some packetsRob Clark2-6/+10
Small cleanup, lets not open-code bits/bitfields that are properly defined in the rnndb xml (and therefore have builders in the generated headers) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: sync generated headersRob Clark18-1183/+5883
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add build_bw_table for A640/A650Jonathan Marek1-0/+74
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: fix crashstate capture for A650Jonathan Marek3-11/+31
A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Quiet error during failure in optional resource mappings.Eric Anholt3-6/+22
We don't expect to find vbif_nrt or regdma on sdm845, but were clogging up dmesg with errors about it. Signed-off-by: Eric Anholt <eric@anholt.net> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Garbage collect unused resource _len fields.Eric Anholt3-31/+0
Nothing was using the lengths of these ioremaps. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: fix/enable 6bpc dither with split-lmRob Clark2-12/+13
If split-lm is used (for ex, on sdm845), we can have multiple ping- pongs, but only a single phys encoder. We need to configure dithering on each of them. Signed-off-by: Rob Clark <robdclark@chromium.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: fix gpu failure after system resumeAkhil P Oommen1-8/+10
On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, move the refcount-get on GX PD before we initialize the GMU. This ensures that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen during GPU wake up during a system resume. Reported-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: dsi: Use OPP API to set clk/perf stateRajendra Nayak1-2/+25
On SDM845 and SC7180 DSI needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate() for devices without an OPP table, hence the change works fine on devices/platforms which only need to set a clock rate. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: Use OPP API to set clk/perf stateRajendra Nayak3-2/+32
On some qualcomm platforms DPU needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: ratelimit crtc event overflow errorRob Clark1-1/+1
This can happen a lot when things go pear shaped. Lets not flood dmesg when this happens. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: send opp instead of a frequencySharat Masetty4-45/+52
This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Fix a null pointer access in msm_gem_shrinker_count()Akhil P Oommen1-15/+21
Adding an msm_gem_object object to the inactive_list before completing its initialization is a bad idea because shrinker may pick it up from the inactive_list. Fix this by making sure that the initialization is complete before moving the msm_obj object to the inactive list. This patch fixes the below error: [10027.553044] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000068 [10027.573305] Mem abort info: [10027.590160] ESR = 0x96000006 [10027.597905] EC = 0x25: DABT (current EL), IL = 32 bits [10027.614430] SET = 0, FnV = 0 [10027.624427] EA = 0, S1PTW = 0 [10027.632722] Data abort info: [10027.638039] ISV = 0, ISS = 0x00000006 [10027.647459] CM = 0, WnR = 0 [10027.654345] user pgtable: 4k pages, 39-bit VAs, pgdp=00000001e3a6a000 [10027.672681] [0000000000000068] pgd=0000000198c31003, pud=0000000198c31003, pmd=0000000000000000 [10027.693900] Internal error: Oops: 96000006 [#1] PREEMPT SMP [10027.738261] CPU: 3 PID: 214 Comm: kswapd0 Tainted: G S 5.4.40 #1 [10027.745766] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT) [10027.752472] pstate: 80c00009 (Nzcv daif +PAN +UAO) [10027.757409] pc : mutex_is_locked+0x14/0x2c [10027.761626] lr : msm_gem_shrinker_count+0x70/0xec [10027.766454] sp : ffffffc011323ad0 [10027.769867] x29: ffffffc011323ad0 x28: ffffffe677e4b878 [10027.775324] x27: 0000000000000cc0 x26: 0000000000000000 [10027.780783] x25: ffffff817114a708 x24: 0000000000000008 [10027.786242] x23: ffffff8023ab7170 x22: 0000000000000001 [10027.791701] x21: ffffff817114a080 x20: 0000000000000119 [10027.797160] x19: 0000000000000068 x18: 00000000000003bc [10027.802621] x17: 0000000004a34210 x16: 00000000000000c0 [10027.808083] x15: 0000000000000000 x14: 0000000000000000 [10027.813542] x13: ffffffe677e0a3c0 x12: 0000000000000000 [10027.819000] x11: 0000000000000000 x10: ffffff8174b94340 [10027.824461] x9 : 0000000000000000 x8 : 0000000000000000 [10027.829919] x7 : 00000000000001fc x6 : ffffffc011323c88 [10027.835373] x5 : 0000000000000001 x4 : ffffffc011323d80 [10027.840832] x3 : ffffffff0477b348 x2 : 0000000000000000 [10027.846290] x1 : ffffffc011323b68 x0 : 0000000000000068 [10027.851748] Call trace: [10027.854264] mutex_is_locked+0x14/0x2c [10027.858121] msm_gem_shrinker_count+0x70/0xec [10027.862603] shrink_slab+0xc0/0x4b4 [10027.866187] shrink_node+0x4a8/0x818 [10027.869860] kswapd+0x624/0x890 [10027.873097] kthread+0x11c/0x12c [10027.876424] ret_from_fork+0x10/0x18 [10027.880102] Code: f9000bf3 910003fd aa0003f3 d503201f (f9400268) [10027.886362] ---[ end trace df5849a1a3543251 ]--- [10027.891518] Kernel panic - not syncing: Fatal exception Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add support for dither block in displayKalyan Thota3-9/+121
This change enables dither block for primary interface in display. Enabled for 6bpc in the current version. Changes in v1: - Remove redundant error checks (Rob). Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: fix gpu probe if no interconnect-namesRob Clark1-8/+10
If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. v2: explicity check for interconnect-names property Fixes: 08af4769c7d2 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Fixes: 00bb9243d346 ("drm/msm/gpu: add support for ocmem interconnect path") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: re-add deleted doc for drm_gem_open_ioctlSteve Cohen1-0/+3
Add back the removed documentation for drm_gem_open_ioctl. This patch is submitted in response to [1]. [1] https://lore.kernel.org/linux-arm-msm/20200728085244.GY6419@phenom.ffwll.local/ Signed-off-by: Steve Cohen <cohens@codeaurora.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1596000952-27621-1-git-send-email-cohens@codeaurora.org
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.