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2020-05-01amd/amdgpu: Limit rlcg write registers only for nv12shaoyunl1-7/+25
Create gfx_v10_0_rlc_funcs_sriov for nv12 with rlcg_write function pointers be initialized so driver can use RLCG to write aceess CSIB and CP_ME_CNTL registers when nv12 in sriov mode Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdkfd: Use a systematic method to calculate queue mask bitYong Zhao2-1/+6
The queue mask used for set_resources always assumes the queue number per pipe is 8, so KFD needs to align with that by using function amdgpu_queue_mask_bit_to_set_resource_bit(). Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: Rename amdgpu_gfx_kcq_queue_mask_transform()Yong Zhao2-9/+9
Rename it to amdgpu_queue_mask_bit_to_set_resource_bit() to be more specific about its functionality. KFD will use it later. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: skip reservation of discovery tmr region in pre-NaviHawking Zhang1-3/+5
IP discovery is only supported in Navi series and onwards. There is no need to reserve a portion of vram as discovery tmr region for pre-Navi adapters. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: re-structue members for ip discoveryHawking Zhang3-35/+38
This is to prepare for initializing discovery tmr size per ASIC type Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: update the method to set kcq queue maskLikun Gao1-1/+14
Use a common method to set queue mask before set kiq resource. The value of queue mask must suitablt for the designated form. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: check SMU NULL ptr on gfx hw initLikun Gao1-7/+9
Check SMU NULL ptr before load smu fw. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: change HWIP from UVD to VCN for VCN2.5Boyuan Zhang1-196/+196
Rename hardware IP name from UVD to VCN to reduce confusion. Hardware IP name UVD and VCN are equivalent for VCN2.5 asics. Use name VCN for future VCN based asics. V2: update description V3: rebase Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: James Zhu <james.zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/i915: Implement vm_ops->access for gdb access into mmapsChris Wilson2-0/+158
gdb uses ptrace() to peek and poke bytes of the target's address space. The driver must implement an vm_ops->access() handler or else gdb will be unable to inspect the pointer and report it as out-of-bounds. Worse than useless as it causes immediate suspicion of the valid GTT pointer, distracting the poor programmer trying to find his bug. v2: Write-protect readonly objects (Matthew). Testcase: igt/gem_mmap_gtt/ptrace Testcase: igt/gem_mmap_offset/ptrace Suggested-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Maciej Patelczyk <maciej.patelczyk@intel.com> Cc: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200501145120.18830-1-chris@chris-wilson.co.uk
2020-05-01drm/i915/gt: Make timeslicing an explicit engine propertyChris Wilson3-14/+18
In order to allow userspace to rely on timeslicing to reorder their batches, we must support preemption of those user batches. Declare timeslicing as an explicit property that is a combination of having the kernel support and HW support. Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200501122249.12417-1-chris@chris-wilson.co.uk
2020-05-01drm/amdgpu: Add missing parameter description in commentsFelix Kuehling2-0/+2
Kerneldoc comments should describe all function parameters. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdkfd: Fix comment formattingFelix Kuehling1-2/+2
Corrected two function names. Added a missing space. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: Changed CU reservation golden settingsOak Zeng1-2/+2
With previous golden settings, compute task can't use reserved LDS (32K) on CU0 and CU1. On 64K LDS system, if compute work group allocate more than 32K LDS, then it can't be dispatched to CU0 and CU1 because of the reservation. This enables compute task to use reserved LDS on CU0 and CU1. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2020-05-01drm/amdkfd: Report domain with topologyOri Messinger2-0/+4
PCI domain has moved to 32-bits to accommodate virtualization, so a 32-bit integer is exposed for domain to reflect this change. Domain can be found in here: /sys/class/kfd/kfd/topology/nodes/X/properties Where X is the card number Signed-off-by: Ori Messinger <ori.messinger@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amd/display: work around fp code being emitted outside of DC_FP_START/ENDDaniel Kolesa1-8/+23
The dcn20_validate_bandwidth function would have code touching the incorrect registers emitted outside of the boundaries of the DC_FP_START/END macros, at least on ppc64le. Work around the problem by wrapping the whole function instead. Signed-off-by: Daniel Kolesa <daniel@octaforge.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.6.x
2020-05-01drm/amdgpu/dc: Use WARN_ON_ONCE for ASSERTMichel Dänzer1-1/+1
Once should generally be enough for diagnosing what lead up to it, repeating it over and over can be pretty annoying. Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-05-01drm/amdgpu: drop redundant cg/pg ungate on runpm enterEvan Quan1-3/+0
CG/PG ungate is already performed in ip_suspend_phase1. Otherwise, the CG/PG ungate will be performed twice. That will cause gfxoff disablement is performed twice also on runpm enter while gfxoff enablemnt once on rump exit. That will put gfxoff into disabled state. Fixes: b2a7e9735ab286 ("drm/amdgpu: fix the hw hang during perform system reboot and reset") Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-05-01drm/amdgpu: move kfd suspend after ip_suspend_phase1Evan Quan1-2/+2
This sequence change should be safe as what did in ip_suspend_phase1 is to suspend DCE only. And this is a prerequisite for coming redundant cg/pg ungate dropping. Fixes: 487eca11a321ef ("drm/amdgpu: fix gfx hang during suspend with video playback (v2)") Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-05-01drm/i915/pmu: Keep a reference to module while activeChris Wilson1-1/+4
While a perf event is open, keep a reference to the module so we don't remove the driver internals mid-sampling. Testcase: igt/perf_pmu/module-unload Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: stable@vger.kernel.org Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430183324.23984-1-chris@chris-wilson.co.uk
2020-05-01drm/i915/gem: Replace user_access_begin by user_write_access_beginChristophe Leroy1-2/+3
When i915_gem_execbuffer2_ioctl() is using user_access_begin(), that's only to perform unsafe_put_user() so use user_write_access_begin() in order to only open write access. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/ebf1250b6d4f351469fb339e5399d8b92aa8a1c1.1585898438.git.christophe.leroy@c-s.fr
2020-05-01Merge tag 'amd-drm-fixes-5.7-2020-04-29' of git://people.freedesktop.org/~agd5f/linux into drm-fixesDave Airlie23-104/+210
amd-drm-fixes-5.7-2020-04-29: amdgpu: - Fix a green screen on resume issue - PM fixes for SR-IOV - SDMA fix for navi - Renoir display fixes - Cursor and pageflip stuttering fixes - Misc additional display fixes UAPI: - Add additional DCC tiling flags for navi1x Used by: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429212008.4306-1-alexander.deucher@amd.com
2020-05-01Merge tag 'drm-intel-fixes-2020-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixesDave Airlie5-14/+36
- Fix selftest refcnt leak (Xiyu) - Fix gem vma lock (Chris) - Fix gt's i915_request.timeline acquire by checking if cacheline is valid (Chris) - Fix IRQ postinistall fault masks (Matt) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430140042.GA270140@intel.com
2020-05-01Merge tag 'drm-misc-fixes-2020-04-30' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixesDave Airlie8-30/+28
A few resources-related fixes for qxl, some doc build warnings and ioctl fixes for dma-buf, an off-by-one fix in edid, and a return code fix in DP-MST Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20200430153201.wx6of2b2gsoip7bk@gilmour.lan
2020-04-30drm/amd/display: Fix unsigned comparison to zeroZou Wei1-1/+2
Fixes coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c:1398:60-61: WARNING: Unsigned expression compared with zero: j >= 0 Fixes: 238387774232 ("drm/amd/display: fix rn soc bb update") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'speakers' in dcn10_stream_encoder.cZheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c:1277:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable] It is introduced by commit 0c41891c81c0 ("drm/amd/display: Refactor stream encoder for HW review"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'speakers' in dce_stream_encoder.cZheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c:1339:11: warning: variable ‘speakers’ set but not used [-Wunused-but-set-variable] It is introduced by commit 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'pixel_width'Zheng Bin1-7/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c:137:11: warning: variable ‘pixel_width’ set but not used [-Wunused-but-set-variable] It is introduced by commit 70ccab604049 ("drm/amdgpu/display: Add core dc support for DCN"), but never used, so remove it. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove set but not used variable 'dc'Zheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8665:13: warning: variable ‘dc’ set but not used [-Wunused-but-set-variable] It is not used since commit d1ebfdd8d0fc ("drm/amd/display: Unify psr feature flags") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: remove set but not used variable 'direct_poll' in vcn_v2_5.cZheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1170:39: warning: variable ‘direct_poll’ set but not used [-Wunused-but-set-variable] It is introduced by commit 7daaebfea5e5 ("drm/amdgpu: add VCN2.5 sriov start for Arctrus"), but never used, so remove it. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: remove set but not used variable 'direct_poll' in vcn_v2_0.cZheng Bin1-3/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1848:39: warning: variable ‘direct_poll’ set but not used [-Wunused-but-set-variable] It is introduced by commit dd26858a9cd8 ("drm/amdgpu: implement initialization part on VCN2.0 for SRIOV"), but never used, so remove it. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: remove set but not used variable 'priority'Zheng Bin1-2/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1211:26: warning: variable ‘priority’ set but not used It is not used since commit 33abcb1f5a17 ("drm/amdgpu: set compute queue priority at mqd_init") Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: work around fp code being emitted outside of DC_FP_START/ENDDaniel Kolesa1-8/+23
The dcn20_validate_bandwidth function would have code touching the incorrect registers emitted outside of the boundaries of the DC_FP_START/END macros, at least on ppc64le. Work around the problem by wrapping the whole function instead. Signed-off-by: Daniel Kolesa <daniel@octaforge.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu/dc: Use WARN_ON_ONCE for ASSERTMichel Dänzer1-1/+1
Once should generally be enough for diagnosing what lead up to it, repeating it over and over can be pretty annoying. Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/radeon: cleanup coding style a bitBernard Zhao1-2/+1
Maybe no need to check ws before kmalloc, kmalloc will check itself, kmalloc`s logic is if ptr is NULL, kmalloc will just return Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: update RAS sequence to parse TA flagsJohn Clements1-1/+28
RAS TA shall notify driver with flags of error specifics Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: update RAS TA to Host interfaceJohn Clements1-17/+42
Update interface to match latest TA Organized input/output structures to better maintain backward compatiblity in the future Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: update RAS error handlingJohn Clements1-9/+31
Parse return status from TA to determine error severity Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu: put the audio codec into suspend state before gpu reset V3Evan Quan1-0/+75
At default, the autosuspend delay of audio controller is 3S. If the gpu reset is triggered within 3S(after audio controller idle), the audio controller may be unable into suspended state. Then the sudden gpu reset will cause some audio errors. The change here is targeted to resolve this. However if the audio controller is in use when the gpu reset triggered, this change may be still not enough to put the audio controller into suspend state. Under this case, the gpu reset will still proceed but there will be a warning message printed("failed to suspend display audio"). V2: limit this for BACO and mode1 reset only V3: try 1st to use pm_runtime_autosuspend_expiration() to query how much time is left. Use default setting on failure Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdgpu/smu10: remove duplicate assignment of smu10_hwmgr_funcs membersJason Yan1-1/+0
The struct member 'asic_setup' was assigned twice, let's remove one: static const struct pp_hwmgr_func smu10_hwmgr_funcs = { ...... .asic_setup = NULL, ...... .asic_setup = smu10_setup_asic_task, ...... }; This fixes the following coccicheck warning: drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c:1357:52-53: asic_setup: first occurrence line 1360, second occurrence line 1388 Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amd/display: remove duplicate assignment of dcn21_funcs membersJason Yan1-5/+0
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: exit_optimized_pwr_state: first occurrence line 86, second occurrence line 92 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: optimize_pwr_state: first occurrence line 85, second occurrence line 91 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_attribute: first occurrence line 71, second occurrence line 89 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_position: first occurrence line 70, second occurrence line 88 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c:31:51-52: set_cursor_sdr_white_level: first occurrence line 72, second occurrence line 90 Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm/amdkfd: Track GPU memory utilization per processMukul Joshi5-12/+84
Track GPU VRAM usage on a per process basis and report it through sysfs. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-04-30drm: Correct DP DSC macro typoRodrigo Siqueira1-1/+1
In the file drm_dp_helper.h we have a macro named DP_DSC_THROUGHPUT_MODE_{0,1}_UPSUPPORTED, the correct name should be DP_DSC_THROUGHPUT_MODE_{0,1}_UNSUPPORTED. This commits adjusts this typo in the header file and in other places that attempt to access this macro. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429184142.1867987-1-Rodrigo.Siqueira@amd.com
2020-04-30drm/i915/gt: Move the batch buffer pool from the engine to the gtChris Wilson16-116/+160
Since the introduction of 'soft-rc6', we aim to park the device quickly and that results in frequent idling of the whole device. Currently upon idling we free the batch buffer pool, and so this renders the cache ineffective for many workloads. If we want to have an effective cache of recently allocated buffers available for reuse, we need to decouple that cache from the engine powermanagement and make it timer based. As there is no reason then to keep it within the engine (where it once made retirement order easier to track), we can move it up the hierarchy to the owner of the memory allocations. v2: Hook up to debugfs/drop_caches to clear the cache on demand. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200430111819.10262-2-chris@chris-wilson.co.uk
2020-04-30drm/ast: remove duplicate assignment of ast_crtc_funcs memberJason Yan1-1/+0
The struct member 'set_config' was assigned twice: static const struct drm_crtc_funcs ast_crtc_funcs = { .reset = ast_crtc_reset, .set_config = drm_crtc_helper_set_config, ...... .set_config = drm_atomic_helper_set_config, ...... }; Since the second one is which we use now in fact, we can remove the first one. This fixes the following coccicheck warning: drivers/gpu/drm/ast/ast_mode.c:932:50-51: set_config: first occurrence line 934, second occurrence line 937 Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200429141010.8445-1-yanaijie@huawei.com
2020-04-30drm/i915: Update DRIVER_DATE to 20200430Joonas Lahtinen1-2/+2
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2020-04-30Merge tag 'gvt-next-2020-04-22' of https://github.com/intel/gvt-linux into drm-intel-next-queuedJoonas Lahtinen5-36/+114
gvt-next-2020-04-22 - remove non-upstream xen support bits (Christoph) - guest context shadow copy optimization (Yan) - guest context tracking for shadow skip optimization (Yan) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200422051230.GH11247@zhen-hp.sh.intel.com
2020-04-30drm/i915/selftests: Add tiled blits selftestZbigniew Kempczyński2-0/+597
Extend coverage of the blitter client by exercising conversion to and from tiled sources. In the process we perform spot checks to verify that the tiling/detiling is being applied correctly, along with position invariance of the tiling parameters. Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200430064957.14942-1-chris@chris-wilson.co.uk
2020-04-30Merge tag 'amd-drm-next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie259-3857/+9203
amd-drm-next-5.8-2020-04-24: amdgpu: - Documentation improvements - Enable FRU chip access on boards that support it - RAS updates - SR-IOV updates - Powerplay locking fixes for older SMU versions - VCN DPG (dynamic powergating) cleanup - VCN 2.5 DPG enablement - Rework GPU scheduler handling - Improve scheduler priority handling - Add SPM (streaming performance monitor) golden settings for navi - GFX10 clockgating fixes - DC ABM (automatic backlight modulation) fixes - DC cursor and plane fixes - DC watermark fixes - DC clock handling fixes - DC color management fixes - GPU reset fixes - Clean up MMIO access macros - EEPROM access fixes - Misc code cleanups amdkfd: - Misc code cleanups radeon: - Clean up safe reg list generation - Misc code cleanups From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200424190827.4542-1-alexander.deucher@amd.com
2020-04-30drm/i915/gt: Restore aggressive post-boost downclockingChris Wilson1-16/+4
We reduced the clocks slowly after a boost event based on the observation that the smoothness of animations suffered. However, since reducing the evalution intervals, we should be able to respond to the rapidly fluctuating workload of a simple desktop animation and so restore the more aggressive downclocking. References: 2a8862d2f3da ("drm/i915: Reduce the RPS shock") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429205446.3259-6-chris@chris-wilson.co.uk
2020-04-30drm/i915/gt: Apply the aggressive downclocking to parkingChris Wilson1-4/+9
We treat parking as a manual RPS timeout event, and downclock the GPU for the next unpark and batch execution. However, having restored the aggressive downclocking and observed that we have very light workloads whose only interaction is through the manual parking events, carry over the aggressive downclocking to the fake RPS events. References: 21abf0bf168d ("drm/i915/gt: Treat idling as a RPS downclock event") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200429205446.3259-5-chris@chris-wilson.co.uk
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