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2020-02-11drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1James Zhu4-14/+15
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode power off issue on instance 1. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Add initialitions for PLL2 clock sourceIsabel Zhang1-0/+6
[Why] Starting from 14nm, the PLL is built into the PHY and the PLL is mapped to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not initialized. This causes DP to HDMI dongle to not light up the display. [How] Initializations added for PLL2 when creating resources. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Limit minimum DPPCLK to 100MHz.Yongqiang Sun1-0/+6
[Why] Underflow is observed when plug in a 4K@60 monitor with 1366x768 eDP due to DPPCLK is too low. [How] Limit minimum DPPCLK to 100MHz. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Check engine is not NULL before acquiringAric Cyr1-1/+1
[Why] Engine can be NULL in some cases, so we must not acquire it. [How] Check for NULL engine before acquiring. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/i915: Fix the docs for intel_set_cdclk_post_plane_update()Ville Syrjälä1-1/+1
s/before/after/ again after accidentally changing it the other way in commit 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200204154803.25403-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-02-11drm/i915: Don't use uninitialized 'ret'Ville Syrjälä1-4/+6
Accidentally removed the 'ret=0' initialization, and thus we're potentially looking at some stack garbage here. The whole 'ret = do_stuff; if (!ret) do_other_stuff;' pattern confuses my brain so let's replace it with the standard immediate return thing. Reported-by: Chris Wilson <chris@chris-wilson.co.uk> Fixes: 28a30b45f5e9 ("drm/i915: Convert cdclk to global state") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200207152228.1054-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2020-02-11drm/i915: Disable use of hwsp_cacheline for kernel_contextChris Wilson3-10/+30
Currently on execlists, we use a local hwsp for the kernel_context, rather than the engine's HWSP, as this is the default for execlists. However, seqno wrap requires allocating a new HWSP cacheline, and may require pinning a new HWSP page in the GGTT. This operation requiring pinning in the GGTT is not allowed within the kernel_context timeline, as doing so may require re-entering the kernel_context in order to evict from the GGTT. As we want to avoid requiring a new HWSP for the kernel_context, we can use the permanently pinned engine's HWSP instead. However to do so we must prevent the use of semaphores reading the kernel_context's HWSP, as the use of semaphores do not support rollover onto the same cacheline. Fortunately, the kernel_context is mostly isolated, so unlikely to give benefit to semaphores. Reported-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200210205722.794180-5-chris@chris-wilson.co.uk
2020-02-11drm/amd/display: Use dcfclk to populate watermark rangesSung Lee1-7/+7
[WHY & HOW] Previously drain clk was unconstrained and fill clk was constrained on fclk. We want to change it to fill clk unconstrained and drain clock constrained to dcfclk. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Do not set optimized_require to false after plane disableSung Lee1-1/+0
[WHY] The optimized_require flag is needed to set watermarks and clocks lower in certain conditions. This flag is set to true and then set to false while programming front end in dcn20. [HOW] Do not set the flag to false while disabling plane. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Fix psr static frames calculationRoman Li1-2/+3
[Why] Driver crash with psr feature enabled due to divide-by-zero error. This is a regression after rework to calculate static screen frame number entry time. [How] Correct order of operations to avoid divide-by-zero. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Remove set but not unused variable 'stream_status'YueHaibing1-7/+1
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function dcn10_post_unlock_program_front_end: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2623:29: warning: variable stream_status set but not used [-Wunused-but-set-variable] commit bbf5f6c3f83b ("drm/amd/display: Split program front end part that occur outside lock") involved this unused variable. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu/powerplay: fix baco check for vega20Alex Deucher1-3/+4
We need to handle the runpm case as well as GPU reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu/smu: properly handle runpm/suspend/resetAlex Deucher1-16/+19
We need some special handling when using baco vs. other things. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu: add flag for runtime suspendAlex Deucher2-0/+3
So we know whether we in are in runtime suspend or system suspend. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu:/navi10: use the ODCAP enum to index the caps arrayAlex Deucher1-11/+11
Rather than the FEATURE_ID flags. Avoids a possible reading past the end of the array. Reviewed-by: Evan Quan <evan.quan@amd.com> Reported-by: Aleksandr Mezin <mezin.alexander@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu: update smu_v11_0_pptable.hAlex Deucher1-14/+32
Update to the latest changes. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu: Do not move root PT bo to relocated listxinhui pan1-17/+17
As root PD has no parent, we just need move its status to idle. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> CC: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu: correct comment to clear up the confusionGuchun Chen1-1/+6
Former comment looks to be one intended behavior in code, actually it's not. So correct it. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/powerplay: suppress nonsupport profile mode overrun messagePrike Liang1-2/+6
SMU12 not support WORKLOAD_DEFAULT_BIT and WORKLOAD_PPLIB_POWER_SAVING_BIT. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/powerplay: update smu11_driver_if_navi10.hEvan Quan2-3/+4
To pair the latest SMU firmwares. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: DCN2.x Do not program DPPCLK if same valueSung Lee1-1/+1
[WHY] Programming DPPCLK to the same value currently set may cause underflow while playing video in certain conditions. [HOW] Only program DPPCLK if clock is not the same as the previous value programmed. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Use fb_base/fb_offset if available for translationNicholas Kazlauskas1-0/+6
[Why] In the case where we do have these passed in then we should be using these instead of the registers - those are only programmed when booting the adapter as primary. [How] Check if fb_base/fb_offset are non-zero. The value of 0 is invalid for fb_base but is valid for fb_offset on dGPU. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Add psr get_state callWyatt Wood3-7/+10
[Why] Driver needs to know PSR state. [How] Use GPINT to call to firmware and get psr state. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Don't map ATOM_ENABLE to ATOM_INITNicholas Kazlauskas1-4/+0
[Why] In DCN hardware sequencer we do actually call ATOM_INIT correctly per pipe. The workaround is not necessary for command table offloading. [How] Drop the workaround since it's not needed. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: add monitor patch to disable SCDC read/writeMartin Leung4-0/+18
[why] customer issue: found that for their specific panel, EDID register space being overwritten during SCDC read write [how] customer accepted HDMI 2 features not working - disabled SCDC read/write as well as HDMI 2 in general based on monitor patch Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: add odm split logic to scaling calculationsDmytro Laktyushkin3-79/+131
Currently odm scaling calculations are only done when adding initial odm pipe. Any scaling re-calculations will mess up odm because of this. This change resolves the problem by updating scaling split logic to handle odm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Michael Strauss <Michael.Strauss@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: 3.2.72Anthony Koo1-1/+1
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Drop unused field from dc_panel_patchNikola Cornij1-1/+0
In the struct dc_panel_patch, we have a field named manage_secondary_link which is not used by any part of the code. This commit drops the unused field. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Update register definesAnthony Koo2-27/+0
[Why] Some register defines are redundant or updated [How] Update register defines Remove some redundant defines Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Toggle VSR button cause system crashPeikang Zhang1-2/+6
[Why] in dcn10_apply_ctx_for_surface(), if we hit !top_pipe_to_program, pipe_ctx->update_flags could not get cleared. [How] Moved clearing pipe_ctx->update_flags logic before if (!top_pipe_to_program) to gurantee pipe_ctx->update_flags get cleared. Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Add backlight support via AUXRodrigo Siqueira2-27/+166
Several modern displays support HDR/OLED panel, and one of the interesting changes provided by this technology is the new approach for handling backlight. More precisely, in the traditional way, we use PWM to manage display backlight; however, with HDR/OLED we begin to use DP Aux channel for adjusting the backlight. This patch, enable the backlight control in HDR/OLED display via DP Aux. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Add AUX backlight registerRodrigo Siqueira2-8/+8
Introduce vendor-specific registers for handling backlight via AUX. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Hookup psr set version callWyatt Wood2-6/+12
[Why] Set version is currently not called. [How] Add call to set version from copy settings. This should be the only time this is called as the eDP caps should never change. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Pass override OUI in to dc_init_dataCalvin Hou4-17/+40
[WHY] Vendor dongle requires propietary OUI and handshake sequence. [HOW] Add a new structure to dc_init_data, to allow creator to pass an override vendor_oui. This value will be written to DP_SOURCE_OUI instead of AMD signature, when dpcd_set_source_specific_data is called. Signed-off-by: Calvin Hou <Calvin.Hou@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Remove unused values from psr structWyatt Wood2-23/+0
[Why] Taking up unnecessary space. [How] Remove unused values from psr struct. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: Don't treat missing command table as failureNicholas Kazlauskas1-2/+2
[Why] With the fallback case in place for command table offloading via DMCUB it's no longer an error for the command table to be missing specific entries. [How] Drop the BREAK_TO_DEBUGGER(); Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amd/display: always apply T7/T9 delay logicMartin Leung1-27/+29
[why] before we exit early in edp_reciever_ready if we detect that panel is not edp or below rev 1.2. This will skip the backlight/t7 delay panel patch. [how] edit logic to ensure panel patch is applied regardless of edp rev. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu/vcn2.5: fix warningJames Zhu1-1/+1
Fix warning during switching to dpg pause mode for VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16 Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu: limit GDS clearing workaround in cold boot sequenceGuchun Chen1-3/+6
GDS clear workaround will cause gfx failure in suspend/resume case. [ 98.679559] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR* late_init of IP block <gfx_v9_0> failed -110 [ 98.679561] PM: dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -110 [ 98.679562] PM: Device 0000:03:00.0 failed to resume async: error -110 As this workaround is specific to the HW bug of GDS's ECC error existing in cold boot up, so bypass this workaround in suspend/ resume case after booting up. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/amdgpu/sriov set driver_table address in VFJack Zhang1-4/+4
With the recent patch to unify VRAM address for driver table(a83f82e). VF cannot dump table info any more because SMU_MSG_SetDriverDramAddrHigh/Low were deleted in the function of smu_update_table. Therefore, VF also needs to set driver_table address in smu_hw_init to fix this regression issue. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-11drm/irq: remove check on dev->dev_privateJani Nikula1-4/+0
There is no real reason to require drivers to set and use dev->dev_private. Indeed, the current recommendation, as documented in drm_device.h, is to embed struct drm_device in the per-device struct instead of using dev_private. Remove the requirement for dev_private to have been set to indicate driver initialization. For background, quoting Daniel Vetter: Now there might be some hilarious races this papers over, but: - Proper drivers should only call drm_dev_register once everything is set up, including this stuff here. No race possible with anything else really. - Slightly more wobbly drivers, including the legacy ones, all use drm_global_mutex. This was the former BKL, which means that it was impossible for soeone to go through the load/unload/reload (between lastclose and firstopen) paths and also run the ioctl. But the ioctl had to be made unlocked because blocking there killed X: commit 8f4ff2b06afcd6f151868474a432c603057eaf56 Author: Ilija Hadzic <ihadzic@research.bell-labs.com> Date: Mon Oct 31 17:46:18 2011 -0400 drm: do not sleep on vblank while holding a mutex The even more legacy DRM_CONTROL ioctl stayed fully locked. But the file open/close paths are still fully locked, and that's the only place legacy drivers should call drm_irq_install/uninstall, so should all still be fully ordered and protected and happy. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel@ffwll.ch> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200211144753.3175-1-jani.nikula@intel.com
2020-02-11drm/panel: simple: Add Rocktech RK101II01D-CT panelJyri Sarha1-0/+32
Add support for Rocktech RK101II01D-CT, 10.1" 1280x800 TFT with LVDS interface, LED backlight and integrated Goodix GT928 capacitive touch panel. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/b543b77d8af7cbbef852d3df4595f11ac1aa0046.1581423249.git.jsarha@ti.com
2020-02-11drm/msm: Fix a6xx GMU shutdown sequenceJordan Crouse2-49/+31
Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") missed updating the VBIF flush in a6xx_gmu_shutdown and instead inserted the new sequence into a6xx_pm_suspend along with a redundant GMU idle. Move a6xx_bus_clear_pending_transactions to a6xx_gmu.c and use it in the appropriate place in the shutdown routine and remove the redundant idle call. v2: Remove newly unused variable that was triggering a warning Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618") Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/msm/a6xx: Update the GMU bus tables for sc7180Jordan Crouse1-25/+60
Fixup the GMU bus table values for the sc7180 target. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/msm/a6xx: Remove unneeded GBIF unhaltJordan Crouse1-12/+0
Commit e812744c5f95 ("drm: msm: a6xx: Add support for A618") added a universal GBIF un-halt into a6xx_start(). This can cause problems for a630 targets which do not use GBIF and might have access protection enabled on the region now occupied by the GBIF registers. But it turns out that we didn't need to unhalt the GBIF in this path since the stop function already takes care of that after executing a flush but before turning off the headswitch. We should be confident that the GBIF is open for business when we restart the hardware. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com> Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm: msm: Fix return type of dsi_mgr_connector_mode_valid for kCFIJohn Stultz1-1/+1
I was hitting kCFI crashes when building with clang, and after some digging finally narrowed it down to the dsi_mgr_connector_mode_valid() function being implemented as returning an int, instead of an enum drm_mode_status. This patch fixes it, and appeases the opaque word of the kCFI gods (seriously, clang inlining everything makes the kCFI backtraces only really rough estimates of where things went wrong). Thanks as always to Sami for his help narrowing this down. Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: Sami Tolvanen <samitolvanen@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Alistair Delva <adelva@google.com> Cc: Amit Pundir <amit.pundir@linaro.org> Cc: Sumit Semwal <sumit.semwal@linaro.org> Cc: freedreno@lists.freedesktop.org Cc: clang-built-linux@googlegroups.com Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/msm/a6xx: Correct the highestbank configurationAkhil P Oommen1-4/+6
Highest bank bit configuration is different for a618 gpu. Update it with the correct configuration which is the reset value incidentally. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618") Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/i915/selftests: Relax timeout for error-interrupt reset processingChris Wilson1-4/+11
We can not require that the system process a tasklet in reasonable time (thanks be to ksoftirqd), but we can insist that having waited sufficiently for the error interrupt to have been raised and having kicked the tasklet, the reset has begun and the request will be marked as in error (if not already completed). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200210205722.794180-3-chris@chris-wilson.co.uk
2020-02-11msm:disp:dpu1: add UBWC support for display on SC7180Kalyan Thota1-1/+57
Add UBWC global configuration for display on SC7180 target. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Fixes: 73bfb790ac78 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-02-11drm/msm/mdp5: rate limit pp done timeout warningsBrian Masney1-2/+2
Add rate limiting of the 'pp done time out' warnings since these warnings can quickly fill the dmesg buffer. Signed-off-by: Brian Masney <masneyb@onstation.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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