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2019-10-25drm/amd/display: Fix MPO & pipe split on 3-pipe dcn2xMichael Strauss2-2/+12
[WHY] DML is incorrectly initialized with 4 pipes on 3 pipe configs RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display) [HOW] Set correct number of DPP/OTGs for dml init to generate correct DPP topology Double RequiredDPPCLK after clock is halved for pipe split and find_secondary_pipe fails to fix underflow Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: remove unnecessary assertDmytro Laktyushkin1-3/+2
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: move dispclk vco freq to clk mgr baseDmytro Laktyushkin10-43/+40
This value will be needed by dml and therefore should be externally accessible. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: correctly initialize dml odm variablesDmytro Laktyushkin3-7/+3
One of odm variables was not initialized in dml. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: split dcn20 fast validate into more functionsDmytro Laktyushkin3-78/+136
Split a large function into smaller, reusable chunks. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: correctly populate dpp refclk in fpgaAnthony Koo1-2/+8
[Why] In diags environment we are not programming the DPP DTO correctly. [How] Populate the dpp refclk in dccg so it can be used to correctly program DPP DTO. Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Enable PSRRoman Li1-3/+130
[Why] PSR (Panel Self-Refresh) is a power-saving feature for eDP panels. The feature has support in DMCU (Display MicroController Unit). DMCU/driver communication is implemented in DC. DM can use existing DC PSR interface to use PSR feature. [How] - Read psr caps via dpcd - Send vsc infoframe if panel supports psr - Disable psr before h/w programming (FULL_UPDATE) - Enable psr after h/w programming - Disable psr for fb console Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Add debugfs entry for reading psr stateRoman Li2-0/+170
[Why] For upcoming PSR stupport it's useful to have debug entry to verify psr state. [How] - Enable psr dc api for Linux - Add psr_state file to eDP connector debugfs usage e.g.: cat /sys/kernel/debug/dri/0/DP-1/psr_state Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: 3.2.55Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: remove unused codeDmytro Laktyushkin3-11/+0
Commit hints are unnecessary after front end programming redesign. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Remove superfluous assertJordan Lazare1-2/+0
[Why] For loop below the assert already checks for the number of instances to create. ASSERT is meaningless and causing spam. [How] dd Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Don't use optimized gamma22 with eetfAidan Yang1-4/+41
[why] Optimized gamma22 assumes fixed point distribution which is not true for eetf true. [how] Use long calculation for eetf. Signed-off-by: Aidan Yang <Aidan.Yang@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Reza Amini <Reza.Amini@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Add unknown clk state.Yongqiang Sun3-11/+12
[Why] System hang during S0i3 if DP only connected due to clk is disabled when doing link training. During S0i3, clk is disabled while the clk state is updated when ini_hw called, and at the moment clk is still disabled which indicating a wrong state for next time trying to enable clk. [How] Add an unknown state and initialize it during int_hw, make sure enable clk command be sent to smu. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: add odm visual confirmJun Lei3-1/+29
[why] Hard to determine if pipe combine is done with MPC or ODM [how] Add new visual confirm type, this will mark each MPCC tree with a different color Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: add 50us buffer as WA for pstate switch in activeJun Lei1-1/+2
Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Avoid sending abnormal VSIFWayne Lin1-0/+3
[Why] While setting hdmi_vic, hv_frame.vic is not initialized and might assign a wrong value to hdmi_vic. Cause to send out VSIF with abnormal value. [How] Initialize hv_frame and avi_frame Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/powerplay: update Arcturus driver smu interface XGMI link partEvan Quan2-9/+21
To fit the latest SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/psp: fix spelling mistake "initliaze" -> "initialize"Colin Ian King1-1/+1
There is a spelling mistake in a DRM_ERROR error message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: Free gamma after calculating legacy transfer functionNicholas Kazlauskas1-0/+2
[Why] We're leaking memory by not freeing the gamma used to calculate the transfer function for legacy gamma. [How] Release the gamma after we're done with it. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/psp11: fix typo in commentXiaojie Yuan1-1/+1
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/psp11: wait for sOS ready for ring creationXiaojie Yuan1-0/+8
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: setting the DIG_MODE to the correct value.Zhan liu1-0/+9
[Why] This patch is for fixing Navi14 HDMI display pink screen issue. [How] Call stream->link->link_enc->funcs->setup twice. This is setting the DIG_MODE to the correct value after having been overridden by the call to transmitter control. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/powerplay: use local renoir array sizes for clock fetchingAlex Deucher1-4/+4
To avoid walking past the end of the arrays since the PP_SMU defines don't match the renoir defines. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu: call amdgpu_vm_prt_fini before deleting the root PDPelloux-prayer, Pierre-eric1-9/+10
amdgpu_vm_prt_fini uses "vm->root.base.bo" so it must still be valid when we call it. Fixes: b65709a92156 ("drm/amdgpu: reserve the root PD while freeing PASIDs") Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/vi: silence an uninitialized variable warningDan Carpenter1-0/+1
Smatch complains that we need to initialized "*cap" otherwise it can lead to an uninitialized variable bug in the caller. This seems like a reasonable warning and it doesn't hurt to silence it at least. drivers/gpu/drm/amd/amdgpu/vi.c:767 vi_asic_reset_method() error: uninitialized symbol 'baco_reset'. Fixes: 425db2553e43 ("drm/amdgpu: expose BACO interfaces to upper level from PP") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/vce: make some functions staticAlex Deucher2-10/+10
They are not used outside of the file they are defined in. Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/vce: fix allocation size in enc ring testAlex Deucher2-5/+16
We need to allocate a large enough buffer for the feedback buffer, otherwise the IB test can overwrite other memory. Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amdgpu/psp: declare PSP TA firmwarechen gong1-0/+3
Add PSP TA firmware declaration for raven raven2 picasso Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-26Merge tag 'drm-next-5.5-2019-10-09' of git://people.freedesktop.org/~agd5f/linux into drm-nextDave Airlie248-4146/+11395
drm-next-5.5-2019-10-09: amdgpu: - Additional RAS enablement for vega20 - RAS page retirement and bad page storage in EEPROM - No GPU reset with unrecoverable RAS errors - Reserve vram for page tables rather than trying to evict - Fix issues with GPU reset and xgmi hives - DC i2c over aux fixes - Direct submission for clears, PTE/PDE updates - Improvements to help support recoverable GPU page faults - Silence harmless SAD block messages - Clean up code for creating a bo at a fixed location - Initial DC HDCP support - Lots of documentation fixes - GPU reset for renoir - Add IH clockgating support for soc15 asics - Powerplay improvements - DC MST cleanups - Add support for MSI-X - Misc cleanups and bug fixes amdkfd: - Query KFD device info by asic type rather than pci ids - Add navi14 support - Add renoir support - Add navi12 support - gfx10 trap handler improvements - pasid cleanups - Check against device cgroup ttm: - Return -EBUSY with pipelining with no_gpu_wait radeon: - Silence harmless SAD block messages device_cgroup: - Export devcgroup_check_permission Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191010041713.3412-1-alexander.deucher@amd.com
2019-10-25drm/i915: capture aux page table error registerLionel Landwerlin3-0/+9
TGL introduced a feature in which we map the main surface to the auxiliary surface. If we screw up the page tables, the HW has a register to tell us which engine encounters a fault in the page table walk. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> [ickle: Be brave and apply to gen12] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191025121718.18806-1-lionel.g.landwerlin@intel.com
2019-10-25drm/i915: Fix PCH reference clock for FDI on HSW/BDWVille Syrjälä3-5/+23
The change to skip the PCH reference initialization during fastboot did end up breaking FDI. To fix that let's try to do the PCH reference init whenever we're disabling a DPLL that was using said reference previously. Cc: stable@vger.kernel.org Tested-by: Andrija <akijo97@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112084 Fixes: b16c7ed95caf ("drm/i915: Do not touch the PCH SSC reference if a PLL is using it") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191022185643.1483-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2019-10-25drm/i915/selftests: Force ordering of context switchesChris Wilson1-7/+28
The parallel switch test has an underlying assumption that its requests are executed in order of submission, which is only true if the backend manages to keep up. Ensure the order of execution matches the submission order by explicit dependencies and so when we wait on the last request, we know we wait on completion of the entire queue. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191016225730.29447-1-chris@chris-wilson.co.uk
2019-10-25drm/i915: Move intel_engine_context_in/out into intel_lrc.cTvrtko Ursulin2-55/+55
Intel_lrc.c is the only caller and so to avoid some header file ordering issues in future patches move these two over there. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191025090952.10135-1-tvrtko.ursulin@linux.intel.com
2019-10-25drm: Don't free jobs in wait_event_interruptible()Steven Price1-19/+24
drm_sched_cleanup_jobs() attempts to free finished jobs, however because it is called as the condition of wait_event_interruptible() it must not sleep. Unfortunately some free callbacks (notably for Panfrost) do sleep. Instead let's rename drm_sched_cleanup_jobs() to drm_sched_get_cleanup_job() and simply return a job for processing if there is one. The caller can then call the free_job() callback outside the wait_event_interruptible() where sleeping is possible before re-checking and returning to sleep if necessary. Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Fixes: 5918045c4ed4 ("drm/scheduler: rework job destruction") Signed-off-by: Steven Price <steven.price@arm.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/337652/
2019-10-25drm/i915/tgl: Fix doc not corresponding to codeAnna Karas1-2/+2
Replace PLLs names used in documentation to that used in the code. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Fixes: 68ff39c3f8c0 ("drm/i915/tgl: Add new pll ids") Signed-off-by: Anna Karas <anna.karas@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190926123559.15717-1-anna.karas@intel.com
2019-10-25drm/i915: Describe structure member in documentationAnna Karas1-0/+5
Add description of wakeref member of intel_shared_dpll structure to documentation. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by: Anna Karas <anna.karas@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191008092849.6511-1-anna.karas@intel.com
2019-10-25drm/i915/selftests: Tweak the default subtest runtimeChris Wilson1-1/+1
BAT is growing a little fat and CI is under pressure and needs to trim off some redundant runtime. An easy option is to reduce the selftest runtimes, so try halving our default subtest timeout. While this reduces the number of iterations used, for the majority of tests that are passing, repeat runs (with different CI_DRM) will make up the difference -- a negative consequence though is that we may reduce the frequency of sporadic failures. Hopefully, we have no tests that were crucially dependent on the previous 1s timeout... Suggested-by: Tomi Sarvela <tomi.p.sarvela@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191025092749.13468-1-chris@chris-wilson.co.uk
2019-10-25drm/ttm: stop exporting ttm_mem_io_* functionsChristian König1-4/+0
Those are not supposed to be used by drivers. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Link: https://patchwork.freedesktop.org/patch/333290/
2019-10-25drm/qxl: stop using TTM to call driver internal functionsChristian König3-12/+5
The ttm_mem_io_* functions were intended to be internal to TTM and shouldn't have been used in a driver. They were exported in commit afe6804c045fbd69a1b75c681107b5d6df9190de just for QXL. Instead call the qxl_ttm_io_mem_reserve() function directly and completely drop the free call since that is a dummy on QXL. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Link: https://patchwork.freedesktop.org/patch/333289/
2019-10-25drm/ttm: use the parent resv for ghost objects v3Christian König1-9/+11
This way the TTM is destroyed with the correct dma_resv object locked and we can even pipeline imported BO evictions. v2: Limit this to only cases when the parent object uses a separate reservation object as well. This fixes another OOM problem. v3: fix init and try_lock on the wrong object Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Huang Rui <ray.huang@amd.com> Link: https://patchwork.freedesktop.org/patch/337499/
2019-10-25drm/ttm: remove pointers to globalsChristian König13-83/+55
As the name says global memory and bo accounting is global. So it doesn't make to much sense having pointers to global structures all around the code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Thomas Hellström <thellstrom@vmware.com> Link: https://patchwork.freedesktop.org/patch/332879/
2019-10-25drm/ttm: always keep BOs on the LRUChristian König12-76/+29
This allows blocking for BOs to become available in the memory management. Amdgpu is doing this for quite a while now during CS. Now apply the new behavior to all drivers using TTM. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Thomas Hellstrom <thellstrom@vmware.com> Link: https://patchwork.freedesktop.org/patch/332878/
2019-10-25drm/ttm, drm/vmwgfx: move cpu_writers handling into vmwgfxChristian König6-39/+19
This feature is only used by vmwgfx and superfluous for everybody else. Signed-off-by: Christian König <christian.koenig@amd.com> Co-developed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Tested-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/333650/
2019-10-25drm/gpu: Fix Memory barrier without comment IssueBhanusree1-4/+4
-Issue found using checkpatch.pl -Insert comments for memory barrier usage Signed-off-by: Bhanusree <bhanusreemahesh@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1571984858-4644-1-git-send-email-bhanusreemahesh@gmail.com
2019-10-25drm/gpu: Fix Missing blank line after declarationsBhanusree1-0/+2
-Insert a blank line after the declarations. -Issue found using checkpatch.pl Signed-off-by: Bhanusree <bhanusreemahesh@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1571984833-4596-1-git-send-email-bhanusreemahesh@gmail.com
2019-10-25Merge tag 'drm-fixes-5.4-2019-10-23' of git://people.freedesktop.org/~agd5f/linux into drm-fixesDave Airlie8-46/+92
drm-fixes-5.4-2019-10-23: amdgpu: - Fix suspend/resume issue related to multi-media engines - Fix memory leak in user ptr code related to hmm conversion - Fix possible VM faults when allocating page table memory - Fix error handling in bo list ioctl Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191024031809.3155-1-alexander.deucher@amd.com
2019-10-25Merge tag 'drm-misc-fixes-2019-10-23' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixesDave Airlie2-3/+4
Two fixes for komeda, one for typos and one to prevent an hardware issue when flushing inactive pipes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191023112643.evpp6f23mpjwdsn4@gilmour
2019-10-24drm/i915/display/psr: Print in debugfs if PSR is not enabled because of sinkJosé Roberto de Souza1-1/+5
Right now if sink reported any PSR error or if it fails to acknowledge the PSR wakeup it sets a flag and do not attempt to enable PSR anymore. That is the safest approach to avoid repetitive glitches and allowed us to have PSR enabled by default. But from time to time even good PSR panels have a PSR error, causing tests to fail. And for now we are not yet to the point were we could try to recover from PSR errors, so lets add this information to the debugfs so IGT can check if PSR is disabled because of sink errors or not and eliminate this noise from CI runs. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ap Kamal <kamal.ap@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191023214932.94679-1-jose.souza@intel.com
2019-10-24drm/i915: Catch GTT fault errors for gen11+ planesMatt Roper2-1/+11
Gen11+ has more hardware planes than gen9 so we need to test additional pipe interrupt register bits to recognize any GTT faults that happen on these extra planes. Bspec: 50335 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191008211716.8391-1-matthew.d.roper@intel.com
2019-10-24drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNTTapani Pälli1-0/+20
As with commit 3fe0107e45ab, this change fixes multiple tests that are using the invocation counts. Documentation doesn't list the workaround for TGL but applying it fixes the tests. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191024103858.28113-2-mika.kuoppala@linux.intel.com
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