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2019-06-20drm/amdgpu: acquire available gfx queuesHawking Zhang2-0/+26
currently, amdgpu will owns the first gfx queue of each pipe they are: me:0 pipe:0 queue:0 me:0 pipe:1 queue:0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add members in amdgpu_me for gfx queueHawking Zhang1-0/+8
Update the structure for gfx10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <jack.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/gfx10: new approach to load gfx10 me fw (v4)Hawking Zhang1-0/+7
gfx10 allows to only upload me jumptable while save the whole me image at gtt memory. v2: program CP_ME_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create me fw bo v4: split common code from gfx10 code Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/gfx10: new approach to load ce fw (v4)Hawking Zhang1-0/+7
gfx10 allows to only upload ce jumptable while save the whole ce image at gtt memory. v2: program CP_CE_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create ce fw bo v4: split common code from gfx10 code Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/gfx10: new approach to load pfp fw (v4)Hawking Zhang1-0/+7
gfx10 allows to only upload pfp jumptable while save the whole pfp image at gtt memory. v2: program CP_PFP_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo v4: split common code from gfx10 code Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add nbio v2.3 for navi10 (v4)Hawking Zhang3-1/+366
nbio handles bus io functionality. v1: add place holder and initial basic nbio v2.3 functions (Ray) v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking) v3: squash in updates (Alex) v4: whitespace fix (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-nextDave Airlie21-445/+1685
- The coherent memory changes including mm changes. - Some vmwgfx debug fixes. - Removal of vmwgfx legacy security checks. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <VMware> <thomas@shipmail.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190619072531.4026-1-thomas@shipmail.org
2019-06-20drm/amdgpu: add nbio callbacks for vcn doorbell supportLeo Liu1-0/+2
For Navi10 VCN2.0, the engine supports Doorbell Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: query vram_width from vram_info tableHawking Zhang1-9/+37
Driver will get channel_number and channel_width from vram_info table, then calculate vram_width by multiply channel_number by channel_width Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: query vram type from atomfirmware vram_infoHawking Zhang1-0/+7
vram_type is saved in member vram_module[0].memory_type Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add navi pm4 headerHawking Zhang1-0/+418
A pm4 header for Navi. PM4 is the packet format used by the compute and gfx engines. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add sdma v5 packet header fileHawking Zhang1-0/+4806
Defines the SDMA packet formats. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gfx v10 clear state header v2Huang Rui1-0/+975
Clear state for gfx pipe. v2: squash in updates Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add v10 structs header (v2)Huang Rui1-0/+1258
Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: parse the new members added by gpu_info ucode v1_1Hawking Zhang1-0/+9
Parse the new parameters for gfx10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10Hawking Zhang1-0/+6
two new members that specific for navi10 are included in v2_0: num_sc_per_sh and num_packer_per_sc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add navi10 gpu info firmwareHuang Rui1-0/+4
gpu info firmware stores configuration data for various IP blocks. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gfx10 specific new member pa_sc_tile_steering_overrideHawking Zhang1-0/+1
New gfx config parameter. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gfx10 specific config in amdgpu_gfx_configHawking Zhang1-0/+3
The two members are used to cache the values from gpu_info fw accordingly Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: Add GDDR6 in vram_name arraryHawking Zhang1-0/+1
For printing vram type. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21Merge tag 'imx-drm-fixes-2019-06-20' of git://git.pengutronix.de/git/pza/linux into drm-fixesDave Airlie1-13/+27
drm/imx: ipu-v3 image converter fixes This series fixes input buffer alignment and downsizer configuration to adhere to IPU mem2mem CSC/scaler hardware restrictions in certain downscaling ratios. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patchwork.freedesktop.org/patch/msgid/1561040798.14349.20.camel@pengutronix.de
2019-06-21Merge tag 'drm-intel-fixes-2019-06-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixesDave Airlie2-15/+38
drm/i915 fixes for v5.2-rc6: - GVT: Fix reserved PVINFO register write (Weinan) - Avoid clobbering M/N values in fastset fuzzy checks (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87pnn8sbdp.fsf@intel.com
2019-06-21Merge tag 'drm-misc-fixes-2019-06-19' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixesDave Airlie5-3/+19
panfrost- Only unmap BO's if they're mapped (Boris) core- Handle buffer desc copy_to_user failure properly (Dan) Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dave Airlie <airlied@redhat.com> From: Sean Paul <sean@poorly.run> Link: https://patchwork.freedesktop.org/patch/msgid/20190619192745.GA145841@art_vandelay
2019-06-21Merge branch 'vmwgfx-fixes-5.2' of git://people.freedesktop.org/~thomash/linux into drm-fixesDave Airlie3-34/+125
A couple of fixes for vmwgfx. Two fixes for a DMA sg-list debug warning message. These are not cc'd stable since there is no evidence of actual breakage. On fix for the high-bandwidth backdoor port which is cc'd stable due to upcoming hardware, on which the code would otherwise break. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <VMware> <thomas@shipmail.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190618072255.2720-1-thomas@shipmail.org
2019-06-20drm/msm: Re-order uninit function to work during probe deferSean Paul1-4/+14
If bind fails, we can call msm_drm_uninit before kms elements have been created. In this case, drm_atomic_helper_shutdown will fail since there are no drm objects. Only call drm unregistration and shutdown if drm is registered. Also while we're in here move the workqueue destruction to below component_unbind since components could be actively using the wq during uninit or in their unbind routine. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190524202919.179289-1-sean@poorly.run
2019-06-20drm/amdgpu: add navi10 asic typeHuang Rui1-0/+1
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add navi10 ip offset headerHawking Zhang2-1/+858
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add doorbell assignement for navi10Hawking Zhang1-0/+40
Update mappings for Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: atomfirmware.h updates for navi10Hawking Zhang1-8/+180
Updated tables for Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add navi10 enums headerHawking Zhang1-0/+22764
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add SMUIO 11.0 register headersHawking Zhang2-0/+1012
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add OSS 5.0 register headersHawking Zhang2-0/+1658
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add MMHUB 2.0 register headersHawking Zhang3-0/+10293
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang3-0/+61330
v2: Update regs (Alex) v3: More updates (Alex) v4: more updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add VCN 2.0 register headersHawking Zhang2-0/+4823
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add NBIO 2.3 register headersHawking Zhang3-0/+153523
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add MP 11.0 register headersHawking Zhang1-0/+429
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add HDP 5.0 register headersHawking Zhang2-0/+876
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add DCN 2.0 register headersHawking Zhang2-0/+85539
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add CLK 11.0 register headersHawking Zhang2-0/+71
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add ATHUB 2.0 register headersHawking Zhang3-0/+3050
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/i915/gtt: Defer address space cleanup to an RCU workerChris Wilson4-113/+71
Enable RCU protection of i915_address_space and its ppgtt superclasses, and defer its cleanup into a worker executed after an RCU grace period. In the future we will be able to use the RCU protection to reduce the locking around VM lookups, but the immediate benefit is being able to defer the release into a kworker (process context). This is required as we may need to sleep to reap the WC pages stashed away inside the ppgtt. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110934 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190620183705.31006-1-chris@chris-wilson.co.uk
2019-06-20drm/i915/ehl/dsi: Enable AFE over PPI strapJosé Roberto de Souza2-0/+12
The other additional step in the DSI sequence for EHL. v2: - Using REG_BIT()(Matt) - Fixed commit message typo(Vandita) BSpec: 20597 Cc: Uma Shankar <uma.shankar@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-2-jose.souza@intel.com
2019-06-20drm/i915/ehl/dsi: Set lane latency optimization for DW1Vandita Kulkarni2-0/+15
EHL has 2 additional steps in the DSI sequence, this is one of then the lane latency optimization for DW1. BSpec: 20597 Cc: Uma Shankar <uma.shankar@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-1-jose.souza@intel.com
2019-06-20drm/msm/dsi: Move setup_encoder to modeset_initSean Paul4-38/+5
Now that the panel probe/setup is in the modeset path, we can call dsi_manager_setup_encoder() in a common place for both internal and external bridge setups. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-10-sean@poorly.run
2019-06-20drm/msm/dsi: Move dsi panel init into modeset init pathSean Paul1-7/+10
Since deferred probe from the modeset init path now works, we can move the panel initialization from detect() into connector init. This avoids doing work in detect() and hopefully will result in a more deterministic boot sequence between devices with a dsi panel, and those with an external bridge. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-9-sean@poorly.run
2019-06-20drm/msm/dsi: Use the new setup_encoder function in attach_dsi_deviceSean Paul3-15/+4
Now that we have a function to call set_encoder_mode() for us, use it. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-8-sean@poorly.run
2019-06-20drm/msm/dsi: Simplify the logic in msm_dsi_manager_panel_init()Sean Paul1-40/+58
This patch moves things around a bit to be a little more readable and pulls out the set_encoder_mode() call into its own function for later use. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-7-sean@poorly.run
2019-06-20drm/msm/dsi: Pull out panel init code into functionSean Paul1-4/+12
Pull all of the panel init code out of detect() and put it in its own function. This will be useful in future patches where it's moved from detect(). Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-6-sean@poorly.run
2019-06-20drm/msm/dsi: Don't store dsi host mode_flags in msm_dsiSean Paul2-9/+9
It's a bit dangerous to store the flags in msm_dsi since there's no way to tell when they're populated. Fortunately the only place that uses them is the same place that fills them. So just use a local variable and delete the struct member. Reviewed-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190617201301.133275-5-sean@poorly.run
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