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2016-12-02drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilakeAnder Conselvan de Oliveira1-4/+6
Geminilake has double wide pipes so it can output two pixels per CD clock. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-8-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Reuse broxton's cdclk code for GLKAnder Conselvan de Oliveira1-8/+65
Geminilake has the same register layout, reference clock and programming sequence as broxton. The difference is that it doesn't support the 1.5 divider and has different ratios, but a lot of code can be shared between the two platforms. v2: Rebase (s/broxton/bxt). v3: Fix vco calculation in glk_de_pll_vco(). Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-7-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Update Port PLL enable sequence for GeminilkaeMadhav Chauhan2-0/+22
Add steps for enabling and disabling Port PLL as per bspec. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Set DCC delay range 2 in PLL enable sequenceAnder Conselvan de Oliveira2-0/+21
Follow the PLL enable sequence updated in bspec, which requires the DCC delay range 2 bit to be set. v2: Moved from DDI init sequence to PLL enable. v3: Don't read value from GRP register. (Rodrido) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ander Conselvan De Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-5-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira5-24/+155
Implement the DDI initsequence and add information about the different phys in GLK. v2: Rebase on the move of phys to be power wells. v3: Rebase on addition of struct bxt_ddi_phy_info. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-4-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Add power wells for GeminilakeAnder Conselvan de Oliveira2-3/+117
Geminilake has power wells are similar to SKL, but with the misc IO well being split into separate AUX IO wells. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-3-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira18-85/+84
Geminilake is mostly backwards compatible with broxton, so change most of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the platforms will be implemented in follow-up patches. v2: Don't reuse broxton's path in intel_update_max_cdclk(). Don't set plane count as in broxton. v3: Rebase v4: Include the check intel_bios_is_port_hpd_inverted(). Commit message. v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo) v6: Rebase. v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll code. (Rodrigo) v8: Squash a couple of DDI patches with more conversions. (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-2-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-02drm/i915/gen6+: Clear upper data byte during PCODE writeImre Deak1-0/+1
The spec calls for the upper data byte to be cleared before most of the PCODE write commands, for others like IPS control it doesn't say anything about this byte. Let's clear it in case it's clobbered somehow, especially that there are places where we only do a PCODE write without a preceding PCODE read. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480346969-16121-1-git-send-email-imre.deak@intel.com
2016-12-02Merge tag 'gvt-next-2016-11-30' of https://github.com/01org/gvt-linux into drm-intel-next-fixesJani Nikula3-4/+9
From Zhenyu Wang <zhenyuw@linux.intel.com> gvt-next-2016-11-30 - initialize vgpu as primary for correct cfg space setting - fix 64 bit bar emulation - fix un-released lock issue on dispatch workload err path Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-12-02drm/i915/audio: extend audio sync rate support for DP MSTLibin Yang1-3/+1
Remove the type judgement in i915_audio_component_sync_audio_rate(). Audio rate sync is necessary for all i915 digital audio now. Signed-off-by: Libin Yang <libin.yang@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480569439-54252-2-git-send-email-libin.yang@intel.com
2016-12-02drm/i915/audio: extend get_saved_enc() to support more scenariosLibin Yang1-4/+28
In initialization, audio driver will call functions get_eld() and etc. But at that time, audio driver may not know whether it is DP MST or not. In the original function get_saved_enc(), if it is DP MST, it requires to set the pipe to the correct value, otherwise, pipe to be -1. Although audio driver can get the knowledge whether it is in DP MST mode or not by reading the codec register. It will drop performance each time before it calls the get_eld and other similar functions. As gfx driver can easily know whether it is in DP MST mode or not. Let's extend the get_saved_enc() function to handle the situation that audio driver still sends the device id info even it is in DP SST mode and return the correct intel_encoder instead of panic. Signed-off-by: Libin Yang <libin.yang@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480569439-54252-1-git-send-email-libin.yang@intel.com
2016-12-02drm/i915: make i915_suspend_switcheroo staticMatthew Auld1-1/+1
Looks like this was missed when unexporting, so let's keep sparse happy. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 7f26cb88014a ("drm/i915: Unexport VGA switcheroo functions") Signed-off-by: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161202102411.19831-1-matthew.auld@intel.com
2016-12-02drm/i915: Fix kerneldoc for intel_guc_finiTvrtko Ursulin1-1/+1
Recent refactoring forgot to update this one. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: bf9e8429ab97 ("drm/i915: Make various init functions take dev_priv") Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1480668233-25372-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-12-02drm/i915: Fix intel_psr_init() kerneldocAnder Conselvan de Oliveira1-1/+1
In commit c39055b072f8 ("drm/i915: Pass dev_priv to intel_setup_outputs()"), I forgot to update the kerneldoc for intel_psr_init() init, leading to warnings when building the documentation: drivers/gpu/drm/i915/intel_psr.c:822: warning: No description found for parameter 'dev_priv' drivers/gpu/drm/i915/intel_psr.c:822: warning: Excess function parameter 'dev' description in 'intel_psr_init' Fixes: c39055b072f8 ("drm/i915: Pass dev_priv to intel_setup_outputs()") Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480420127-11382-1-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-01drm/i915: Make intel_pm_setup take dev_privTvrtko Ursulin3-5/+3
Function actually wants dev_priv so give it to it. v2: Commit message. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480601805-14391-2-git-send-email-tvrtko.ursulin@linux.intel.com
2016-12-01drm/i915: Make i915_save/restore_state and intel_i2c_reset take dev_privTvrtko Ursulin4-19/+15
dev_priv is more appropriate since it is used much more in these. v2: Commit message and keep the local pdev variable. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: Make i915_destroy_error_state take dev_privTvrtko Ursulin5-13/+12
Since it does not need dev at all. Also change the stored pointer in struct i915_error_state_file_priv to i915. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: Make gmbus setup take dev_privTvrtko Ursulin4-10/+8
Simplify the code by passing the right argument in. v2: Commit message. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: Unexport VGA switcheroo functionsTvrtko Ursulin2-4/+4
They are only used in i915_drv.c so a forward declaration is enough. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: dev_priv cleanup in bridge/bar/mmio init codeTvrtko Ursulin1-28/+17
dev_priv is more appropriate for these so converting saves some lines of source. v2: Commit message and keep the pdev local variable. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: More GEM init dev_priv cleanupTvrtko Ursulin4-18/+13
Simplifies the code to pass the right parameter in. v2: Commit message. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: Make various init functions take dev_privTvrtko Ursulin11-90/+77
Like GEM init, GUC init, MOCS init and context creation. Enables them to lose dev_priv locals. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915: Make GEM object create and create from data take dev_privTvrtko Ursulin12-30/+32
Makes all GEM object constructors consistent. v2: Fix compilation in GVT code. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v1)
2016-12-01drm/i915: Make GEM object alloc/free and stolen created take dev_privTvrtko Ursulin12-29/+24
Where it is more appropriate and also to be consistent with the direction of the driver. v2: Leave out object alloc/free inlining. (Joonas Lahtinen) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm: Make the connector .detect() callback optionalLaurent Pinchart26-193/+11
Many drivers (21 to be exact) create connectors that are always connected (for instance to an LVDS or DSI panel). Instead of forcing them to implement a dummy .detect() handler, make the callback optional and consider the connector as always connected in that case. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jyri Sarha <jsarha@ti.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Vincent Abriou <vincent.abriou@st.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> [seanpaul fixed small conflict in rcar-du/rcar_du_lvdscon.c] Signed-off-by: Sean Paul <seanpaul@chromium.org>
2016-12-01drm/i915/lspcon: Enable AUX interrupts for resume time initializationImre Deak1-1/+4
For LSPCON initialization during system resume we need AUX functionality, but we call the corresponding encoder reset hook with all interrupts disabled. Without interrupts we'll do a poll-wait for AUX transfer completions, which adds a significant delay if the transfers timeout/need to be retried for some reason. Fix this by enabling interrupts before calling the reset hooks. Note that while this will enable AUX interrupts it will keep HPD interrupts disabled, in a similar way to the init time output setup code. This issue existed since LSPCON support was added. v2: - Rebased on drm-tip. Cc: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480448429-27739-1-git-send-email-imre.deak@intel.com
2016-12-01drm/i915/glk: Add a IS_GEN9_LP() macroAnder Conselvan de Oliveira2-0/+4
Broxton and Geminilake are both gen9lp platforms. To avoid adding IS_GEMINILAKE() checks everywhere alongside the IS_BROXTON() ones, add a IS_GEN9_LP() macro. v2: Rename macro parameter to dev_priv. (Joonas) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-12-01drm/i915/glk: Add Geminilake PCI IDsAnder Conselvan de Oliveira1-0/+1
v2: Add new 0x3185 ID. (Joonas) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1478791400-21756-4-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-01drm/i915/glk: Introduce Geminilake platform definitionAnder Conselvan de Oliveira2-0/+9
Geminilake is an Intel® Processor containing Intel® HD Graphics following Broxton. Let's start by adding the platform definition. PCI IDs and plaform specific code will follow. v2: Rebase (don't allow dev to be used with the new macro). v3: Update ddb size. (Matt) Rebase on s/preliminary_hw/alpha/ Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1479133526-32389-1-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-01drm/i915: Create a common GEN9_LP_FEATURE.Rodrigo Vivi1-22/+25
The following LP platform inherits a lot of this platform So let's simplify here to re-use this later. v2: Keep ddb_size out of the new macro. v3: Rebase (has_decoupled_mmio). (Imre) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480584796-19466-1-git-send-email-ander.conselvan.de.oliveira@intel.com
2016-12-01drm/bridge: tc358767: don't warn if display side ASSR enable failsLucas Stach1-1/+1
ASSR is an optional feature, so it's a valid operating condition for the display to reject ASSR enable. Demote the warning to the debug level. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by:Andrey Gusakov <andrey.gusakov@cogentembedded.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/20161130114810.3245-1-l.stach@pengutronix.de
2016-12-01drm: Initialise drm_mm.head_node.allocatedChris Wilson1-0/+1
commit 202b52b7fbf7 ("drm: Track drm_mm nodes with an interval tree") introduced a requirement that the special drm_mm.head_node was initialised and marked as not being allocated. It is a very special node that has no side but has a hole that represents the drm_mm address space, and holds the list of nodes. Since it is not a real node, it is not part of the node rbtree and we detect this as it being unallocated. This presumed that drm_mm_init() was initialising it to zero. It happens that i915 kzallocs its objects and so it was accidentally setting it, but for generic use we cannot make that assumption. [ 22.981519] general protection fault: 0000 [#1] SMP [ 22.981521] Modules linked in: test_drm_mm(+) ctr ccm arc4 rt2800usb rt2x00usb rt2800lib rt2x00lib crc_ccitt mac80211 cmac rfcomm bnep snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic snd_hda_intel dcdbas snd_hda_codec x86_pkg_temp_thermal intel_powerclamp btusb snd_hda_core coretemp crct10dif_pclmul cfg80211 btrtl btbcm btintel bluetooth crc32_pclmul ghash_clmulni_intel aesni_intel snd_pcm i2c_hid aes_x86_64 lrw gf128mul glue_helper ablk_helper cryptd snd_timer hid_multitouch snd joydev serio_raw lpc_ich mfd_core i2c_designware_platform i2c_designware_core 8250_dw binfmt_misc soundcore acpi_pad nls_iso8859_1 usbhid hid psmouse ahci libahci [last unloaded: test_drm_mm] [ 22.981544] CPU: 1 PID: 2088 Comm: drm_mm Tainted: G W 4.9.0-rc7+ #234 [ 22.981545] Hardware name: Dell Inc. XPS 13 9343/0310JH, BIOS A07 11/11/2015 [ 22.981546] task: ffff88020c971cc0 task.stack: ffffc90001728000 [ 22.981547] RIP: 0010:[<ffffffff814050f0>] [<ffffffff814050f0>] drm_mm_interval_tree_add_node+0xa0/0xd0 [ 22.981551] RSP: 0018:ffffc9000172ba98 EFLAGS: 00010202 [ 22.981552] RAX: 0f0000c69cf63d80 RBX: ffff88020be00000 RCX: ffff88020be00000 [ 22.981553] RDX: 0000000000000fff RSI: ffffc9000172bc48 RDI: ffffffff810ac4df [ 22.981553] RBP: ffffc9000172bb08 R08: ffffc9000172bc70 R09: 0000000000000fff [ 22.981554] R10: ffffffff810ac4d7 R11: 4dc04d8b4cffffe5 R12: 0000000000001000 [ 22.981555] R13: ffffc9000172bbd0 R14: ffffc9000172bbe0 R15: 0000000002000000 [ 22.981556] FS: 00007f80c9fab740(0000) GS:ffff88021f480000(0000) knlGS:0000000000000000 [ 22.981557] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 22.981558] CR2: 00007f80c9fd5000 CR3: 000000020c191000 CR4: 00000000003406e0 [ 22.981559] Stack: [ 22.981560] ffffffff81405d09 ffff88020be00000 ffffc9000172bbe0 000000000172bb08 [ 22.981562] ffffffffffffffff 0000000000000000 0000000000000000 0000000000000000 [ 22.981563] 0000000002000000 0000000002000000 ffffffffa02f3000 ffff88020be00000 [ 22.981565] Call Trace: [ 22.981568] [<ffffffff81405d09>] ? drm_mm_insert_node_generic+0x229/0x310 [ 22.981570] [<ffffffffa02f3000>] ? 0xffffffffa02f3000 [ 22.981572] [<ffffffffa02903c1>] __subtest_insert_range.constprop.7+0xd1/0x5b0 [test_drm_mm] [ 22.981575] [<ffffffff81081222>] ? default_wake_function+0x12/0x20 [ 22.981576] [<ffffffff81096905>] ? __wake_up_common+0x55/0x90 [ 22.981578] [<ffffffff81085f42>] ? sched_clock_cpu+0x72/0xa0 [ 22.981581] [<ffffffff811308ad>] ? irq_work_queue+0xd/0x80 [ 22.981582] [<ffffffff810abcc4>] ? wake_up_klogd+0x34/0x40 [ 22.981584] [<ffffffff810ac19d>] ? console_unlock+0x4cd/0x530 [ 22.981585] [<ffffffff810ac4d7>] ? vprintk_emit+0x2d7/0x490 [ 22.981587] [<ffffffff810ac82f>] ? vprintk_default+0x1f/0x30 [ 22.981589] [<ffffffff81146e1c>] ? printk+0x4d/0x4f [ 22.981590] [<ffffffffa02f3000>] ? 0xffffffffa02f3000 [ 22.981592] [<ffffffffa02908b5>] subtest_insert_range+0x15/0x80 [test_drm_mm] [ 22.981594] [<ffffffffa02f3088>] test_drm_mm_init+0x88/0x1000 [test_drm_mm] [ 22.981597] [<ffffffff8100043d>] do_one_initcall+0x3d/0x150 [ 22.981600] [<ffffffff8119dfbf>] ? kfree+0x13f/0x180 [ 22.981602] [<ffffffff811471f2>] do_init_module+0x60/0x1f1 [ 22.981606] [<ffffffff810db878>] load_module+0x2228/0x2790 [ 22.981608] [<ffffffff810d8590>] ? __symbol_put+0x40/0x40 [ 22.981612] [<ffffffff811c52b1>] ? kernel_read+0x41/0x60 [ 22.981614] [<ffffffff810dbfb6>] SYSC_finit_module+0x96/0xd0 [ 22.981617] [<ffffffff810dc00e>] SyS_finit_module+0xe/0x10 [ 22.981620] [<ffffffff816e7aa4>] entry_SYSCALL_64_fastpath+0x17/0x98 [ 22.981622] Code: c7 41 30 00 00 00 00 48 89 e5 48 89 3a 48 c7 c2 20 4e 40 81 e8 b2 a1 f0 ff 5d c3 48 8d 56 78 45 31 d2 48 89 d6 eb 25 48 8b 51 58 <48> 39 50 38 73 04 48 89 50 38 4c 8b 58 28 4c 39 59 48 48 8d 50 [ 22.981651] RIP [<ffffffff814050f0>] drm_mm_interval_tree_add_node+0xa0/0xd0 [ 22.981655] RSP <ffffc9000172ba98> Testcase: igt/drm_mm Fixes: 202b52b7fbf7 ("drm: Track drm_mm nodes with an interval tree") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: David Herrmann <dh.herrmann@gmail.com> Cc: dri-devel@lists.freedesktop.org Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: <drm-intel-fixes@lists.freedesktop.org> # v4.9-rc1+ Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161130205126.31106-1-chris@chris-wilson.co.uk
2016-12-01drm: Add support for Amlogic Meson Graphic ControllerNeil Armstrong23-0/+3876
The Amlogic Meson Display controller is composed of several components : DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| | vd1 _______ _____________ _________________ | | D |-------| |----| | | | | HDMI PLL | D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | R |-------| |----| Processing | | | | | | osd2 | | | |---| Enci ----------|----|-----VDAC------| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| A | osd1 | | | Blenders | | Encl ----------|----|---------------| M |-------|______|----|____________| |________________| | | ___|__________________________________________________________|_______________| VIU: Video Input Unit --------------------- The Video Input Unit is in charge of the pixel scanout from the DDR memory. It fetches the frames addresses, stride and parameters from the "Canvas" memory. This part is also in charge of the CSC (Colorspace Conversion). It can handle 2 OSD Planes and 2 Video Planes. VPP: Video Post Processing -------------------------- The Video Post Processing is in charge of the scaling and blending of the various planes into a single pixel stream. There is a special "pre-blending" used by the video planes with a dedicated scaler and a "post-blending" to merge with the OSD Planes. The OSD planes also have a dedicated scaler for one of the OSD. VENC: Video Encoders -------------------- The VENC is composed of the multiple pixel encoders : - ENCI : Interlace Video encoder for CVBS and Interlace HDMI - ENCP : Progressive Video Encoder for HDMI - ENCL : LCD LVDS Encoder The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock tree and provides the scanout clock to the VPP and VIU. The ENCI is connected to a single VDAC for Composite Output. The ENCI and ENCP are connected to an on-chip HDMI Transceiver. This driver is a DRM/KMS driver using the following DRM components : - GEM-CMA - PRIME-CMA - Atomic Modesetting - FBDev-CMA For the following SoCs : - GXBB Family (S905) - GXL Family (S905X, S905D) - GXM Family (S912) The current driver only supports the CVBS PAL/NTSC output modes, but the CRTC/Planes management should support bigger modes. But Advanced Colorspace Conversion, Scaling and HDMI Modes will be added in a second time. The Device Tree bindings makes use of the endpoints video interface definitions to connect to the optional CVBS and in the future the HDMI Connector nodes. HDMI Support is planned for a next release. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2016-12-01Merge tag 'drm-misc-fixes-2016-11-30' of git://anongit.freedesktop.org/git/drm-misc into drm-fixesDave Airlie1-4/+6
single drm fix. * tag 'drm-misc-fixes-2016-11-30' of git://anongit.freedesktop.org/git/drm-misc: drm: Don't call drm_for_each_crtc with a non-KMS driver
2016-12-01Merge tag 'tilcdc-4.10' of https://github.com/jsarha/linux into drm-nextDave Airlie11-388/+1018
tilcdc changes for v4.10 * tag 'tilcdc-4.10' of https://github.com/jsarha/linux: (23 commits) drm/tilcdc: fix parsing of some DT properties drm/tilcdc: Enable frame done irq and functionality for LCDC rev 1 drm/tilcdc: Configure video mode to HW in enable() not in mode_set_nofb() drm/tilcdc: Load palette at the end of mode_set_nofb() drm/tilcdc: Add timeout wait for palette loading to complete drm/tilcdc: Enable palette loading for revision 2 LCDC too drm/tilcdc: Fix load mode bit-field setting in tilcdc_crtc_enable() drm/tilcdc: Add tilcdc_write_mask() to tilcdc_regs.h drm/tilcdc: Fix tilcdc_crtc_create() return value handling drm/tilcdc: implement palette loading for rev1 drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDC drm/tilcdc: Add drm bridge support for attaching drm bridge drivers drm/bridge: Add ti-tfp410 DVI transmitter driver dt-bindings: Move "ti,tfp410.txt" from display/ti to display/bridge drm/tilcdc: Recover from sync lost error flood by resetting the LCDC drm/tilcdc: Fix race from forced shutdown of crtc in unload drm/tilcdc: Use unload to handle initialization failures drm/tilcdc: Stop using struct drm_driver load() callback drm/tilcdc: Remove obsolete drm_connector_register() calls drm/tilcdc: Correct misspelling in error message ...
2016-12-01Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-nextDave Airlie54-947/+6756
On the userspace side, all the basics are working, and most of glmark2 is working. I've been working through deqp, and I've got a couple more things to fix (but we've gone from 70% to 80+% pass in last day, and current deqp run that is going should pick up another 5-10%). I expect to push the mesa patches today or tomorrow. There are a couple more a5xx related patches to take the gpu out of secure mode (for the devices that come up in secure mode, like the hw I have), but those depend on an scm patch that would come in through another tree. If that can land in the next day or two, there might be a second late pull request for drm/msm. In addition to the new-shiny, there have also been a lot of overlay/ plane related fixes for issues found using drm-hwc2 (in the process of testing/debugging the atomic/kms fence patches), resulting in rework to assign hwpipes to kms planes dynamically (as part of global atomic state) and also handling SMP (fifo) block allocation atomically as part of the ->atomic_check() step. All those patches should also help out atomic weston (when those patches eventually land). * 'msm-next' of git://people.freedesktop.org/~robclark/linux: (36 commits) drm/msm: gpu: Add support for the GPMU drm/msm: gpu: Add A5XX target support drm/msm: Disable interrupts during init drm/msm: Remove 'src_clk' from adreno configuration drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7 drm/msm: Add adreno_gpu_write64() drm/msm: gpu Add new gpu register read/write functions drm/msm: gpu: Return error on hw_init failure drm/msm: gpu: Cut down the list of "generic" registers to the ones we use drm/msm: update generated headers drm/msm/adreno: move scratch register dumping to per-gen code drm/msm/rd: support for 64b iova drm/msm: convert iova to 64b drm/msm: set dma_mask properly drm/msm: Remove bad calls to of_node_put() drm/msm/mdp5: move LM bounds check into plane->atomic_check() drm/msm/mdp5: dump smp state on errors too drm/msm/mdp5: add debugfs to show smp block status drm/msm/mdp5: handle SMP block allocations "atomically" drm/msm/mdp5: dynamically assign hw pipes to planes ...
2016-11-30drm/i915: Remove dummy i915_kick_out_firmware_fbDaniel Vetter1-7/+0
Since commit 44adece57e2604cec8527a499b48e4d584ab53b8 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Aug 10 18:52:34 2016 +0200 drm/fb-helper: Add a dummy remove_conflicting_framebuffers the drm helpers take care of this for us. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161130110131.25668-1-daniel.vetter@ffwll.ch
2016-11-30drm/tilcdc: fix parsing of some DT propertiesBartosz Golaszewski1-2/+2
The DT binding for tildc is not consistent with the driver code: there are two options - 'max-width' and 'max-pixelclock' specified in the documentation which are parsed as 'ti,max-width' and 'ti,max-pixelclock' respectively. Make the driver code consistent with the binding. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-11-30drm/tilcdc: Enable frame done irq and functionality for LCDC rev 1Jyri Sarha2-7/+12
We should wait for the last frame to complete before shutting things down also on LCDC rev 1. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Configure video mode to HW in enable() not in mode_set_nofb()Jyri Sarha2-220/+212
Configure video mode to HW in enable() call back. There is no reason to do it before that. This makes PM functions way easier because there is no HW context to save when screen is for instance blanked. This patch removes mode_set_nofb() call back from tilcdc. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Load palette at the end of mode_set_nofb()Jyri Sarha1-20/+5
Load palette at the end of mode_set_nofb(). Moving the palette loading to mode_set_nofb() saves us from storing and restoring of framebuffer addresses in dma registers that were just recently written there. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Add timeout wait for palette loading to completeJyri Sarha1-1/+5
Add timeout wait for palette loadind to complete. We do not want to hang forever if palette loaded interrupt does not arrive for some reason. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Enable palette loading for revision 2 LCDC tooJyri Sarha1-43/+47
The LCDC revision 2 documentation also mentions the mandatory palette for true color modes. Even if the rev 2 LCDC appears to work just fine without the palette being loaded loading it helps in testing the feature. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Fix load mode bit-field setting in tilcdc_crtc_enable()Jyri Sarha1-1/+3
Set LCDC_PALETTE_LOAD_MODE bit-field with new tilcdc_write_mask() instead of tilcdc_set(). Setting a bit-fields with tilcdc_set() is fundamentally broken. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Add tilcdc_write_mask() to tilcdc_regs.hJyri Sarha1-0/+13
Add tilcdc_write_mask() for handling register field wider than one bit and mask values for those fields. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Fix tilcdc_crtc_create() return value handlingJyri Sarha3-13/+12
Failed tilcdc_crtc_create() error handling was broken, this patch should fix it. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: implement palette loading for rev1Bartosz Golaszewski1-1/+87
Revision 1 of the IP doesn't work if we don't load the palette (even if it's not used, which is the case for the RGB565 format). Add a function called from tilcdc_crtc_enable() which performs all required actions if we're dealing with a rev1 chip. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Enable sync lost error and recovery handling for rev 1 LCDCJyri Sarha2-15/+21
Revision 1 LCDC support also sync lost errors and can benefit from sync lost recovery routine. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/tilcdc: Add drm bridge support for attaching drm bridge driversJyri Sarha4-72/+205
Adds drm bride support for attaching drm bridge drivers to tilcdc. The decision whether a video port leads to an external encoder or bridge is made simply based on remote device's compatible string. The code has been tested with BeagleBone-Black with and without BeagleBone DVI-D Cape Rev A3 using ti-tfp410 driver. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2016-11-30drm/bridge: Add ti-tfp410 DVI transmitter driverJyri Sarha3-0/+325
Add very basic ti-tfp410 DVI transmitter driver. The only feature separating this from a completely dummy bridge is the EDID read support trough DDC I2C. Even that functionality should be in a separate generic connector driver. However, because of missing DRM infrastructure support the connector is implemented within the bridge driver. Some tfp410 HW specific features may be added later if needed, because there is a set of registers behind i2c if it is connected. This implementation is tested against my new tilcdc bridge support and it works with BeagleBone DVI-D Cape Rev A3. A DT binding document is also updated. Signed-off-by: Jyri Sarha <jsarha@ti.com> Acked-by: Rob Herring <robh@kernel.org>
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