aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2016-11-28drm/amd/powerplay: initialize the soft_regs offset in struct smu7_hwmgrRex Zhu1-1/+4
This could lead to mclk dpm problems on some boards. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Ack-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-28drm/msm: gpu: Add support for the GPMUJordan Crouse6-3/+431
Most 5XX targets have GPMU (Graphics Power Management Unit) that handles a lot of the heavy lifting for power management including thermal and limits management and dynamic power collapse. While the GPMU itself is optional, it is usually nessesary to hit aggressive power targets. The GPMU firmware needs to be loaded into the GPMU at init time via a shared hardware block of registers. Using the GPU to write the microcode is more efficient than using the CPU so at first load create an indirect buffer that can be executed during subsequent initalization sequences. After loading the GPMU gets initalized through a shared register interface and then we mostly get out of its way and let it do its thing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Add A5XX target supportJordan Crouse8-9/+945
Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Disable interrupts during initJordan Crouse2-0/+7
Disable the interrupt during the init sequence to avoid having interrupts fired for errors and other things that we are not ready to handle while initializing. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Remove 'src_clk' from adreno configurationJordan Crouse2-24/+14
The adreno code inherited a silly workaround from downstream from the bad old days before decent clock control. grp_clk[0] (named 'src_clk') doesn't actually exist - it was used as a proxy for whatever the core clock actually was (usually 'core_clk'). All targets should be able to correctly request 'core_clk' and get the right thing back so zap the anachronism and directly use grp_clk[0] to control the clock rate. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Add OUT_TYPE4 and OUT_TYPE7Jordan Crouse1-0/+30
Add helper functions for TYPE4 and TYPE7 ME opcodes that replace TYPE0 and TYPE3 starting with the A5XX targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: Add adreno_gpu_write64()Jordan Crouse4-5/+34
Add a new generic function to write a "64" bit value. This isn't actually a 64 bit operation, it just writes the upper and lower 32 bit of a 64 bit value to a specified LO and HI register. If a particular target doesn't support one of the registers it can mark that register as SKIP and writes/reads from that register will be quietly dropped. This can be immediately put in place for the ringbuffer base and the RPTR address. Both writes are converted to use adreno_gpu_write64() with their respective high and low registers and the high register appropriately marked as SKIP for both 32 bit targets (a3xx and a4xx). When a5xx comes it will define valid target registers for the 'hi' option and everything else will just work. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu Add new gpu register read/write functionsJordan Crouse2-10/+41
Add some new functions to manipulate GPU registers. gpu_read64 and gpu_write64 can read/write a 64 bit value to two 32 bit registers. For 4XX and older these are normally perfcounter registers, but future targets will use 64 bit addressing so there will be many more spots where a 64 bit read and write are needed. gpu_rmw() does a read/modify/write on a 32 bit register given a mask and bits to OR in. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Return error on hw_init failureJordan Crouse5-26/+30
When the GPU hardware init function fails (like say, ME_INIT timed out) return error instead of blindly continuing on. This gives us a small chance of saving the system before it goes boom. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: gpu: Cut down the list of "generic" registers to the ones we useJordan Crouse3-215/+0
There are very few register accesses in the common code. Cut down the list of common registers to just those that are used. This saves const space and saves us the effort of maintaining registers for A3XX and A4XX that don't exist or are unused. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: update generated headersRob Clark15-107/+4177
Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm/adreno: move scratch register dumping to per-gen codeRob Clark3-6/+14
Scratch registers move, annoyingly enough, in a5xx. Move to per-generation aNxx_recover() fxn. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm/rd: support for 64b iovaRob Clark1-2/+2
For backwards compat, the rd format puts the high 32b after the size field in the GPUADDR packet. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: convert iova to 64bRob Clark15-32/+34
For a5xx the gpu is 64b so we need to change iova to 64b everywhere. On the display side, iova is still 32b so it can ignore the upper bits. (Although all the armv8 devices have an iommu that can map 64b pa to 32b iova.) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/edid: Consider alternate cea timings to be the same VICVille Syrjälä1-12/+54
CEA-861 specifies that the vertical front porch may vary by one or two lines for specific VICs. Up to now we've only considered a mode to match the VIC if it matched the shortest possible vertical front porch length (as that is the variant we store in cea_modes[]). Let's allow our VIC matching to work with the other timings variants as well so that that we'll send out the correct VIC if the variant actually used isn't the one with the shortest vertical front porch. Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Adam Jackson <ajax@redhat.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1478177609-16762-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
2016-11-28drm: bridge: dw-hdmi: add ASoC dependencyArnd Bergmann1-0/+1
The newly added sound driver depends on SND_SOC_HDMI_CODEC, which in turn only makes sense when ASoC is enabled, as shown by this warning: warning: (DRM_MSM && DRM_STI && DRM_MEDIATEK_HDMI && DRM_I2C_NXP_TDA998X && DRM_DW_HDMI_I2S_AUDIO) selects SND_SOC_HDMI_CODEC which has unmet direct dependencies (SOUND && !M68K && !UML && SND && SND_SOC) Since the audio driver is probably useless without the audio subsystem, adding a dependency here seems the right solution. Fixes: 2761ba6c0925 ("drm: bridge: add DesignWare HDMI I2S audio support") Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/20161125205411.1157522-1-arnd@arndb.de
2016-11-28drm: Fix shift operations for drm_fb_helper::drm_target_preferred()Chris Wilson1-6/+7
smatch correctly warns: drivers/gpu/drm/drm_fb_helper.c:1960 drm_target_preferred() warn: should '1 << i' be a 64 bit type? drivers/gpu/drm/drm_fb_helper.c:2001 drm_target_preferred() warn: should '1 << i' be a 64 bit type? Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-11-28drm: Avoid NULL dereference for DRM_LEGACY debug messageChris Wilson1-1/+2
smatch warns: drivers/gpu/drm/drm_lock.c:188 drm_legacy_lock() warn: variable dereferenced before check 'master->lock.hw_lock' (see line 177) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161127170910.29106-2-chris@chris-wilson.co.uk
2016-11-28drm: Use u64_to_user_ptr() helper for blob ioctlsChris Wilson1-6/+6
Remove the ugly sparse casts by using the helper u64_to_user_ptr() instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161127170910.29106-1-chris@chris-wilson.co.uk
2016-11-28drm/nouveau: Queue hpd_work on (runtime) resumeHans de Goede1-1/+10
We need to call drm_helper_hpd_irq_event() on resume to properly detect monitor connection / disconnection on some laptops, use hpd_work for this to avoid deadlocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau: Rename acpi_work to hpd_workHans de Goede2-17/+17
We need to call drm_helper_hpd_irq_event() on resume to properly detect monitor connection / disconnection on some laptops. For runtime-resume (which gets called on resume from normal suspend too) we must call drm_helper_hpd_irq_event() from a workqueue to avoid a deadlock. Rename acpi_work to hpd_work, and move it out of the #ifdef CONFIG_ACPI blocks to make it suitable for generic work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/kms/nv50: Fix atomic pageflip events.Mario Kleiner1-0/+2
The new atomic modesetting/pageflip code for nv50+ for Linux 4.10+ no longer uses pageflip irq's to signal flip completion. Instead it polls for flip completion from within a kthread/work queue. This creates a race between the vblank irq handler updating the vblank count and timestamp for the vblank of flip completion, and the kthread's polling code detecting flip completion and sending out the flip completion event. Depending on who executes a few microseconds earlier, the flip completion event will either contain correct count/timestamp or a stale count/timestamp from the previous vblank. This error was observed for about 50% of all executed flips, e.g., observable under DRI2 by the Xorg.log filling with flip handler warning messages. Call drm_accurate_vblank_count() before sending out flip completion events to enforce a vblank count/ts update for the vblank of flip completion and avoid stale counts/timestamps. This fix leads to one redundant call to drm_update_vblank_count for each completed flip, but no other side effects. On a ~6 year old Core i7 M620@ 2.67GHz the redundant call costs about 10 usecs per flip Successfully tested on GeForce 9500/9600/330M so far. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/fb/ram/gp100-: fix memory detection where FBP_NUM != FBPA_NUMBen Skeggs1-2/+2
In this situation, we'd have ended up detecting less VRAM than we have. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/volt: pointers are 32-bitBen Skeggs3-17/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/vmap: pointers are 32-bitBen Skeggs3-17/+17
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/timing: pointers are 32-bitBen Skeggs2-13/+13
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/therm: pointers are 32-bitBen Skeggs1-10/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/perf: pointers are 32-bitBen Skeggs3-14/+16
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/iccsense: pointers are 32-bitBen Skeggs1-4/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/fan: pointers are 32-bitBen Skeggs2-10/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/cstep: pointers are 32-bitBen Skeggs3-23/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-28drm/nouveau/bios/boost: pointers are 32-bitBen Skeggs3-23/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-11-27drm/msm: set dma_mask properlyRob Clark1-1/+7
Previous value really only made sense on armv7 without LPAE. Everything that supports more than 4g of memory also has iommu's that can map anything. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: Remove bad calls to of_node_put()Archit Taneja1-7/+2
In add_components_mdp, we parse the endpoints in MDP output ports using the helper for_each_endpoint_of_node(). Our function calls of_node_put() on the endpoint node before we iterate over the next one. This is already done by the helper, and results in trying to decrement the refcount twice. Remove the extra of_node_put calls. This fixes warnings seen when we try to insert the driver as a module on IFC6410. Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: move LM bounds check into plane->atomic_check()Rob Clark2-2/+15
The mode_config->max_{width,height} is for the maximum size of a fb, not the max scanout limits (of the layer-mixer). It is legal, and in fact common, to create a larger fb, only only scan-out a smaller part of it. For example multi-monitor configurations for x11, or android wallpaper layer (which is created larger than the screen resolution for fast scrolling by just changing the src x/y coordinates). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: dump smp state on errors tooRob Clark2-2/+6
If the dumpstate modparam is enabled, for debugging error irq's, also dump SMP state. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: add debugfs to show smp block statusRob Clark6-3/+116
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: handle SMP block allocations "atomically"Rob Clark7-245/+193
Previously, SMP block allocation was not checked in the plane's atomic_check() fxn, so we could fail allocation SMP block allocation at atomic_update() time. Re-work the block allocation to request blocks during atomic_check(), but not update the hw until committing the atomic update. Since SMP blocks allocated at atomic_check() time, we need to manage the SMP state as part of mdp5_state (global atomic state). This actually ends up significantly simplifying the SMP management, as the SMP module does not need to manage the intermediate state between assigning new blocks before setting flush bits and releasing old blocks after vblank. (The SMP registers and SMP allocation is not double-buffered, so newly allocated blocks need to be updated in kms->prepare_commit() released blocks in kms->complete_commit().) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: dynamically assign hw pipes to planesRob Clark6-78/+170
(re)assign the hw pipes to planes based on required caps, and to handle situations where we could not modify an in-use plane (ie. SMP block reallocation). This means all planes advertise the superset of formats and properties. Userspace must (as always) use atomic TEST_ONLY step for atomic updates, as not all planes may be available for use on every frame. The mapping of hwpipe to plane is stored in mdp5_state, so that state updates are atomically committed in the same way that plane/etc state updates are managed. This is needed because the mdp5_plane_state keeps a pointer to the hwpipe, and we don't want global state to become out of sync with the plane state if an atomic update fails, we hit deadlock/ backoff scenario, etc. The use of state_lock keeps multiple parallel updates which both re-assign hwpipes properly serialized. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: add skeletal mdp5_stateRob Clark2-0/+65
Add basic state duplication/apply mechanism. Following commits will move actual global hw state into this. The state_lock allows multiple concurrent updates to proceed as long as they don't both try to alter global state. The ww_mutex mechanism will trigger backoff in case of deadlock between multiple threads trying to update state. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2016-11-27drm/msm: subclass drm_atomic_stateRob Clark4-0/+51
This will give the kms backends a slot to stash their own hw specific global state. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: introduce mdp5_hw_pipeRob Clark7-87/+199
Split out the hardware pipe specifics from mdp5_plane. To start, the hw pipes are statically assigned to planes, but next step is to assign the hw pipes during plane->atomic_check() based on requested caps (scaling, YUV, etc). And then hw pipe re-assignment if required if required SMP blocks changes. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Archit Taneja <architt@codeaurora.org>
2016-11-27drm/msm/mdp5: rip out mode_changedRob Clark2-21/+4
It wasn't really doing the right thing if, for example, position or height changed. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: don't be so castyRob Clark1-5/+7
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: drop mdp5_plane::nameRob Clark1-15/+11
Just use plane->name now that it is a thing. In a following patch, once we dynamically assign hw pipes to planes, it won't make sense to name planes the way we do, so this also partly reduces churn in following patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: nuke mdp5_plane_complete_flip()Rob Clark3-23/+10
We can do this all from mdp5_plane_complete_commit(), so simplify things a bit and drop mdp5_plane_complete_flip(). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: drop mdp5_crtc::nameRob Clark1-17/+11
Plane's (pipes) can be assigned dynamically with atomic, so it doesn't make much sense to name the pipe after it's primary plane. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm/mdp5: small renameRob Clark1-4/+4
These are really plane-id's, not crtc-id's. Only connection to CRTCs is that they are used as primary-planes. Current name is just legacy from when we only supported RGB/primary planes. Lets pick a better name now. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-27drm/msm: support multiple address spacesRob Clark16-80/+208
We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-26drm/msm/mdp5: clip img size to src sizeRob Clark1-2/+2
If fb dimensions are larger than what can be scanned out, but the src dimensions are not, the hw can still handle this. So clip. Signed-off-by: Rob Clark <robdclark@gmail.com>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.