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2016-03-01drm/exynos: dsi: restore support for drm bridgeMarek Szyprowski1-0/+1
This patch fixes issue introduced by commit cf67cc9a29ac19c98bc4fa0e6d14b0c1f592d322 ("drm/exynos: remove struct exynos_drm_display"), which removed assigning of drm bridge to drm encoder. Lack of it caused that no bridge callbacks were called on encoder enable/disable actions. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: mic: make all functions staticMarek Szyprowski1-5/+5
There is no point exposing all internal functions to global kernel name space, so make all internals functions static. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: mic: convert to component frameworkMarek Szyprowski1-20/+36
MIC is SoC component and important part of kms pipeline on Exynos5433, so convert it to use component framework like other KMS/CRTC drivers. MIC driver is already listed on KMS component driver list in Exynos DRM core, so without this conversion, initialization of Exynos DRM core fails on Exynos 5433 SoC. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: mic: use devm_clk interfaceMarek Szyprowski1-5/+1
Drivers should use devm_clk* interface instead of of_clk* functions. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: fix types for compilation on 64bit architecturesMarek Szyprowski3-6/+9
This patch fixes compilation warnings (on 64bit architectures) and bugs related to casting pointers through 32bit integers. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: ipp: fix incorrect format specifiers in debug messagesMarek Szyprowski4-19/+19
Drivers should use %p for printing pointers instead of hardcoding them as hexadecimal integers. This patch fixes compilation warnings on 64bit architectures. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/exynos: depend on ARCH_EXYNOS for DRM_EXYNOSJoonyoung Shim1-1/+1
Because PLAT_SAMSUNG isn't include exynos SoCs for arm64, but ARCH_EXYNOS can do it. And it also needs to add ARCH_S3C64XX instead of PLAT_SAMSUNG. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2016-03-01drm/i915: Try to fix CRT port clock limitsVille Syrjälä1-4/+12
LPT/WPT-H are limited to max 180 MHz CRT dotclock. Most other platforms have a limit of 350 MHz. Supposedly gen3 and gen4 go up to 400 MHz. VLV is a bit special since the docs are poor. Supposedly the DAC would be good up to 355 MHz, but currently we limit the DPLL to 270 MHz, so we'll have to limit the port clock to the same unless we change the DPLL limits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-7-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Read out VGA dotclock properly on LPTVille Syrjälä4-2/+48
Rather than assume the VGA dotclock is really the FDI based thing, let's read out the real thing via iclkip, and after readout it'll get to compare it with the FDI based number to make sure they're in sync. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-6-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Make the LPT iclkip 20MHz case more genericVille Syrjälä1-21/+19
The reason for spcial casing 20MHz in the iclkip calculations is that it would overflow the 7 bit divisor value. Let's rewrite the special case to check for just that, and bump up auxdiv when needed. This makes the code work for freqeuencies close to but not exactly 20MHz. The real lower limit for auxdiv=0 is actually: 172800000/(0x7f+2)*64)=~20930 kHz, and below that we must resort to auxdiv=1. Actually this is all very theoretical since we limit the dotclock to min 25MHz with CRT on all platforms. 25Mhz is actually the documented limit in Bspec, so it seems we ought to never need to worry about the auxdiv=1 case. But no harm in having it. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-5-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()Ville Syrjälä1-7/+10
Instead of assuming we've correctly set up SPLL to run at 270Mhz for FDI, let's use the port_clock from pipe_config which should be what we want. This would catch problems if someone misconfigures SPLL for whatever reason. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()Ville Syrjälä7-58/+38
Currently we check if the encoder's idea of dotclock agrees with what we calculated based on the FDI parameters. We do this in the encoder .get_config() hooks, which isn't so nice in case the BIOS (or some other outside party) made a mess of the state and we're just trying to take over. So as a prep step to being able sanitize such a bogus state, move the the sanity check to just after we've read out the entire state. If we then need to sanitize a bad state, it should be easier to move the sanity check to occur after sanitation instead of before it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-3-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDWVille Syrjälä1-1/+1
On HSW/BDW ddi_pll_sel is the actual register value. Let's dump it in hex so that people migth actually understand what it says. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455738073-14502-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-03-01drm/i915: Embed rotation_info under intel_framebufferVille Syrjälä2-11/+17
Instead of repopulatin the rotation_info struct for the fb every time we try to use the fb, we can just populate it once when creating the fb, and later we can just copy the pre-populate struct into the gtt_view. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-10-git-send-email-ville.syrjala@linux.intel.com
2016-03-01drm/i915: Move the NULL sg handling out from rotate_pages()Ville Syrjälä1-10/+8
rotate_pages() checks to see if it got called with a NULL sg, and then goes to extract it from sg->sgl. It always gets called with a NULL sg for the first plane, so moving the initial 'sg=st->sgl' assignment out into intel_rotate_fb_obj_pages() seems less special-casey. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-9-git-send-email-ville.syrjala@linux.intel.com
2016-03-01drm/i915: Reorganize intel_rotation_infoVille Syrjälä4-37/+35
Throw out a bunch of unnecessary stuff from struct intel_rotation_info, and pull most of the remaining stuff to live under an array of per-color plane sub-structures. What still remains outside the sub-structure will be reorgranized later as well, but that requires more work elsewhere so leave it be for now. v2: Split the vma size == luma+chroma size fix to prep patch (Daniel) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-8-git-send-email-ville.syrjala@linux.intel.com
2016-03-01drm/i915: Pass drm_frambuffer to intel_compute_page_offset()Ville Syrjälä3-18/+12
intel_compute_page_offsets() gets passed a bunch of the framebuffer metadate sepearately. Just pass the framebuffer itself to make life simpler for the caller, and make it less likely they would make a mistake in the order of the arguments (as most as just unsigned ints and such). We still pass the pitch explicitly since for 90/270 degree rotation the caller has to pass in the right thing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-7-git-send-email-ville.syrjala@linux.intel.com
2016-03-01drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj()Ville Syrjälä3-28/+20
intel_pin_and_fence_fb_obj() only needs the framebuffer, and the desird rotation (to find the right GTT view for it), so no need to pass all kinds of plane stuff. The main motivation is to get rid of the uggy NULL plane_state handling due to fbdev. v2: Add a note why I really want this Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Grumpily-Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-6-git-send-email-ville.syrjala@linux.intel.com
2016-03-01drm/i915: Support for extra alignment for tiled surfacesVille Syrjälä1-5/+45
SKL+ needs >4K alignment for tiled surfaces, so make intel_compute_page_offset() handle it. The way we do it is first we compute the closest tile boundary as before, and then figure out how many tiles we need to go to reach the desired alignment. The difference in the offset is then added into the x/y offsets. v2: Be less confusing wrt. units (pixels vs. bytes) (Daniel) v3: Use u32 for offsets Have intel_adjust_tile_offset() return the new offset (will be useful later) Add an offset_aligned variable (Daniel) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-5-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-03-01drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()Ville Syrjälä3-30/+63
The page aligned surface address calculation needs to know which way things are rotated. The contract now says that the caller must pass the rotate x/y coordinates, as well as the tile_height aligned stride in the tile_height direction. This will make it fairly simple to deal with 90/270 degree rotation on SKL+ where we have to deal with the rotated view into the GTT. v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270 v3: Introduce intel_tile_dims(), and don't mix up different units so much v4: Unconfuse bytes vs. pixels even more Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-03-01drm/i915: s/tile_width/tile_width_bytes/Ville Syrjälä1-16/+16
Make if clear whether we're talking tile widths in bytes or in pixels. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-3-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-03-01drm/i915: Account for the size of the chroma plane for the rotated gtt viewVille Syrjälä1-1/+1
The size of the rotated ggtt mapping ought to include the size of the chroma plane as well. Not a huge deal since we don't expose NV12 (or any pother planar format for that matter) yet. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Fixes: 89e3e1427629 ("drm/i915: Support NV12 in rotated GGTT mapping") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455569699-27905-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2016-03-01drm/i915: Add missing NULL check before calling initial_watermarksImre Deak1-2/+6
Not all platforms set this callback, so NULL check it before calling it. v2: - Call intel_update_watermarks() on HSW+ where the callback is not set. (Matt) CC: Matt Roper <matthew.d.roper@intel.com> Fixes: commit ed4a6a7ca853 ("drm/i915: Add two-stage ILK-style watermark programming (v11)") Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456776633-3401-1-git-send-email-imre.deak@intel.com Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
2016-03-01drm/i915: Execlists small cleanups and micro-optimisationsTvrtko Ursulin2-103/+114
Assorted changes in the areas of code cleanup, reduction of invariant conditional in the interrupt handler and lock contention and MMIO access optimisation. * Remove needless initialization. * Improve cache locality by reorganizing code and/or using branch hints to keep unexpected or error conditions out of line. * Favor busy submit path vs. empty queue. * Less branching in hot-paths. v2: * Avoid mmio reads when possible. (Chris Wilson) * Use natural integer size for csb indices. * Remove useless return value from execlists_update_context. * Extract 32-bit ppgtt PDPs update so it is out of line and shared with two callers. * Grab forcewake across all mmio operations to ease the load on uncore lock and use chepear mmio ops. v3: * Removed some more pointless u8 data types. * Removed unused return from execlists_context_queue. * Commit message updates. v4: * Unclumsify the unqueue if statement. (Chris Wilson) * Hide forcewake from the queuing function. (Chris Wilson) Version 3 now makes the irq handling code path ~20% smaller on 48-bit PPGTT hardware, and a little bit less elsewhere. Hot paths are mostly in-line now and hammering on the uncore spinlock is greatly reduced together with mmio traffic to an extent. Benchmarking with "gem_latency -n 100" (keep submitting batches with 100 nop instruction) shows approximately 4% higher throughput, 2% less CPU time and 22% smaller latencies. This was on a big-core while small-cores could benefit even more. Most likely reason for the improvements are the MMIO optimization and uncore lock traffic reduction. One odd result is with "gem_latency -n 0" (dispatching empty batches) which shows 5% more throughput, 8% less CPU time, 25% better producer and consumer latencies, but 15% higher dispatch latency which is yet unexplained. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1456505912-22286-1-git-send-email-tvrtko.ursulin@linux.intel.com
2016-03-01drm/i915: Handle -EDEADLK in drm_atomic_commit from load-detect.Maarten Lankhorst1-1/+2
CI runs with DEBUG_WW_MUTEX_SLOWPATH, so -EDEADLK occurs a lot more. Handle the case where drm_atomic_commit fails with -EDEADLK correctly. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/56D3FEF1.6070306@linux.intel.com Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2016-03-01drm/imx: only enable vblank IRQs when neededLucas Stach1-0/+9
The vblank IRQ is only needed to trigger page flip work, so we might as well disable it when there is no work to do. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: implement fence syncLucas Stach1-2/+61
If the FB is backed by a GEM object with an dma-buf attached we need to wait for any pending fences to signal before executing the page flip. The implementation is straight forward by deferring the flip to a workqueue in that case. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: keep GEM object referenced as long as scanout is activeLucas Stach1-5/+44
The DRM core only references the currently queued/active framebuffer. So there is a period of time where the flip is not completed, but the GEM object backing the FB is already unreferenced and could be destroyed if userspace closes its handle. Make sure to keep a reference to the GEM object until the flip is actually executed clean things up in a worker running behind the flip execution. Also move the page flip event into the context of this worker, so it gets cleaned up automatically. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: track flip state explicitlyLucas Stach1-5/+10
Start tracking the flip state explicitly, as opposed to inferring it from the presence if a new FB. This is a preparatory step to introduce an new immediate state, where we can wait for a fence to signal. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: don't touch primary fb on pageflipLucas Stach1-1/+0
The core already does the correct replacemet if the driver page flip function returns without an error, so there is no need to do it here. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: ipuv3 plane: Replace dev_info with dev_dbg if a plane's CRTC changesLiu Ying1-1/+1
This patch changes the dev_info() call to dev_dbg() in ipu_plane_update() to print out the information that a plane's CRTC is changed, because this kind of information is only useful for debugging. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01gpu: ipu-v3: ipu-dc: Simplify display controller microcode setupPhilipp Zabel1-26/+25
This cleans up the display controller microcode setup in ipu_dc_init_sync a little bit. The microcode template words for DI0 and DI1 are properly separated to avoid a clash when DI1 is active in interlaced mode at the same time as DI0 in non-interlaced mode. A comment is added to explain the meaning of the sync counter. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/rockchip: remove rockchip_drm_encoder_get_mux_idPhilipp Zabel4-34/+2
It is replaced by drm_of_encoder_active_endpoint_id. Suggested-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Yakir Yang <ykk@rock-chips.com> [for dw_hdmi-rockchip] Acked-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01drm/imx: remove imx_drm_encoder_get_mux_idPhilipp Zabel4-36/+4
It is replaced by drm_of_encoder_active_port_id. Suggested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2016-03-01Merge tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie43-1072/+1537
- lots and lots of fbc work from Paulo - max pixel clock checks from Mika Kahola - prep work for nv12 offset handling from Ville - piles of small fixes and refactorings all around * tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel: (113 commits) drm/i915: Update DRIVER_DATE to 20160214 drm/i915: edp resume/On time optimization. agp/intel-gtt: Only register fake agp driver for gen1 drm/i915: TV pixel clock check drm/i915: CRT pixel clock check drm/i915: SDVO pixel clock check drm/i915: DisplayPort-MST pixel clock check drm/i915: HDMI pixel clock check drm/i915: DisplayPort pixel clock check drm/i915: check that rpm ref is held when accessing ringbuf in stolen mem drm/i915: fix error path in intel_setup_gmbus() drm/i915: Stop depending upon CONFIG_AGP_INTEL agp/intel-gtt: Don't leak the scratch page drm/i915: Capture PCI revision and subsytem details in error state drm/i915: fix context/engine cleanup order drm/i915: Handle PipeC fused off on IVB/HSW/BDW drm/i915/skl: Fix typo in DPLL_CFGCR1 definition drm/i915: Skip DDI PLL selection for DSI drm/i915/skl: Explicitly check for eDP in skl_ddi_pll_select() drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select() ...
2016-03-01drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)Chris Wilson1-14/+12
commit 09731280028ce03e6a27e1998137f1775a2839f3 Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 17 14:17:42 2016 +0200 drm/i915: Add helper to get a display power ref if it was already enabled left the rpm wakelock assertions unbalanced if CONFIG_PM was disabled as intel_runtime_pm_get_if_in_use() would return true without incrementing the local bookkeeping required for the assertions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> CC: Mika Kuoppala <mika.kuoppala@intel.com> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-02-29drm/i915: remove dead codeEric Engestrom1-12/+0
79e539453b34e35f39299a899d263b0a1f1670bd ("DRM: i915: add mode setting support") added those variables but never used them. Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1456763047-28828-2-git-send-email-eric.engestrom@imgtec.com
2016-02-29drm/i915: remove left over dead codeEric Engestrom1-14/+0
ae80152ddad252f33893b92dd69f00cc53c5949f ("drm/i915: Rewrite VLV/CHV watermark code") removed everything that would have used those vars. Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1456763047-28828-1-git-send-email-eric.engestrom@imgtec.com
2016-02-29drm/crtc: Use drm_mode_object_put() in __drm_framebuffer_unregister()Liu Ying1-3/+1
The function __drm_framebuffer_unregister() has boilerplate code to drop idr reference. Let's replace it with drm_mode_object_put() to simplify the code. Signed-off-by: Liu Ying <gnuiyl@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1456716070-2602-1-git-send-email-gnuiyl@gmail.com
2016-02-29drm/amdgpu: trace the pd_addr in vm_grab_id as wellChristian König2-10/+14
Makes matching it to the flushes much easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-29drm/amdgpu: fix VM faults caused by vm_grab_id() v4Christian König9-80/+91
The owner must be per ring as long as we don't support sharing VMIDs per process. Also move the assigned VMID and page directory address into the IB structure. v3: assign the VMID to all IBs, not just the first one. v4: use correct pointer for owner Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-29drm/i915: Add two-stage ILK-style watermark programming (v11)Matt Roper6-58/+244
In addition to calculating final watermarks, let's also pre-calculate a set of intermediate watermark values at atomic check time. These intermediate watermarks are a combination of the watermarks for the old state and the new state; they should satisfy the requirements of both states which means they can be programmed immediately when we commit the atomic state (without waiting for a vblank). Once the vblank does happen, we can then re-program watermarks to the more optimal final value. v2: Significant rebasing/rewriting. v3: - Move 'need_postvbl_update' flag to CRTC state (Daniel) - Don't forget to check intermediate watermark values for validity (Maarten) - Don't due async watermark optimization; just do it at the end of the atomic transaction, after waiting for vblanks. We do want it to be async eventually, but adding that now will cause more trouble for Maarten's in-progress work. (Maarten) - Don't allocate space in crtc_state for intermediate watermarks on platforms that don't need it (gen9+). - Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit now that ilk_update_wm is gone. v4: - Add a wm_mutex to cover updates to intel_crtc->active and the need_postvbl_update flag. Since we don't have async yet it isn't terribly important yet, but might as well add it now. - Change interface to program watermarks. Platforms will now expose .initial_watermarks() and .optimize_watermarks() functions to do watermark programming. These should lock wm_mutex, copy the appropriate state values into intel_crtc->active, and then call the internal program watermarks function. v5: - Skip intermediate watermark calculation/check during initial hardware readout since we don't trust the existing HW values (and don't have valid values of our own yet). - Don't try to call .optimize_watermarks() on platforms that don't have atomic watermarks yet. (Maarten) v6: - Rebase v7: - Further rebase v8: - A few minor indentation and line length fixes v9: - Yet another rebase since Maarten's patches reworked a bunch of the code (wm_pre, wm_post, etc.) that this was previously based on. v10: - Move wm_mutex to dev_priv to protect against racing commits against disjoint CRTC sets. (Maarten) - Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten) v11: - Now that we've moved to atomic watermark updates, make sure we call the proper function to program watermarks in {ironlake,haswell}_crtc_enable(); the failure to do so on the previous patch iteration led to us not actually programming the watermarks before turning on the CRTC, which was the cause of the underruns that the CI system was seeing. - Fix inverted logic for determining when to optimize watermarks. We were needlessly optimizing when the intermediate/optimal values were the same (harmless), but not actually optimizing when they differed (also harmless, but wasteful from a power/bandwidth perspective). Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-29drm/msm/hdmi: HDMI 8996 PHY/PLL supportArchit Taneja4-0/+780
Add support for the HDMI PHY/PLL found in MSM8996/APQ8096. Unlike the previous PHYs supported in the driver, this doesn't need the powerup/powerdown ops. The PLL prepare/unprepare clock ops enable/disable the phy itself. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Update generated headers for HDMI 8996 PHYArchit Taneja1-2/+498
Adds HDMI 8996 PHY offsets. The offsets are divided into 3 parts: - Core HDMI PHY registers - HDMI PLL registers (part of QSERDES block) - HDMI TX lane registers (part of QSERDES block) Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Update generated headers to split PHY/PLL offsetsArchit Taneja1-83/+74
- Create separate domains for 8960 PHY and PLL - Create separate domains for 8x60 PHY Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Convert PHY files according to new designArchit Taneja6-711/+99
Remove the old PHY ops managed by hdmi_platform_config and use them as ops provided by the HDMI PHY driver. Remove the old HDMI 8960 PLL code that used the top level HDMI TX mmio base. NOTE: With this commit, HDMI functionality will break until the HDMI PHY/PLL register offsets in hdmi.xml.h aren't updated to be used as separate domains. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Make HDMI core get its PHYArchit Taneja2-0/+42
Make HDMI core get its PHY by parsing the "phys" phandle. The core will use this PHY reference to enable/disable PHY. The driver defers probe until PHY isn't available. The DT bindings used here is the same as the one used for PHYs using the common PHY framework bindings. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Manage HDMI PLL through PHY driverArchit Taneja4-0/+506
Add a helper to initialize PLL in the PHY driver. HDMI PLLs are going to have their own mmio base different from that of PHY. For the clock code in hdmi_phy_8960.c, some changes were needed for it to work with the updated register offsets. Create a copy of the updated clock code in hdmi_pll_8960.c, instead of rewriting it in hdmi_phy_8960.c itself. This removes the need to place CONFIG_COMMON_CLOCK checks all around, makes the code more legible, and also removes some old checkpatch warnings with the original code. The older hdmi pll clock ops in hdmi_phy_8960.c will be removed later. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Create a separate HDMI PHY driverArchit Taneja7-4/+281
Create a PHY device that represents the TX PHY and PLL parts of the HDMI block. This makes management of PHY specific resources (regulators and clocks) much easier, and makes the PHY and PLL usable independently. It also simplifies the core HDMI driver, which currently assigns phy ops among many other things. The PHY driver implementation done here is very similar to the PHY driver we already have for DSI. Keep the old hdmi_phy_funcs ops for now. The driver will use these until the HDMI PHY/PLL register offsets aren't considered as separate domains (i.e. their offsets start from 0). The driver doesn't use the common PHY framework for now. This is because it's hard to map our ops with the ops provided by the framework. The bindings used for this is the generic phy bindings. So, this can be adapted to the PHY framework in the future, if possible. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29drm/msm/hdmi: Fix connector detect when there is no HPD gpioArchit Taneja1-0/+9
Some platforms may not have a HPD gpio line to detect Hot Plug signal from the connector. They need to rely only on reading REG_HDMI_HPD_INT_STATUS for HPD. Modify hdmi_connector_detect logic such that it checks for HPD only using the status register if there is no HPD gpio. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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