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2016-02-23drm: rcar-du: lvds: Add R-Car Gen3 supportKoji Matsuoka4-48/+123
The LVDS encoder differs slightly in Gen3 SoCs in its PLL configuration. Add support for the Gen3 LVDS PLL parameters and startup procedure. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Rename PLLEN bit to PLLONLaurent Pinchart2-2/+2
The bit is named PLLON in the datasheet, rename it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Fix PLL frequency-related configurationLaurent Pinchart1-3/+3
The frequency checks don't match the datasheet, fix them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: lvds: Avoid duplication of clock clamp codeLaurent Pinchart4-10/+18
Replace the duplicate code by a single central function. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Add R8A7795 device supportLaurent Pinchart8-39/+140
Document the R8A7795-specific DT bindings and support them in the driver. The HDMI and LVDS outputs are currently not supported. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Output the DISP signal on the ODDF pinLaurent Pinchart2-1/+13
The ODDF signal, output by default on the ODDF pin, isn't used on any board supported in the kernel. As the Gen3 Salvator-X board uses the ODDF pin as a DISP signal, hardcode that configuration in the driver. Use of the ODDF signal will be implemented later through proper DT-based configuration of the DU pins. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Output the DISP signal on the DISP pinLaurent Pinchart1-1/+1
The DE signal is currently configured to be identical to the DISP signal and is used for the same purpose. To make it clearer that the DISP pin outputs the DISP signal, select it explicitly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Support up to 4 CRTCsKoji Matsuoka3-2/+3
The Gen3 R8A7795 DU has 4 CRTCs, support them all. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Drop LVDS double dependency on OFLaurent Pinchart1-1/+0
LVDS support depends on DRM_RCAR_DU which already depends on OF. Drop the explicit dependency. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Enable compilation on ARM64Koji Matsuoka1-1/+2
The R8A7795 SoC is ARM64-based and include a DU. Enable driver compilation on ARM64. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Fix compile warning on 64-bit platformsKoji Matsuoka1-4/+4
Use %tu instead of %u to print difference between pointers. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-23drm: rcar-du: Expose the VSP1 compositor through KMS planesLaurent Pinchart10-16/+539
On R-Car Gen3 SoCs the DU lost its ability to access memory directly and needs to work in conjunction with the VSP to do so. This commit handles the VSP internally to hide it from the user. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-22drm/i915: Add for_each_pipe_masked()Ville Syrjälä2-18/+12
for_each_pipe_masked() can be used to iterate over the pipes included in the user provided pipe mask. Removes a few lines of duplicated code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455907651-16397-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-02-22drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+Ville Syrjälä3-0/+37
Starting from BDW the DE_PIPE interrupts for pipe B and C belong to the relevant display power well. So we should make sure we've finished processing them before turning off the power well. The pipe interrupts shouldn't really happen at this point anymore since we've already shut down the planes/pipes/whatnot, but being a bit paranoid shouldn't hurt. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455907651-16397-1-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-02-22drm/i915: synchronize_irq() before turning off disp2d power well on VLV/CHVVille Syrjälä1-0/+3
After we've told the irq code we don't want to handle display irqs anymore, we must make sure any display irq handling already kicked off has finished before we actually turn off the power well. I wouldn't expect PIPESTAT based interrupts to occur anymore since vblanks/page flips/gmbus/etc should all be quiescent at this point. But at least hotplug interrupts could still occur. Hotplug interrupts may also kick off the workqueue based hotplug processing, but that code should take the required power domain references itself, so there shouldn't be any need to synchronize with the hotplug processing from the power well code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455900112-15387-1-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-02-22drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is downVille Syrjälä1-0/+6
PIPESTAT registers live in the display power well on VLV/CHV, so we shouldn't access them when things are powered down. Let's check whether the display interrupts are on or off before accessing the PIPESTAT registers. Another option would be to read the PIPESTAT registers only when the IIR register indicates that there's a pending pipe event. But that would mean we might miss even more underrun reports than we do now, because the underrun status bit lives in PIPESTAT but doesn't actually generate an interrupt. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93738 Cc: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455825266-24686-1-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2016-02-22drm/i915/gen9: Verify and enforce dc6 state writesMika Kuoppala1-2/+39
It has been observed that sometimes disabling the dc6 fails and dc6 state pops back up, brief moment after disabling. This has to be dmc save/restore timing issue or other bug in the way dc states are handled. Try to work around this issue as we don't have firmware fix yet available. Verify that the value we wrote for the dmc sticks, and also enforce it by rewriting it, if it didn't. v2: Zero rereads on rewrite for extra paranoia (Imre) Testcase: kms_flip/basic-flip-vs-dpms References: https://bugs.freedesktop.org/show_bug.cgi?id=93768 Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455811089-27884-1-git-send-email-mika.kuoppala@intel.com (cherry picked from commit 779cb5d3ddd72950ec726f86e38f7575c7fbdd4c) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/gen9: Check for DC state mismatchPatrik Jakobsson3-0/+11
The DMC can incorrectly run off and allow DC states on it's own. We don't know the root-cause for this yet but this patch makes it more visible. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-2-git-send-email-mika.kuoppala@intel.com (cherry picked from commit 832dba889e27487c3087149f1039acc3feb89003) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/radeon/pm: adjust display configuration after powerstateAlex Deucher1-2/+3
set_power_state defaults to no displays, so we need to update the display configuration after setting up the powerstate on the first call. In most cases this is not an issue since ends up getting called multiple times at any given modeset and the proper order is achieved in the display changed handling at the top of the function. Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-02-22drm/amdgpu/pm: adjust display configuration after powerstateAlex Deucher1-2/+3
set_power_state defaults to no displays, so we need to update the display configuration after setting up the powerstate on the first call. In most cases this is not an issue since ends up getting called multiple times at any given modeset and the proper order is achieved in the display changed handling at the top of the function. Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2016-02-22drm/amdgpu/pm: add some checks for PXAlex Deucher1-1/+20
I.e., doesn't make sense to change power states or check the temperature when the asic is powered off. Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-22drm/amdgpu: fix locking in force performance levelAlex Deucher1-2/+1
Looks like a copy paste typo when we added powerplay support. Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-22drm/amdgpu/gfx8: fix priv reg interrupt enableAlex Deucher1-1/+1
Looks like a copy/paste typo. Reviewed-by: Christian König <christian.koenig@amd.com> Noticed-by: David Panariti <David.Panariti@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-22drm/i915/skl: Ensure HW is powered during DDB HW state readoutImre Deak1-1/+6
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93441 CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455719489-3008-1-git-send-email-imre.deak@intel.com (cherry picked from commit 4d800030238878c1a98d1d3a37a3d673eea661ce) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/lvds: Ensure the HW is powered during HW state readoutImre Deak1-3/+11
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-13-git-send-email-imre.deak@intel.com (cherry picked from commit ecb2448218acf23c401434c26be256147833b221) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/hdmi: Ensure the HW is powered during HW state readoutImre Deak1-3/+11
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-12-git-send-email-imre.deak@intel.com (cherry picked from commit 5b0921748c0b1d0362bbfa802dc25a5c23de7e76) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/dsi: Ensure the HW is powered during HW state readoutImre Deak1-3/+10
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-11-git-send-email-imre.deak@intel.com (cherry picked from commit 3f3f42b887fbffc3353e44ef9f32456c19ae4280) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/dp: Ensure the HW is powered during HW state readoutImre Deak1-4/+14
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-10-git-send-email-imre.deak@intel.com (cherry picked from commit 6fa9a5ecf7a54450b255229ac1fc6df276cf0653) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915: Ensure the HW is powered when accessing the CRC HW blockImre Deak1-7/+21
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. While at it also add the missing reference around the HW access in i915_interrupt_info(). v2: - update the commit message mentioning that this also fixes the HW access in the interrupt info debugfs entry (Daniel) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-9-git-send-email-imre.deak@intel.com (cherry picked from commit e129649b7a3e1d50d196e159492496777769437e) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/ddi: Ensure the HW is powered during HW state readoutImre Deak1-33/+79
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-8-git-send-email-imre.deak@intel.com (cherry picked from commit e27daab49718e3232318d8b539cb302521b4b724) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/crt: Ensure the HW is powered during HW state readoutImre Deak1-3/+10
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93439 CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-7-git-send-email-imre.deak@intel.com (cherry picked from commit 1c8fdda1ea947ae8cf994969a1c285acc7089cb9) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915: Ensure the HW is powered during HW access in assert_pipeImre Deak1-4/+7
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-6-git-send-email-imre.deak@intel.com (cherry picked from commit 4feed0ebfa45879bc422c9a0bfa3cffec82ea60a) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915: Ensure the HW is powered when disabling VGAImre Deak1-1/+3
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-5-git-send-email-imre.deak@intel.com (cherry picked from commit 6392f8478e6f119467b1ad06e30e1f078e62efc1) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/ibx: Ensure the HW is powered during PLL HW readoutImre Deak1-1/+3
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-4-git-send-email-imre.deak@intel.com (cherry picked from commit 12fda3876d08519bdf6f0acc70dd35754b422ed5) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915: Ensure the HW is powered during display pipe HW readoutImre Deak1-19/+48
The assumption when adding the intel_display_power_is_enabled() checks was that if it returns success the power can't be turned off afterwards during the HW access, which is guaranteed by modeset locks. This isn't always true, so make sure we hold a dedicated reference for the time of the access. Signed-off-by: Imre Deak <imre.deak@intel.com> Revieved-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455296121-4742-3-git-send-email-imre.deak@intel.com (cherry picked from commit 1729050eb4bbc192e54069e82069f2811313c1dd) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915: Add helper to get a display power ref if it was already enabledImre Deak2-9/+94
We have many places in the code where we check if a given display power domain is enabled and if so access registers backed by this power domain. We assumed that some modeset lock will prevent the power reference from vanishing in the middle of the HW access, but this assumption doesn't always hold. In such cases we get either the wakeref not held, or an unclaimed register access error message. To fix this in a future-proof way that's independent of other locks wrap any such access with a get_ref_if_enabled()/put_ref() pair. Kudos to Ville and Joonas for the ideas of this new interface. v2: - init the power_domains ptr when declaring it everywhere (Joonas) v3: - don't report the device to be powered if runtime PM is disabled CC: Mika Kuoppala <mika.kuoppala@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> CC: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455711462-7442-1-git-send-email-imre.deak@intel.com (cherry picked from commit 09731280028ce03e6a27e1998137f1775a2839f3) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-02-22drm/i915/gen9: Write dc state debugmask bits only onceMika Kuoppala3-9/+8
DMC debugmask bits should stick so no need to write them everytime dc state is changed. v2: Write after firmware has been successfully loaded (Ville) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-5-git-send-email-mika.kuoppala@intel.com
2016-02-22drm/i915/gen9: Extend dmc debug mask to include coresMika Kuoppala2-6/+11
Cores need to be included into the debug mask. We don't exactly know what it does but the spec says it must be enabled. So obey. v2: Cores should be only set for BXT (Imre, Art) Cc: Imre Deak <imre.deak@intel.com> Cc: Runyan, Arthur J <arthur.j.runyan@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455877564-5128-1-git-send-email-mika.kuoppala@intel.com
2016-02-22drm/i915/gen9: Verify and enforce dc6 state writesMika Kuoppala1-2/+39
It has been observed that sometimes disabling the dc6 fails and dc6 state pops back up, brief moment after disabling. This has to be dmc save/restore timing issue or other bug in the way dc states are handled. Try to work around this issue as we don't have firmware fix yet available. Verify that the value we wrote for the dmc sticks, and also enforce it by rewriting it, if it didn't. v2: Zero rereads on rewrite for extra paranoia (Imre) Testcase: kms_flip/basic-flip-vs-dpms References: https://bugs.freedesktop.org/show_bug.cgi?id=93768 Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455811089-27884-1-git-send-email-mika.kuoppala@intel.com
2016-02-22drm/i915/gen9: Check for DC state mismatchPatrik Jakobsson3-0/+11
The DMC can incorrectly run off and allow DC states on it's own. We don't know the root-cause for this yet but this patch makes it more visible. Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1455808874-22089-2-git-send-email-mika.kuoppala@intel.com
2016-02-20drm: rcar-du: Move plane allocator to rcar_du_plane.cLaurent Pinchart3-275/+290
The plane allocator is specific to DU planes and won't be used for VSP-based planes, move it with the rest of the DU planes code where it belongs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Restart the DU group when a plane source changesLaurent Pinchart4-2/+28
Plane sources are configured by the VSPS bit in the PnDDCR4 register. Although the datasheet states that the bit is updated during vertical blanking, it seems that updates only occur when the DU group is held in reset through the DSYSR.DRES bit. Restart the group if the source changes. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Add VSP1 compositor supportLaurent Pinchart6-49/+82
Configure the plane source at plane setup time to source frames from memory or from the VSP1. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Add VSP1 support to the planes allocatorLaurent Pinchart3-6/+44
The R8A7790 DU can source frames directly from the VSP1 devices VSPD0 and VSPD1. VSPD0 feeds DU0/1 plane 0, and VSPD1 feeds either DU2 plane 0 or DU0/1 plane 1. Allocate the correct fixed plane when sourcing frames from VSPD0 or VSPD1, and allocate planes in reverse index order otherwise to ensure maximum availability of planes 0 and 1. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Refactor plane setupLaurent Pinchart1-18/+21
Rename plane setup functions using more explicit names, and use local variables to store intermediate values to increase readability. This also prepares for VSP compositor support. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Compute plane DDCR4 register value directlyLaurent Pinchart1-10/+3
There's no need for a read-modify-write pattern, all register bits can be set explicitly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Don't update planes on disabled CRTCsLaurent Pinchart1-1/+1
A disabled CRTC can't display planes, the driver shouldn't try to configure it when updating planes. The DRM core will store the plane state for us, and the plane will be configured appropriately the next time the CRTC is enabled. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Remove local CRTC enabled stateLaurent Pinchart2-13/+1
The atomic framework guarantees that the CRTC enable and disable functions will only be called when needed, there's no need to duplicate the CRTC state check. By replacing the local CRTC enabled state check at resume time with the CRTC active state we can remove the local CRTC enabled state altogether. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2016-02-20drm: rcar-du: Perform initialization/cleanup at probe/remove timeLaurent Pinchart4-114/+106
The drm driver .load() operation is prone to race conditions as it initializes the driver after registering the device nodes. Its usage is deprecated, inline it in the probe function and call drm_dev_alloc() and drm_dev_register() explicitly. For consistency inline the .unload() handler in the remove function as well. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2016-02-19drm/amdgpu: Don't hang in amdgpu_flip_work_func on disabled crtc.Mario Kleiner1-3/+15
This fixes a regression introduced in Linux 4.4. This is a port of the same fix for radeon-kms in the patch "drm/radeon: Don't hang in radeon_flip_work_func on disabled crtc. (v2)" Limit the amount of time amdgpu_flip_work_func can delay programming a page flip, by both limiting the maximum amount of time per wait cycle and the maximum number of wait cycles. Continue the flip if the limit is exceeded, even if that may result in a visual or timing glitch. This is to prevent a hang of page flips, as reported in fdo bug #93746: Disconnecting a DisplayPort display in parallel to a kms pageflip getting queued can cause the following hang of page flips and thereby an unusable desktop: 1. kms pageflip ioctl() queues pageflip -> queues execution of amdgpu_flip_work_func. 2. Hotunplug of display causes the driver to DPMS OFF the unplugged display. Display engine shuts down, scanout no longer moves, but stays at its resting position at start line of vblank. 3. amdgpu_flip_work_func executes while crtc is off, and due to the non-moving scanout position, the new flip delay code introduced into Linux 4.4 by commit 8e36f9d33c13 ("drm/amdgpu: Fixup hw vblank counter/ts..") enters an infinite wait loop. 4. After reconnecting the display, the pageflip continues to hang in 3. and the display doesn't update its view of the desktop. This patch fixes the Linux 4.4 regression from fdo bug #93746 <https://bugs.freedesktop.org/show_bug.cgi?id=93746> Reported-by: Bernd Steinhauser <linux@bernd-steinhauser.de> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: <stable@vger.kernel.org> # 4.4+ Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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