aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2015-12-21drm/amdgpu: enable powerplay module by default for fiji.Rex Zhu1-0/+3
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: enable powerplay module by default for tonga.Rex Zhu1-0/+8
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu/powerplay: program display gap for tonga.Rex Zhu1-0/+91
Implement displaygap programming for tonga. This is required for properly mclk switching. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu/powerplay: implement pem_task for display_configuration_changeRex Zhu4-6/+15
Add support for display configuration changes to the event manager. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu/poweprlay: export program display gap function to eventmgrRex Zhu2-0/+29
This allows the eventmgr to properly update the displaygap on certain power events. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu/powerplay: add function point in hwmgr_funcs for program display gapRex Zhu1-1/+3
Displaygap support is required for proper mclk switching. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/amdgpu: enable powerplay and smc firmware loading for Fiji.Eric Huang3-1/+7
Switch over to handling in the powerplay module. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amdgpu: add amdgpu.powerplay module optionJammy Zhou1-0/+5
This option can be used to enable the new powerplay implementation, and it is disabled by default. Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add Fiji DPM support.Eric Huang7-1/+5815
This enabled DPM support for Fiji. DPM is dynamic clock and voltage scaling. v2: rename fiji_hwmgr_early_init to fiji_hwmgr_init v3: (agd) fold in endian fix, additional function addition Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: add Fiji SMU support.Eric Huang4-1/+1117
Add support for the SMU manager for Fiji. This handles the firmware loading for other IP blocks (GFX, SDMA, etc.). Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: update atomctrl for fijiEric Huang3-9/+496
Add some new functions to support Fiji. Split out from the previous patch. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: add/update headers for Fiji SMU and DPMEric Huang7-182/+12926
New headers for Fiji. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: add Tonga dpm support (v3)yanyang120-12/+9284
This implements DPM for tonga. DPM handles dynamic clock and voltage scaling. v2: merge all the patches related with tonga dpm v3: merge dpm force level fix, cgs display fix, spelling fix Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: Add Tonga SMU supportJammy Zhou5-2/+921
The SMU manager handles firmware loading for other IP blocks (GFX, SDMA, etc.). This implements it for Tonga. v3: delete peci sub-module v2: use cgs interface directly Signed-off-by: Young Yang <Young.Yang@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add header file for tonga smu and dpmyanyang14-198/+1844
These headers provide the SMU interface used by the driver. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: Move smu7*.h from amdgpu to powerplay.yanyang13-0/+0
Move smu7.h, smu7_discrete.h and smu7_fusion.h from amdgpu to powerplay. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.hyanyang11-0/+1
Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by new powerplay code for tonga and fiji. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: implement functions of amd_powerplay_funcRex Zhu1-8/+183
This is the common interface for interacting with the powerplay module. v2: squash in fixes Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add event manager sub-componentRex Zhu20-1/+2423
The event manager handles power related driver events. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add CG and PG support for carrizoRex Zhu10-12/+1058
This adds clock and powergating support for CZ. v2: squash in fixes Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add Carrizo dpm supportJammy Zhou4-3/+1212
This patch enables basic DPM support for Carrizo. DPM handles dynamic clock and voltage scaling. v3: delete peci sub-module v2: use cgs interface directly correct define SMU_EnabledFeatureScoreboard_SclkDpmOn Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add Carrizo smu supportJammy Zhou8-2/+963
This implements the SMU firmware manager interface for CZ. Some header files are moved from amdgpu folder to powerplay as well. v3: delete peci sub-module. v2: use cgs interface directly add load_mec_firmware function Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add hardware manager sub-componentJammy Zhou16-6/+3439
The hwmgr handles all hardware related calls, including clock/power gating control, DPM, read and parse PPTable, etc. v5: squash in fixes v4: implement acpi's atcs function use cgs interface v3: fix code style error and add big-endian mode support. v2: use cgs interface directly in hwmgr sub-module Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add SMU manager sub-componentJammy Zhou6-0/+560
The SMUMGR is one sub-component of powerplay for SMU firmware support. The SMU handles firmware loading for other IP blocks (GFX, SDMA, etc.) on VI parts. The adds the core powerplay infrastructure to handle that. v3: direct use printk in powerplay module. v2: direct use cgs_read/write_register functions in smu-modules Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: export amd_powerplay_func to amdgpu and other ip blockRex Zhu2-81/+180
Update amdgpu to deal with the new powerplay module properly. v2: squash in fixes v3: squash in Rex's power state reporting fix Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: disable legacy path of firmware check if powerplay is enabledRex Zhu2-46/+52
Powerplay will use a different interface once it's integrated. These legacy pathes will be removed once powerplay is enabled by default. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add basic powerplay frameworkAlex Deucher12-9/+718
amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: add new cgs interface to get display info (v2)Rex Zhu2-0/+60
Add new CGS interfaces to query display info across modules. This is nedded by the powerplay module for synchronizing with the display module. v2: (agd): fold in refresh rate fix, rebase Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: implement cgs interface to query system infoRex Zhu2-0/+46
Add a query to get the bus number and function of the device. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-21drm/amdgpu: implement new cgs interface for acpi functionRex Zhu2-3/+262
Add a new driver internal interface for accessing ACPI methods. These will be used by various new components including powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: mv amdgpu_acpi.h to amd/include/amd_acpi.hRex Zhu3-4/+4
This will be shared with the new powerplay module. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: mv some definition from amdgpu_acpi.c to amdgpu_acpi.hRex Zhu2-60/+53
These will be shared with the new powerplay module. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: share struct amdgpu_pm_state_type with powerplay moduleRex Zhu3-30/+27
rename amdgpu_pm_state_type to amd_pm_state_type Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/radeon: clean up fujitsu quirksAlex Deucher1-9/+3
Combine the two quirks. bug: https://bugzilla.kernel.org/show_bug.cgi?id=109481 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/amdgpu: Fix off-by-one errors in amdgpu_vm_bo_mapFelix Kuehling1-5/+5
eaddr is sometimes treated as the last address inside the address range, and sometimes as the first address outside the range. This was resulting in errors when a test filled up the entire address space. Make it consistent to always be the last address within the range. Signed-off-by: Felix.Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/radeon: Fix off-by-one errors in radeon_vm_bo_set_addrFelix Kuehling1-6/+6
eoffset is sometimes treated as the last address inside the address range, and sometimes as the first address outside the range. This was resulting in errors when a test filled up the entire address space. Make it consistent to always be the last address within the range. Also fixed related errors when checking the VA limit and in radeon_vm_fence_pts. Signed-off-by: Felix.Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/radeon: fix dp link rate selection (v2)Alex Deucher3-76/+48
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: fix dp link rate selection (v2)Alex Deucher1-59/+35
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/i915: Remove obsolete code from intelfb_alloc()Lukas Wunner1-3/+1
Clean up after 0c82312f3f15 ("drm/i915: Pin the ifbdev for the info->system_base GGTT mmapping"): At each of the remaining "goto out" in intelfb_alloc(), fb can only be either an ERR_PTR or NULL, so the call to drm_framebuffer_unreference() is now obsolete. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: http://patchwork.freedesktop.org/patch/msgid/56756c41.c306c20a.d0602.1830SMTPIN_ADDED_MISSING@mx.google.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Workaround CHV pipe C cursor failVille Syrjälä1-0/+17
Turns out CHV pipe C was glued on somewhat poorly, and there's something wrong with the cursor. If the cursor straddles the left screen edge, and is then moved away from the edge or disabled, the pipe will often underrun. If enough underruns are triggered quickly enough the pipe will fall over and die (it just scans out a solid color and reports a constant underrun). We need to turn the disp2d power well off and on again to recover the pipe. None of that is very nice for the user, so let's just refuse to place the cursor in the compromised position. The ddx appears to fall back to swcursor when the ioctl returns an error, so theoretically there's no loss of functionality for the user (discounting swcursor bugs). I suppose most cursors images actually have the hotspot not exactly at 0,0 so under typical conditions the fallback will in fact kick in as soon as the cursor touches the left edge of the screen. Any atomic compositor should anyway be prepared to fall back to GPU composition when things don't work out, so there should be no problem with those. Other things that I tried to solve this include flipping all display related clock gating knobs I could find, increasing the minimum gtt alignment all the way up to 512k. I also tried to see if there are more specific screen coordinates that hit the bug, but the findings were somewhat inconclusive. Sometimes the failures happen almost across the whole left edge, sometimes more at the very top and around the bottom half. I wasn't able to find any real pattern to these variations, so it seems our only choice is to just refuse to straddle the left screen edge at all. Cc: stable@vger.kernel.org Cc: Jason Plum <max@warheads.net> Testcase: igt/kms_chv_cursor_fail Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92826 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1450459479-16286-1-git-send-email-ville.syrjala@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Reorder i915_params struct.Joonas Lahtinen1-4/+4
Move all the bool variables to the end as per the comment. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1450436898-20408-3-git-send-email-joonas.lahtinen@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Decouple struct i915_params i915 into i915_params.hJoonas Lahtinen3-38/+71
Otherwise usage in the i915 debug macros yields problems due to i915_drv.h <-> i915_trace.h <-> intel_drv.h include loops. v2: - Document not-so-obvious need for linux/cache.h (Chris) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1450436898-20408-2-git-send-email-joonas.lahtinen@linux.intel.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Limit VF cache invalidate workaround usage to gen9Ben Widawsky1-8/+8
It is unclear if this is even required on BXT. v2: Make sure to set the default value to false. Uncertain how my compiler doesn't complain with v1. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1450374597-7021-1-git-send-email-benjamin.widawsky@intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Correct max delay for HDMI hotplug live status checkingGary Wang1-3/+4
The total delay of HDMI hotplug detecting with 30ms have already been split into a resolution of 3 retries of 10ms each, for the worst cases. But it still suffered from only waiting 10ms at most in intel_hdmi_detect(). This patch corrects it by reading hotplug status with 4 times at most for 30ms delay. v2: - straight up to loop execution for more clear in code readability - mdelay will replace with msleep by Daniel's new patch drm/i915: mdelay(10) considered harmful - suggest to re-evaluate try times for being compatible to old HDMI monitor Reviewed-by: Cooper Chiou <cooper.chiou@intel.com> Tested-by: Gary Wang <gary.c.wang@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Gavin Hindman <gavin.hindman@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Gary Wang <gary.c.wang@intel.com> [danvet: fixup conflict with s/mdelay/msleep/ patch.] Cc: drm-intel-fixes@lists.freedesktop.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/i915: Move Braswell stop_machine GGTT insertion workaroundChris Wilson1-22/+28
There was a silent conflict between commit 0a878716265e9af9f697264dc2e858fcc060d833 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 14:23:01 2015 +0200 drm/i915: restore ggtt double-bind avoidance and commit 5bab6f60cb4d1417ad7c599166bcfec87529c1a2 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Oct 23 18:43:32 2015 +0100 drm/i915: Serialise updates to GGTT with access through GGTT on Braswell thankfully caught by the extra WARN safegaurd in 0a878716. Since we now override the GGTT insert_pages callback when installing the aliasing ppgtt, we assert that the callback is the original ggtt routine. However, on Braswell we now use a different insertion routine to serialise access through the GGTT with updating the PTE and hence the conflict. To avoid the conflict, move the custom insertion routine for Braswell down a level. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447859979-20107-1-git-send-email-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: drm-intel-fixes@lists.freedesktop.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-21drm/fb-helper: Use proper plane mask for fb cleanupMatt Roper1-1/+1
pan_display_atomic() calls drm_atomic_clean_old_fb() to sanitize the legacy FB fields (plane->fb and plane->old_fb). However it was building the plane mask to pass to this function incorrectly (the bitwise OR was using plane indices rather than plane masks). The end result was that sometimes the legacy pointers would become out of sync with the atomic pointers. If another operation tried to re-set the same FB onto the plane, we might end up with the pointers back in sync, but improper reference counts, which would eventually lead to system crashes when we accessed a pointer to a prematurely-destroyed FB. The cause here was a very subtle bug introduced in commit: commit 07d3bad6c1210bd21e85d084807ef4ee4ac43a78 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Wed Nov 11 11:29:11 2015 +0100 drm/core: Fix old_fb handling in pan_display_atomic. I found the crashes were most easily reproduced (on i915 at least) by starting X and then VT switching to a VT that wasn't running a console instance...the sequence of vt/fbcon entries that happen in that case trigger a reference count mismatch and crash the system. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93313 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-12-20drm/exynos: atomic check only enabled crtc statesAndrzej Hajda1-0/+3
Since atomic check is called also for disabled crtcs it should skip mode checking as it can be uninitialized. The patch fixes it. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-12-19Merge branch 'linux-4.4' of git://github.com/skeggsb/linux into drm-fixesDave Airlie1-0/+1
single nouveau fix. * 'linux-4.4' of git://github.com/skeggsb/linux: drm/nouveau/bios/fan: hardcode the fan mode to linear
2015-12-19Merge branch 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux into drm-nextDave Airlie26-0/+7016
here is the pull request for the etnaviv DRM driver. It includes the DT bindings and the driver itself, platform devicetree changes will be merged through the respective SoC trees. Otherwise it's just a squashed version of the V2 patches that have been on the list for a while. * 'drm-etnaviv-next' of git://git.pengutronix.de/git/lst/linux: MAINTAINERS: add maintainer and reviewers for the etnaviv DRM driver drm/etnaviv: add initial etnaviv DRM driver drm/etnaviv: add devicetree bindings devicetree: add vendor prefix for Vivante Corporation
2015-12-19Merge tag 'topic/drm-misc-2015-12-18' of git://anongit.freedesktop.org/drm-intel into drm-nextDave Airlie59-203/+188
Seems I lied in my last drm-misc pull request and suddenly there's a big pile of random stuff. Boris dug out Thierry's drm-trivial branch and resubmitted everything since that branch didn't really work out. On top of that Nicolas' changes to drm_dev_set_unique - this might conflict with new driver pulls (I double checked and current drm-next should be fine), so please beware. The -next/-fixes conflict in vmwgfx will change slightly with this here too. * tag 'topic/drm-misc-2015-12-18' of git://anongit.freedesktop.org/drm-intel: (36 commits) drm: use dev_name as default unique name in drm_dev_alloc() drm: make drm_dev_set_unique() not use a format string drm/vmwgfx: Constify function pointer structs drm/udl: Constify function pointer structs drm/tegra: Constify function pointer structs drm/rockchip: Constify function pointer structs drm/nouveau: Constify function pointer structs drm/mgag200: Constify function pointer structs drm/imx: Constify function pointer structs drm/i2c/sil164: Constify function pointer structs drm/i2c/adv7511: Constify function pointer structs drm/exynos: Constify function pointer structs drm/cirrus: Constify function pointer structs drm/i2c/ch7006: Constify function pointer structs drm/bridge/nxp-ptn3460: Constify function pointer structs drm/bridge/dw_hdmi: Constify function pointer structs drm/bochs: Constify function pointer structs drm/atmel-hlcdc: Constify function pointer structs drm/armada: Constify function pointer structs drm: Constify drm_encoder_slave_funcs ...
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.