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2017-08-29i2c: busses: make i2c_adapter_quirks constBhumika Goyal1-1/+1
Make these const as they are only stored as a reference in the quirks field of an i2c_adapter structure, which is const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-11-29i2c: qup: support SMBus block readNaveen Kaje1-3/+61
I2C QUP driver relies on SMBus emulation support from the framework. To handle SMBus block reads, the driver should check I2C_M_RECV_LEN flag and should read the first byte received as the message length. The driver configures the QUP hardware to read one byte. Once the message length is known from this byte, the QUP hardware is configured to read the rest. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-11-29i2c: qup: add ACPI supportNaveen Kaje1-16/+42
Add support to get the device parameters from ACPI. Assume that the clocks are managed by firmware. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-22i2c: qup: skip qup_i2c_suspend if the device is already runtime suspendedSudeep Holla1-1/+2
If the i2c device is already runtime suspended, if qup_i2c_suspend is executed during suspend-to-idle or suspend-to-ram it will result in the following splat: WARNING: CPU: 3 PID: 1593 at drivers/clk/clk.c:476 clk_core_unprepare+0x80/0x90 Modules linked in: CPU: 3 PID: 1593 Comm: bash Tainted: G W 4.8.0-rc3 #14 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) PC is at clk_core_unprepare+0x80/0x90 LR is at clk_unprepare+0x28/0x40 pc : [<ffff0000086eecf0>] lr : [<ffff0000086f0c58>] pstate: 60000145 Call trace: clk_core_unprepare+0x80/0x90 qup_i2c_disable_clocks+0x2c/0x68 qup_i2c_suspend+0x10/0x20 platform_pm_suspend+0x24/0x68 ... This patch fixes the issue by executing qup_i2c_pm_suspend_runtime conditionally in qup_i2c_suspend. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2016-07-27Merge branch 'i2c/for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linuxLinus Torvalds1-83/+72
Pull i2c updates from Wolfram Sang: "Here is the I2C pull request for 4.8: - the core and i801 driver gained support for SMBus Host Notify - core support for more than one address in DT - i2c_add_adapter() has now better error messages. We can remove all error messages from drivers calling it as a next step. - bigger updates to rk3x driver to support rk3399 SoC - the at24 eeprom driver got refactored and can now read special variants with unique serials or fixed MAC addresses. The rest is regular driver updates and bugfixes" * 'i2c/for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (66 commits) i2c: i801: use IS_ENABLED() instead of checking for built-in or module Documentation: i2c: slave: give proper example for pm usage Documentation: i2c: slave: describe buffer problems a bit better i2c: bcm2835: Don't complain on -EPROBE_DEFER from getting our clock i2c: i2c-smbus: drop useless stubs i2c: efm32: fix a failure path in efm32_i2c_probe() Revert "i2c: core: Cleanup I2C ACPI namespace" Revert "i2c: core: Add function for finding the bus speed from ACPI" i2c: Update the description of I2C_SMBUS i2c: i2c-smbus: fix i2c_handle_smbus_host_notify documentation eeprom: at24: tweak the loop_until_timeout() macro eeprom: at24: add support for at24mac series eeprom: at24: support reading the serial number for 24csxx eeprom: at24: platform_data: use BIT() macro eeprom: at24: split at24_eeprom_write() into specialized functions eeprom: at24: split at24_eeprom_read() into specialized functions eeprom: at24: hide the read/write loop behind a macro eeprom: at24: call read/write functions via function pointers eeprom: at24: coding style fixes eeprom: at24: move at24_read() below at24_eeprom_write() ...
2016-07-15i2c: qup: Fixed the DMA segments lengthAbhishek Sahu1-5/+7
1. The current QCOM I2C driver code is failing for transfer length greater than 255. This is happening due to improper segments length as the I2C DMA segments can be maximum of 256 bytes. 2. The transfer length tlen was being initialized with 0 for 256 bytes, which is being passed for DMA mappings resulting in improper DMA mapping length. This patch fixes the above said problems by initializing the block count with the values calculated in qup_i2c_set_blk_data and calculating the remaining length for last DMA segment. Also, the block data length need to be decremented after each transfer. Additionally, this patch corrects the tlen assignment for DMA mapping. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-07-15i2c: qup: Cleared the error bits in ISRAbhishek Sahu1-6/+8
1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07 in some scenarios. The QUP controller generates invalid write in this case, since these addresses are reserved for different bus formats. 2. Also, the error handling is done by I2C QUP ISR in the case of DMA mode. The state need to be RESET in case of any error for clearing the available data in FIFO, which otherwise leaves the BAM DMA controller in hang state. This patch fixes the above two issues by clearing the error bits from I2C and QUP status in ISR in case of I2C error, QUP error and resets the QUP state to clear the FIFO data. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix wrong value of index variableSricharan R1-0/+2
index gets incremented during check to determine if the messages can be transferred with dma. But not reset after that, resulting in wrong start value in subsequent loop, causing failure. Fix it. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2016-06-18i2c: qup: use address helper function in read transferNaveen Kaje1-1/+1
qup_i2c_issue_read() derives the address from i2c_msg. This called in the read path when I2C_M_RD flag is set. Therefore, use the 8 bit address helper function. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix error handlingSricharan R1-35/+41
Among the bus errors reported from the QUP_MASTER_STATUS register only NACK is considered and transfer gets suspended, while other errors are ignored. Correct this and suspend the transfer for other errors as well. This avoids unnecessary 'timeouts' which happens when waiting for events that would never happen when there is already an error condition on the bus. Also the error handling procedure should be the same for both NACK and other bus errors in case of dma mode. So correct that as well. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix broken dma when CONFIG_DEBUG_SG is enabledSricharan R1-36/+15
With CONFIG_DEBUG_SG is enabled and when dma mode is used, below dump is seen, ------------[ cut here ]------------ kernel BUG at include/linux/scatterlist.h:140! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-00459-g9f087b9-dirty #7 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) task: ffffffc036868000 ti: ffffffc036870000 task.ti: ffffffc036870000 PC is at qup_sg_set_buf.isra.13+0x138/0x154 LR is at qup_sg_set_buf.isra.13+0x50/0x154 pc : [<ffffffc0005a0ed8>] lr : [<ffffffc0005a0df0>] pstate: 60000145 sp : ffffffc0368735c0 x29: ffffffc0368735c0 x28: ffffffc036873752 x27: ffffffc035233018 x26: ffffffc000c4e000 x25: 0000000000000000 x24: 0000000000000004 x23: 0000000000000000 x22: ffffffc035233668 x21: ffffff80004e3000 x20: ffffffc0352e0018 x19: 0000004000000000 x18: 0000000000000028 x17: 0000000000000004 x16: ffffffc0017a39c8 x15: 0000000000001cdf x14: ffffffc0019929d8 x13: ffffffc0352e0018 x12: 0000000000000000 x11: 0000000000000001 x10: 0000000000000001 x9 : ffffffc0012b2d70 x8 : ffffff80004e3000 x7 : 0000000000000018 x6 : 0000000030000000 x5 : ffffffc00199f018 x4 : ffffffc035233018 x3 : 0000000000000004 x2 : 00000000c0000000 x1 : 0000000000000003 x0 : 0000000000000000 Process swapper/0 (pid: 1, stack limit = 0xffffffc036870020) Stack: (0xffffffc0368735c0 to 0xffffffc036874000) sg_set_bug expects that the buf parameter passed in should be from lowmem and a valid pageframe. This is not true for pages from dma_alloc_coherent which can be carveouts, hence the check fails. Change allocation of sg buffers from dma_coherent memory to kzalloc to fix the issue. Note that now dma_map/unmap is used to make the kzalloc'ed buffers coherent before passing it to the dmaengine. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-04-11i2c: qup: use new 8 bit address helper functionWolfram Sang1-1/+1
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-03-03i2c: qup: Fix fifo handling after adding V2 supportSricharan R1-7/+39
After the addition of V2 support, there was a regression observed when testing it on MSM8996. The reason is driver puts the controller in to RUN state and writes the data to be 'tx' ed in fifo. But controller has to be put in to 'PAUSE' state and data has to written to fifo. Then should be put in to 'RUN' state separately. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Pramod Gurav <gpramod@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-24i2c: qup: Add bam dma capabilitiesSricharan R1-14/+459
QUP cores can be attached to a BAM module, which acts as a dma engine for the QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data is written to the output FIFO and the BAM producer pipe received data is read from the input FIFO. With BAM capabilities, qup-i2c core can transfer more than 256 bytes, without a 'stop' which is not possible otherwise. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bitSricharan R1-8/+26
The definition of i2c_msg says that "If this is the last message in a group, it is followed by a STOP. Otherwise it is followed by the next @i2c_msg transaction segment, beginning with a (repeated) START" So the expectation is that there is no 'STOP' bit inbetween individual i2c_msg segments with repeated 'START'. Adding the support for the same. This is required for some clients like touchscreen which keeps incrementing counts across individual transfers and 'STOP' bit inbetween resets the counter, which is not required. This patch adds the support in non-dma mode. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> [wsa: updated commit message] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Add V2 tags supportSricharan R1-29/+386
QUP from version 2.1.1 onwards, supports a new format of i2c command tags. Tag codes instructs the controller to perform a operation like read/write. This new tagging version supports bam dma and transfers of more than 256 bytes without 'stop' in between. Adding the support for the same. For each block a data_write/read tag and data_len tag is added to the output fifo. For the final block of data write_stop/read_stop tag is used. Signed-off-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Change qup_wait_writeready function to use for all timeoutsSricharan R1-19/+48
qup_wait_writeready waits only on a output fifo empty event. Change the same function to accept the event and data length to wait as parameters. This way the same function can be used for timeouts in other places as well. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-03-13i2c: qup: make use of the new infrastructure for quirksWolfram Sang1-11/+10
Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
2014-10-20i2c: busses: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-03i2c: qup: Fix order of runtime pm initializationAndy Gross1-4/+8
The runtime pm calls need to be done before populating the children via the i2c_add_adapter call. If this is not done, a child can run into issues trying to do i2c read/writes due to the pm_runtime_sync failing. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2014-08-06i2c: qup: disable clks and return instead of just returning errorPramod Gurav1-4/+8
This fixes a error handling scenario where clocks were not being disabled when QUP_OUTPUT_BLOCK_SIZE returns a size greater than the size of blk_sizes array. So this patch adds a statement to jump to the fail lable to release the clocks. Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-05-14i2c: qup: Fix pm_runtime_get_sync usageAndy Gross1-1/+1
This patch corrects the error check on the call to pm_runtime_get_sync. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-04-06i2c: qup: use proper type fro clk_freqWolfram Sang1-1/+1
It is used with of_property_read_u32(), so it should be u32. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Fixes: 10c5a8425968 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller')
2014-04-03i2c: qup: off by ones in qup_i2c_probe()Dan Carpenter1-2/+2
These should ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()". Fixes: 10c5a8425968 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-03-28i2c: qup: New bus driver for the Qualcomm QUP I2C controllerBjorn Andersson1-0/+768
This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs. The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path engine with input/output FIFOs and an embedded i2c mini-core. The driver supports FIFO mode (for low bandwidth applications) and block mode (interrupt generated for each block-size data transfer). Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Philip Elcan <pelcan@codeaurora.org> [wsa: removed needless IS_ERR_VALUE] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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