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2018-10-05i2c: qup: use core to detect 'no zero length' quirkWolfram Sang1-8/+6
And don't reimplement in the driver. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-06-14Merge branch 'i2c/for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linuxLinus Torvalds1-19/+40
Pull i2c updates from Wolfram Sang: - mainly feature additions to drivers (stm32f7, qup, xlp9xx, mlxcpld, ...) - conversion to use the i2c_8bit_addr_from_msg macro consistently - move includes to platform_data - core updates to allow the (still in review) I3C subsystem to connect - and the regular share of smaller driver updates * 'i2c/for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (68 commits) i2c: qup: fix building without CONFIG_ACPI i2c: tegra: Remove suspend-resume i2c: imx-lpi2c: Switch to SPDX identifier i2c: mxs: Switch to SPDX identifier i2c: busses: make use of i2c_8bit_addr_from_msg i2c: algos: make use of i2c_8bit_addr_from_msg i2c: rcar: document R8A77980 bindings i2c: qup: Add command-line parameter to override SCL frequency i2c: qup: Correct duty cycle for FM and FM+ i2c: qup: Add support for Fast Mode Plus i2c: qup: add probe path for Centriq ACPI devices i2c: robotfuzz-osif: drop pointless test i2c: robotfuzz-osif: remove pointless local variable i2c: rk3x: Don't print visible virtual mapping MMIO address i2c: opal: don't check number of messages in the driver i2c: ibm_iic: don't check number of messages in the driver i2c: imx: Switch to SPDX identifier i2c: mux: pca954x: merge calls to of_match_device and of_device_get_match_data i2c: mux: demux-pinctrl: use proper parent device for demux adapter i2c: mux: improve error message for failed symlink ...
2018-06-12treewide: devm_kzalloc() -> devm_kcalloc()Kees Cook1-4/+4
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-05-31i2c: qup: fix building without CONFIG_ACPIArnd Bergmann1-2/+0
The added Centriq support broke compilation with CONFIG_ACPI disabled: drivers/i2c/busses/i2c-qup.c: In function 'qup_i2c_probe': drivers/i2c/busses/i2c-qup.c:1707:25: error: 'qup_i2c_acpi_match' undeclared (first use in this function); did you mean 'qup_i2c_recv_data'? This fixes it by removing the extraneous #ifdef. All ACPI specific code will be dropped implicitly when that option is disabled, but the compiler first needs to see it. Fixes: 902a91a02bdf ("i2c: qup: add probe path for Centriq ACPI devices") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-29i2c: busses: make use of i2c_8bit_addr_from_msgPeter Rosin1-1/+1
Because it looks neater. For diolan, this allows factoring out some code that is now common between if and else. For eg20t, pch_i2c_writebytes is always called with a write in msgs->flags, and pch_i2c_readbytes with a read. For imx, i2c_imx_dma_write and i2c_imx_write are always called with a write in msgs->flags, and i2c_imx_read with a read. For qup, qup_i2c_write_tx_fifo_v1 is always called with a write in qup->msg->flags. For stu300, also restructure debug output for resends, since that code as a result is only handling debug output. Reviewed-by: Guenter Roeck <linux@roeck-us.net> [diolan] Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [efm32 and imx] Acked-by: Linus Walleij <linus.walleij@linaro.org> [stu300] Signed-off-by: Peter Rosin <peda@axentia.se> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-29i2c: qup: Add command-line parameter to override SCL frequencyAustin Christ1-4/+13
Add a module parameter to override SCL frequency provided by firmware. This can be useful when testing spec compliance for I2C modes or when debugging issues across multiple operating frequencies. Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-29i2c: qup: Correct duty cycle for FM and FM+Austin Christ1-2/+8
The I2C spec UM10204 Rev. 6 specifies the following timings. Standard Fast Mode Fast Mode Plus SCL low 4.7us 1.3us 0.5us SCL high 4.0us 0.6us 0.26us This results in a 33%/66% duty cycle as opposed to the 50%/50% duty cycle used for Standard-mode. Add High Time Divider settings to correct duty cycle for FM(400kHz) and FM+(1MHz). Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-29i2c: qup: Add support for Fast Mode PlusAustin Christ1-3/+8
Previously the QUP driver limited operation mode to I2C Fast Mode. Add Fast Mode Plus functionality by raising SCL limit from 400kHz to 1MHz. Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-29i2c: qup: add probe path for Centriq ACPI devicesAustin Christ1-9/+12
Add support for Qualcomm Centriq devices that are qup-v2 compatible but do not support DMA, so nodma needs to be set. Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: reorganization of driver code to remove polling for qup v2Abhishek Sahu1-385/+515
Following are the major issues in current driver code 1. The current driver simply assumes the transfer completion whenever its gets any non-error interrupts and then simply do the polling of available/free bytes in FIFO. 2. The block mode is not working properly since no handling in being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_READ. 3. An i2c transfer can contain multiple message and QUP v2 supports reconfiguration during run in which the mode should be same for all the sub transfer. Currently the mode is being programmed before every sub transfer which is functionally wrong. If one message is less than FIFO length and other message is greater than FIFO length, then transfers will fail. Because of above, i2c v2 transfers of size greater than 64 are failing with following error message i2c_qup 78b6000.i2c: timeout for fifo out full To make block mode working properly and move to use the interrupts instead of polling, major code reorganization is required. Following are the major changes done in this patch 1. Remove the polling of TX FIFO free space and RX FIFO available bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE, QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ interrupts to handle FIFO’s properly so check all these interrupts. 2. Determine the mode for transfer before starting by checking all the tx/rx data length in each message. The complete message can be transferred either in DMA mode or Programmed IO by FIFO/Block mode. in DMA mode, both tx and rx uses same mode but in PIO mode, the TX and RX can be in different mode. 3. During write, For FIFO mode, TX FIFO can be directly written without checking for FIFO space. For block mode, the QUP will generate OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available space. 4. During read, both TX and RX FIFO will be used. TX will be used for writing tags and RX will be used for receiving the data. In QUP, TX and RX can operate in separate mode so configure modes accordingly. 5. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which will be generated after all the bytes have been copied in RX FIFO. For read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts whenever it has block size of available data. 6. Split the transfer in chunk of one QUP block size(256 bytes) and schedule each block separately. QUP v2 supports reconfiguration during run in which QUP can transfer multiple blocks without issuing a stop events. 7. Port the SMBus block read support for new code changes. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: reorganization of driver code to remove polling for qup v1Abhishek Sahu1-143/+223
Following are the major issues in current driver code 1. The current driver simply assumes the transfer completion whenever its gets any non-error interrupts and then simply do the polling of available/free bytes in FIFO. 2. The block mode is not working properly since no handling in being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ. Because of above, i2c v1 transfers of size greater than 32 are failing with following error message i2c_qup 78b6000.i2c: timeout for fifo out full To make block mode working properly and move to use the interrupts instead of polling, major code reorganization is required. Following are the major changes done in this patch 1. Remove the polling of TX FIFO free space and RX FIFO available bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE, QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ interrupts to handle FIFO’s properly so check all these interrupts. 2. During write, For FIFO mode, TX FIFO can be directly written without checking for FIFO space. For block mode, the QUP will generate OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available space. 3. During read, both TX and RX FIFO will be used. TX will be used for writing tags and RX will be used for receiving the data. In QUP, TX and RX can operate in separate mode so configure modes accordingly. 4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which will be generated after all the bytes have been copied in RX FIFO. For read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts whenever it has block size of available data. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: send NACK for last read sub transfersAbhishek Sahu1-1/+4
According to I2c specification, “If a master-receiver sends a repeated START condition, it sends a not-acknowledge (A) just before the repeated START condition”. QUP v2 supports sending of NACK without stop with QUP_TAG_V2_DATARD_NACK so added the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: fix buffer overflow for multiple msg of maximum xfer lenAbhishek Sahu1-84/+110
The BAM mode requires buffer for start tag data and tx, rx SG list. Currently, this is being taken for maximum transfer length (65K). But an I2C transfer can have multiple messages and each message can be of this maximum length so the buffer overflow will happen in this case. Since increasing buffer length won’t be feasible since an I2C transfer can contain any number of messages so this patch does following changes to make i2c transfers working for multiple messages case. 1. Calculate the required buffers for 2 maximum length messages (65K * 2). 2. Split the descriptor formation and descriptor scheduling. The idea is to fit as many messages in one DMA transfers for 65K threshold value (max_xfer_sg_len). Whenever the sg_cnt is crossing this, then schedule the BAM transfer and subsequent transfer will again start from zero. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: change completion timeout according to transfer lengthAbhishek Sahu1-3/+10
Currently the completion timeout is being taken according to maximum transfer length which is too high if SCL is operating in high frequency. This patch calculates timeout on the basis of one-byte transfer time and uses the same for completion timeout. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: use the complete transfer length to choose DMA modeAbhishek Sahu1-6/+7
Currently each message length in complete transfer is being checked for determining DMA mode and if any of the message length is less than FIFO length then non DMA mode is being used which will increase overhead. DMA can be used for any length and it should be determined with complete transfer length. Now, this patch selects DMA mode if the total length is greater than FIFO length. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: proper error handling for i2c error in BAM modeAbhishek Sahu1-9/+16
Currently the i2c error handling in BAM mode is not working properly in stress condition. 1. After an error, the FIFO are being written with FLUSH and EOT tags which should not be required since already these tags have been written in BAM descriptor itself. 2. QUP state is being moved to RESET in IRQ handler in case of error. When QUP HW encounters an error in BAM mode then it moves the QUP STATE to PAUSE state. In this case, I2C_FLUSH command needs to be executed while moving to RUN_STATE by writing to the QUP_STATE register with the I2C_FLUSH bit set to 1. 3. In Error case, sometimes, QUP generates more than one interrupt which will trigger the complete again. After an error, the flush operation will be scheduled after doing reinit_completion which should be triggered by BAM IRQ callback. If the second QUP IRQ comes during this time then it will call the complete and the transfer function will assume the all the BAM HW descriptors have been completed. 4. The release DMA is being called after each error which will free the DMA tx and rx channels. The error like NACK is very common in I2C transfer and every time this will be overhead. Now, since the error handling is proper so this release channel can be completely avoided. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: fix the transfer length for BAM RX EOT FLUSH tagsAbhishek Sahu1-2/+2
In case of FLUSH operation, BAM copies INPUT EOT FLUSH (0x94) instead of normal EOT (0x93) tag in input data stream when an input EOT tag is received during flush operation. So only one tag will be written instead of 2 separate tags. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: schedule EOT and FLUSH tags at the end of transferAbhishek Sahu1-15/+24
The role of FLUSH and EOT tag is to flush already scheduled descriptors in BAM HW in case of error. EOT is required only when descriptors are scheduled in RX FIFO. If all the messages are WRITE, then only FLUSH tag will be used. A single BAM transfer can have multiple read and write messages. The EOT and FLUSH tags should be scheduled at the end of BAM HW descriptors. Since the READ and WRITE can be present in any order so for some of the cases, these tags are not being written correctly. Following is one of the example READ, READ, READ, READ Currently EOT and FLUSH tags are being written after each READ. If QUP gets NACK for first READ itself, then flush will be triggered. It will look for first FLUSH tag in TX FIFO and will stop there so only descriptors for first READ descriptors be flushed. All the scheduled descriptors should be cleared to generate BAM DMA completion. Now this patch is scheduling FLUSH and EOT only once after all the descriptors. So, flush will clear all the scheduled descriptors and BAM will generate the completion interrupt. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: remove redundant variables for BAM SG countAbhishek Sahu1-24/+18
The rx_nents and tx_nents are redundant. rx_buf and tx_buf can be used for total number of SG entries. Since rx_buf and tx_buf give the impression that it is buffer instead of count so rename it to tx_cnt and rx_cnt for giving it more meaningful variable name. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: minor code reorganization for use_dmaAbhishek Sahu1-8/+11
1. Assigns use_dma in qup_dev structure itself which will help in subsequent patches to determine the mode in IRQ handler. 2. Does minor code reorganization for loops to reduce the unnecessary comparison and assignment. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: fixed releasing dma without flush operation completionAbhishek Sahu1-0/+2
The QUP BSLP BAM generates the following error sometimes if the current I2C DMA transfer fails and the flush operation has been scheduled “bam-dma-engine 7884000.dma: Cannot free busy channel” If any I2C error comes during BAM DMA transfer, then the QUP I2C interrupt will be generated and the flush operation will be carried out to make I2C consume all scheduled DMA transfer. Currently, the same completion structure is being used for BAM transfer which has already completed without reinit. It will make flush operation wait_for_completion_timeout completed immediately and will proceed for freeing the DMA resources where the descriptors are still in process. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Acked-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-03-24i2c: qup: fix copyrights and update to SPDX identifierAbhishek Sahu1-11/+2
The file has been updated from 2016 to 2018 so fixed the copyright years. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-08-29i2c: busses: make i2c_adapter_quirks constBhumika Goyal1-1/+1
Make these const as they are only stored as a reference in the quirks field of an i2c_adapter structure, which is const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-11-29i2c: qup: support SMBus block readNaveen Kaje1-3/+61
I2C QUP driver relies on SMBus emulation support from the framework. To handle SMBus block reads, the driver should check I2C_M_RECV_LEN flag and should read the first byte received as the message length. The driver configures the QUP hardware to read one byte. Once the message length is known from this byte, the QUP hardware is configured to read the rest. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-11-29i2c: qup: add ACPI supportNaveen Kaje1-16/+42
Add support to get the device parameters from ACPI. Assume that the clocks are managed by firmware. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Austin Christ <austinwc@codeaurora.org> Reviewed-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-22i2c: qup: skip qup_i2c_suspend if the device is already runtime suspendedSudeep Holla1-1/+2
If the i2c device is already runtime suspended, if qup_i2c_suspend is executed during suspend-to-idle or suspend-to-ram it will result in the following splat: WARNING: CPU: 3 PID: 1593 at drivers/clk/clk.c:476 clk_core_unprepare+0x80/0x90 Modules linked in: CPU: 3 PID: 1593 Comm: bash Tainted: G W 4.8.0-rc3 #14 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) PC is at clk_core_unprepare+0x80/0x90 LR is at clk_unprepare+0x28/0x40 pc : [<ffff0000086eecf0>] lr : [<ffff0000086f0c58>] pstate: 60000145 Call trace: clk_core_unprepare+0x80/0x90 qup_i2c_disable_clocks+0x2c/0x68 qup_i2c_suspend+0x10/0x20 platform_pm_suspend+0x24/0x68 ... This patch fixes the issue by executing qup_i2c_pm_suspend_runtime conditionally in qup_i2c_suspend. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2016-07-27Merge branch 'i2c/for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linuxLinus Torvalds1-83/+72
Pull i2c updates from Wolfram Sang: "Here is the I2C pull request for 4.8: - the core and i801 driver gained support for SMBus Host Notify - core support for more than one address in DT - i2c_add_adapter() has now better error messages. We can remove all error messages from drivers calling it as a next step. - bigger updates to rk3x driver to support rk3399 SoC - the at24 eeprom driver got refactored and can now read special variants with unique serials or fixed MAC addresses. The rest is regular driver updates and bugfixes" * 'i2c/for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (66 commits) i2c: i801: use IS_ENABLED() instead of checking for built-in or module Documentation: i2c: slave: give proper example for pm usage Documentation: i2c: slave: describe buffer problems a bit better i2c: bcm2835: Don't complain on -EPROBE_DEFER from getting our clock i2c: i2c-smbus: drop useless stubs i2c: efm32: fix a failure path in efm32_i2c_probe() Revert "i2c: core: Cleanup I2C ACPI namespace" Revert "i2c: core: Add function for finding the bus speed from ACPI" i2c: Update the description of I2C_SMBUS i2c: i2c-smbus: fix i2c_handle_smbus_host_notify documentation eeprom: at24: tweak the loop_until_timeout() macro eeprom: at24: add support for at24mac series eeprom: at24: support reading the serial number for 24csxx eeprom: at24: platform_data: use BIT() macro eeprom: at24: split at24_eeprom_write() into specialized functions eeprom: at24: split at24_eeprom_read() into specialized functions eeprom: at24: hide the read/write loop behind a macro eeprom: at24: call read/write functions via function pointers eeprom: at24: coding style fixes eeprom: at24: move at24_read() below at24_eeprom_write() ...
2016-07-15i2c: qup: Fixed the DMA segments lengthAbhishek Sahu1-5/+7
1. The current QCOM I2C driver code is failing for transfer length greater than 255. This is happening due to improper segments length as the I2C DMA segments can be maximum of 256 bytes. 2. The transfer length tlen was being initialized with 0 for 256 bytes, which is being passed for DMA mappings resulting in improper DMA mapping length. This patch fixes the above said problems by initializing the block count with the values calculated in qup_i2c_set_blk_data and calculating the remaining length for last DMA segment. Also, the block data length need to be decremented after each transfer. Additionally, this patch corrects the tlen assignment for DMA mapping. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-07-15i2c: qup: Cleared the error bits in ISRAbhishek Sahu1-6/+8
1. Current QCOM I2C driver hangs when sending data to address 0x03-0x07 in some scenarios. The QUP controller generates invalid write in this case, since these addresses are reserved for different bus formats. 2. Also, the error handling is done by I2C QUP ISR in the case of DMA mode. The state need to be RESET in case of any error for clearing the available data in FIFO, which otherwise leaves the BAM DMA controller in hang state. This patch fixes the above two issues by clearing the error bits from I2C and QUP status in ISR in case of I2C error, QUP error and resets the QUP state to clear the FIFO data. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix wrong value of index variableSricharan R1-0/+2
index gets incremented during check to determine if the messages can be transferred with dma. But not reset after that, resulting in wrong start value in subsequent loop, causing failure. Fix it. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2016-06-18i2c: qup: use address helper function in read transferNaveen Kaje1-1/+1
qup_i2c_issue_read() derives the address from i2c_msg. This called in the read path when I2C_M_RD flag is set. Therefore, use the 8 bit address helper function. Signed-off-by: Naveen Kaje <nkaje@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix error handlingSricharan R1-35/+41
Among the bus errors reported from the QUP_MASTER_STATUS register only NACK is considered and transfer gets suspended, while other errors are ignored. Correct this and suspend the transfer for other errors as well. This avoids unnecessary 'timeouts' which happens when waiting for events that would never happen when there is already an error condition on the bus. Also the error handling procedure should be the same for both NACK and other bus errors in case of dma mode. So correct that as well. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-06-18i2c: qup: Fix broken dma when CONFIG_DEBUG_SG is enabledSricharan R1-36/+15
With CONFIG_DEBUG_SG is enabled and when dma mode is used, below dump is seen, ------------[ cut here ]------------ kernel BUG at include/linux/scatterlist.h:140! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-00459-g9f087b9-dirty #7 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) task: ffffffc036868000 ti: ffffffc036870000 task.ti: ffffffc036870000 PC is at qup_sg_set_buf.isra.13+0x138/0x154 LR is at qup_sg_set_buf.isra.13+0x50/0x154 pc : [<ffffffc0005a0ed8>] lr : [<ffffffc0005a0df0>] pstate: 60000145 sp : ffffffc0368735c0 x29: ffffffc0368735c0 x28: ffffffc036873752 x27: ffffffc035233018 x26: ffffffc000c4e000 x25: 0000000000000000 x24: 0000000000000004 x23: 0000000000000000 x22: ffffffc035233668 x21: ffffff80004e3000 x20: ffffffc0352e0018 x19: 0000004000000000 x18: 0000000000000028 x17: 0000000000000004 x16: ffffffc0017a39c8 x15: 0000000000001cdf x14: ffffffc0019929d8 x13: ffffffc0352e0018 x12: 0000000000000000 x11: 0000000000000001 x10: 0000000000000001 x9 : ffffffc0012b2d70 x8 : ffffff80004e3000 x7 : 0000000000000018 x6 : 0000000030000000 x5 : ffffffc00199f018 x4 : ffffffc035233018 x3 : 0000000000000004 x2 : 00000000c0000000 x1 : 0000000000000003 x0 : 0000000000000000 Process swapper/0 (pid: 1, stack limit = 0xffffffc036870020) Stack: (0xffffffc0368735c0 to 0xffffffc036874000) sg_set_bug expects that the buf parameter passed in should be from lowmem and a valid pageframe. This is not true for pages from dma_alloc_coherent which can be carveouts, hence the check fails. Change allocation of sg buffers from dma_coherent memory to kzalloc to fix the issue. Note that now dma_map/unmap is used to make the kzalloc'ed buffers coherent before passing it to the dmaengine. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-04-11i2c: qup: use new 8 bit address helper functionWolfram Sang1-1/+1
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-03-03i2c: qup: Fix fifo handling after adding V2 supportSricharan R1-7/+39
After the addition of V2 support, there was a regression observed when testing it on MSM8996. The reason is driver puts the controller in to RUN state and writes the data to be 'tx' ed in fifo. But controller has to be put in to 'PAUSE' state and data has to written to fifo. Then should be put in to 'RUN' state separately. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Pramod Gurav <gpramod@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-24i2c: qup: Add bam dma capabilitiesSricharan R1-14/+459
QUP cores can be attached to a BAM module, which acts as a dma engine for the QUP core. When DMA with BAM is enabled, the BAM consumer pipe transmitted data is written to the output FIFO and the BAM producer pipe received data is read from the input FIFO. With BAM capabilities, qup-i2c core can transfer more than 256 bytes, without a 'stop' which is not possible otherwise. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Transfer each i2c_msg in i2c_msgs without a stop bitSricharan R1-8/+26
The definition of i2c_msg says that "If this is the last message in a group, it is followed by a STOP. Otherwise it is followed by the next @i2c_msg transaction segment, beginning with a (repeated) START" So the expectation is that there is no 'STOP' bit inbetween individual i2c_msg segments with repeated 'START'. Adding the support for the same. This is required for some clients like touchscreen which keeps incrementing counts across individual transfers and 'STOP' bit inbetween resets the counter, which is not required. This patch adds the support in non-dma mode. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> [wsa: updated commit message] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Add V2 tags supportSricharan R1-29/+386
QUP from version 2.1.1 onwards, supports a new format of i2c command tags. Tag codes instructs the controller to perform a operation like read/write. This new tagging version supports bam dma and transfers of more than 256 bytes without 'stop' in between. Adding the support for the same. For each block a data_write/read tag and data_len tag is added to the output fifo. For the final block of data write_stop/read_stop tag is used. Signed-off-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-02-12i2c: qup: Change qup_wait_writeready function to use for all timeoutsSricharan R1-19/+48
qup_wait_writeready waits only on a output fifo empty event. Change the same function to accept the event and data length to wait as parameters. This way the same function can be used for timeouts in other places as well. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Tested-by: Archit Taneja <architt@codeaurora.org> Tested-by: Telkar Nagender <ntelkar@codeaurora.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2015-03-13i2c: qup: make use of the new infrastructure for quirksWolfram Sang1-11/+10
Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com>
2014-10-20i2c: busses: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-03i2c: qup: Fix order of runtime pm initializationAndy Gross1-4/+8
The runtime pm calls need to be done before populating the children via the i2c_add_adapter call. If this is not done, a child can run into issues trying to do i2c read/writes due to the pm_runtime_sync failing. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@kernel.org
2014-08-06i2c: qup: disable clks and return instead of just returning errorPramod Gurav1-4/+8
This fixes a error handling scenario where clocks were not being disabled when QUP_OUTPUT_BLOCK_SIZE returns a size greater than the size of blk_sizes array. So this patch adds a statement to jump to the fail lable to release the clocks. Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-05-14i2c: qup: Fix pm_runtime_get_sync usageAndy Gross1-1/+1
This patch corrects the error check on the call to pm_runtime_get_sync. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-04-06i2c: qup: use proper type fro clk_freqWolfram Sang1-1/+1
It is used with of_property_read_u32(), so it should be u32. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Fixes: 10c5a8425968 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller')
2014-04-03i2c: qup: off by ones in qup_i2c_probe()Dan Carpenter1-2/+2
These should ">= ARRAY_SIZE()" instead of "> ARRAY_SIZE()". Fixes: 10c5a8425968 ('i2c: qup: New bus driver for the Qualcomm QUP I2C controller') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-03-28i2c: qup: New bus driver for the Qualcomm QUP I2C controllerBjorn Andersson1-0/+768
This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs. The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path engine with input/output FIFOs and an embedded i2c mini-core. The driver supports FIFO mode (for low bandwidth applications) and block mode (interrupt generated for each block-size data transfer). Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Philip Elcan <pelcan@codeaurora.org> [wsa: removed needless IS_ERR_VALUE] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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