| Age | Commit message (Collapse) | Author | Files | Lines |
|---|
|
Add the SAR ADC driver for the Amlogic Meson-G12A SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Meson8b and Meson8m2 use the same logic to convert the ADC register
value to celsius, which is different from Meson8:
- Meson8 has different multiplier and divider values
- Meson8 uses a 4-bit TSC (temperature sensor coefficient) which fits
into the 4-bit field in the MESON_SAR_ADC_DELTA_10 register:
MESON_SAR_ADC_DELTA_10_TS_C_MASK. Meson8b and Meson8m2 have a 5-bit
TSC which requires writing the upper-most bit into the
MESON_HHI_DPLL_TOP_0[9] register from the HHI register area.
This adds support for the temperature sensor on the Meson8b and Meson8m2
SoCs by implementing the logic to write the upper-most TSC bit into the
HHI register area. The SoC-specific values (temperature_trimming_bits,
temperature_multiplier, temperature_divider) are added - these simply
integrate into the existing infrastructure (which was implemented for
Meson8) and thus require no further changes to the existing temperature
calculation logic.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Before this patch we are registering the internal clocks (for example on
Meson8b, where the SAR ADC IP block implements the divider and gate
clocks) with the following names:
- /soc/cbus@c1100000/adc@8680#adc_div
- /soc/cbus@c1100000/adc@8680#adc_en
This is bad because the common clock framework uses the clock to create
a directory in <debugfs>/clk. With such name, the directory creation
(silently) fails and the debugfs entry ends up being created at the
debugfs root.
With this change, the new clock names are:
- c1108680.adc#adc_div
- c1108680.adc#adc_en
This matches the clock naming scheme used in the PWM, Ethernet and MMC
drivers. It also fixes the problem with debugfs.
The idea is shamelessly taken from commit b96e9eb62841c5 ("pwm: meson:
Fix mux clock names").
Fixes: 3921db46a8c5bc ("iio: Convert to using %pOF instead of full_name")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
devm_kasprintf() may return NULL on failure of internal allocation thus
the assignments to init.name are not safe if not checked. On error
meson_sar_adc_clk_init() returns negative values so -ENOMEM in the
(unlikely) failure case of devm_kasprintf() should be fine here.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Channel 6 of the SAR ADC can be switched between two inputs:
SAR_ADC_CH6 input (an actual pad on the SoC) and the signal from the
temperature sensor inside the SoC.
To get usable results from the temperature sensor we need to read the
corresponding calibration data from the eFuse and pass it to the SAR ADC
registers. If the temperature sensor is not calibrated (the eFuse data
contains a bit for this) then the driver will only register the
iio_chan_spec's for voltage measurements.
This only enables the temperature sensor for the Meson8 SoC. Meson8b and
Meson8m2 SoCs can be supported in the future as well but we first need
a way to pass the fifth TSC (temperature sensor coefficient) bit to the
HHI register area (apart from that the infrastructure as already
implemented for Meson8 can be used). On the 64-bit SoCs (GXBB, GXL and
GXM) the temperature sensor inside SAR ADC is firmware-controlled (by
BL30, we can simply use the SCPI hwmon driver to get the chip
temperature).
To keep the devicetree interface backwards compatible we simply skip the
temperature sensor initialization if no eFuse nvmem cell is passed via
devicetree.
The public documentation for the SAR ADC IP block does not explain how
to use the registers to read the temperature. The logic from this patch
is based on reading and understanding Amlogic's GPL kernel sources.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Until now the "channel" number is identical to how the channel is
identified inside the (FIFO) registers. In our case we have eight
channels and the hardware also has eight inputs.
However, there are two special inputs:
- channel 6 can select between the SAR_ADC_CH6 pad and the chip's
internal temperature sensor
- channel 7 can select between SAR_ADC_CH7 and VSS, VDD / 4, VDD / 2,
VDD * 3 / 4 and VDD.
When programming the registers to read for example the temperature
sensor we have to select FIFO channel 6, set the correct bit which muxes
channel 6 to the temperature sensor and then start the ADC measurement
for channel 6 as usual.
When we add support for the temperature sensor the driver has to know
about that it has to use FIFO channel 6 to measure using the chip's
internal temperature sensor. However, in that case the iio_chan_spec
channel will not be 6 because this is already used for the SAR_ADC_CH6
pad input. Thus we use iio_chan_spec's address field to store the FIFO
channel number for each channel.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
In the future we may support two different channel sets:
- one which includes the voltage pads and the temperature sensor output
(for Meson8, Meson8b and Meson8m2)
- one which only includes the voltage pads (GXBB, GXL, GXM and AXG)
Channel 7 has a special function on all of these platforms. However,
since we will have different channel array definitions we want our code
to always use whatever channels struct iio_dev uses.
No functional changes for now. This is the preparation for adding
temperature sensor support to this driver.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Commit 053ffe3c8cfe31 ("iio: adc: meson-saradc: squash and share the
common adc platform data") put all the data which is needed at runtime
from struct meson_sar_adc_data to a new struct meson_sar_adc_param so
we can re-use the platform specific configuration without having to
duplicate everything just to change the name.
The only place where struct meson_sar_adc_data is now needed is the
_probe function which has to pass the name to the iio_dev. All other
functions only need access to struct meson_sar_adc_param. This means we
can simplify struct meson_sar_adc_priv.
The goal of this patch is to make the code a bit easier to read since
this removes one level of nesting. No functional changes intended.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
This simplifies our _probe function by using of_device_get_match_data
instead of open-coding it. No functional changes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
This define is of no use because the driver is avoiding shifting bits
by itself but using FIELD_GET/FIELD_PREP (which are using bit masks)
instead. There is already a MESON_SAR_ADC_DELTA_10_TS_C_MASK bit mask so
MESON_SAR_ADC_DELTA_10_TS_C_SHIFT was redundant.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
The SAR ADC on Meson8m2 behaves identical to the one found in the
Meson8b SoCs. Add a separate compatible string because the temperature
sensor logic (not supported yet) differs between Meson8 and Meson8m2
(however, it's the same for Meson8b and Meson8m2).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Jonathan writes:
1st round of IIO new device support, features and cleanup for the 4.18 cycle
A nice mix this time of excellent cleanups (many to send drivers
speeding toward staging graduations) and new drivers / device support.
A good part of this is Brian Masney's never ending task on the tsl2x7x
driver. The end is in sight so hopefully we'll get that one out of
staging very soon!
New device support
* AD5686
- Support AD5685R (was wrongly present as AD5685)
- Support AD5672R, AD5676, AD5676, AD5684R and AD5686R 4 and 8 channel
SPI DACs with various precisions.
- Support AD5671R, AD5675R, AD5694, AD5694R, AD5695R, AD5696 and AD5696R
I2C DACs with various percisions and numbers of channels.
* Analog front end rescale driver - New driver.
- Support current sensing usings a shunt resistor.
- Support simple voltage dividers.
- support simple current sense amplifiers.
* TI dac5571
- New driver and device bindings supporting:
dac5571, dac6571, dac7571, dac5574, dac6574, dac7574,
dac5573, dac6573 and dac7573
* Meson-adc
- Support for Meson AXG with DT bindings.
* mpu6050
- Support the mpu9255 which only requires additional WHOAMI entry and
compatible string.
* st_lsm6dsx
- Support for lsm330dlc combinded accelerometer and gyro sensors with
DT bindings.
* stm32_adc
- Add support for STM32MP1 with bindings.
Staging graduations
* adis16201 after some excelent cleanup by Himanshu Jha.
* adis16029 after some excelent cleanup by Shreeya Patel.
New features:
* ABI docs
- Add core ABI docs for angle channels.
* inv_mpu6050
- Provide support for the full range of interrupts the device
supports.
* st_accel
- Add SMO8840 ACPI ID seen in the wild on some Lenovo machines.
* stx104
- Provide a multiple gpio get function.
Cleanups / Minor fixes
* core
- Use new nested structure support to improve kernel-doc.
* ad2s1200
- Use be16_to_cpup instead of opencoding.
* ad5686
- Indentation tidy up.
- Switch to SPDX
- Refactor to allow various numbers of channels.
- Refactor to separate core and SPI specific support, prior to
addition of i2c equivalent devices.
* ad7606
- Use drvdata directly from device rather than boucing via the
platform_device structure.
* ad7746
- Replace opencoded byte swapped i2c calls with _swapped variants.
- White space and line break readability improvements.
- Reorder includes and variable declarations where appropriate.
* ad7791
- Changes to the AD ADC library used by this driver took in the
sampling frequency. This lead to be the wrong path being the one
tied to the resulting attribute, so it didn't work, and a warning
to be printed.
* ad7780
- Remove apparent support for sampling frequency control on devices
that don't support changing the sampling attributes.
* ade7854
- Fix a read of the wrong number of bits.
- Improve error handling on i2c read/write errors.
- Rework i2c and spi code to reduce duplication.
* adis16201 (staging)
- Improve meaning inherent in some macro names by adding units etc
where relevant.
- Adjust comments to improve detail and drop the irrelevant.
- Rename register address definitions definitions to add a _REG
postfix, clearly separating them from field definitions. Reorganize
the definitions to group register address and fields.
- Use sign_extend32 rather than open coding.
- Reverse Xmas tree ordering where appropriate and align function args.
- Remove unused headers.
- Use GENMASK where appropriate instead of open coding.
* adis16209 (staging)
- Indent field definitions to visually separate them from
register address definitions.
- Use reverse xmas tree ordering where appropriate.
- Add some whitespace where it will help readability.
- Drop some unused headers.
- Use GENMASK where appropriate.
* ad2s1200
- Drop unnecessary includes and reorder alphabetically.
- Reverse xmas tree and blank line cleanups.
* atlas-ph-sensor
- Use msleep instead of usleep_range where the precise value doesn't
matter and the delays are long.
* bcm150
- Drop transaction splitting as core now handles it.
* cros_ec
- Move the shared header to the include/iio/common directory.
This brings it inline with the other multiple type devices.
- Use drvdata directly from device rather than boucing via the
platform_device structure.
* hid-sensors
- Use drvdata directly from device rather than boucing via the
platform_device structure.
* inv_mpu6050
- Clear out a second function definition for the same function.
- Don't flush fifo when the iio buffer is full but just drop excess
data.
- Tidy up set_power_itg and ensure it is used in the right places.
- Use set_power_itg rather than opencoding it again in the i2c mux
control.
- Make sure error paths disable the power if undoing power on.
- Used managed devm_ functions during probe. Delete remove function.
- Refactor to pull raw data read out of read_raw function.
- Simplify data reading error paths.
- Only enable the i2c mux for chips with the i2c aux bus (not icm20608)
- Fix a potential deadlock due to varying lock ordering.
- Fix an issue where first sample from gyro after enabling is unstable
by dropping the first sample.
- Fix an issue where the user_ctrl register is incorrectly overwritten.
- Tidy up some grammar and spelling minor issus.
* mcp320x
- Use vendor compatible strings.
* mcp4018
- Switch to using i2c .probe_new.
* mcp4351
- switch to using i2c .probe_new.
* meson-adc
- rework handing on common ADC platform data so it can be shared
across multiple families of SoCs.
* sca3000
- Fix an error handling path if the ring configure fails.
* st_lsm6dsx
- Fix a wrong fifo threshold mask (no actual effect)
* stm32-dfsdm
- Style fixes and cleanups.
- Check filter ID is in range and check spi-max-frequency.
* tsl2x7x (staging)
- Drop some unnecessary function calls, unused variables and
unnecessary local variables.
- Fix wrong interrupt type.
- Avoid unnecessary double clear of interrupt.
- Simplify proximity calibration call which did various things
unrelated to actually calibrating.
- Separate control of the proximity and ALS interrupts.
- Improve consistency of logging.
- Separate ALS and proximity persistence settings as they have
separate hardware controls.
- Tidy up variable ordering.
- Add Brian to copyright notice given consider work on this driver.
- Take advantage of hardware support for I2C address auto increment.
- Combine individuaal enable and period attributes for the two
directions on the threshold events into a single value as the
hardware doesn't separate them.
- Move integration_time* attributes from light channel to
intensity value as they effect the intensity readings directly
and the light reading only indirectly. Hence this better
reflects reality. Also move the calibscale_available.
- Avoid returning an error in the IRQ handler.
- Hard code the reg value in _clear_interrupts as it only takes
one value in the code. Result is the function has little
purpose so opencode the two remaining i2c_smbus_write_byte
calls.
- Drop some unnecessary checking of the chip status register.
- Tidy up return path in _write_interrupt_config.
- Tidy up the ID verification code.
- Move the power and diode settings defines into the header as these
are needed for platform data configuration.
- Various renames and comment cleanups for consistency and clarity.
- Use actual device defaults for default startup settings.
- SPDX
- Add some range sanity checking to sysfs attribute writes.
- Don't provide event interfaces if the interrupt line isn't available.
- Use IIO_CONST_ATTR macro for calibscale_available as it's a constant
string.
- Fix the integration time and lux equations.
- Make device IDs explicit index values in the device_channel_config array.
|
|
Add the SAR ADC driver for the Amlogic Meson-AXG SoC.
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Extract and promote common adc platform data into a new structure,
to make it better share the info between several SoCs,
this will avoid duplicating the code all over the place,
Save a few memory and make the code more maintainable.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
The meson_sar_adc_lock() function is not supposed to hold the
"indio_dev->mlock" on the error path.
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
On some Meson8 devices the channel muxes are not programmed. This
results in garbage values when trying to read channels that are not set
up.
Fix this by initializing the channel 0 and 1 muxes in
MESON_SAR_ADC_CHAN_10_SW as well as the muxes for all other channels in
MESON_SAR_ADC_AUX_SW based on what the vendor driver does (which is
simply a 1:1 mapping of channel number and channel mux).
This only showed up on Meson8 devices, because for GXBB and newer BL30
is taking care of initializing the channel muxes.
This additionally fixes a typo in the
MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK macro because the old definition
assumed that the register fields were 2 bit wide, while they are
actually 3 bit wide.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
GX SoCs use a 1.2 MHz ADC clock, while the older SoCs use a 1.14 MHz
clock.
A comment in the driver from Amlogic's GPL kernel says that it's
running at 1.28 MHz. However, it's actually programming a divider of
20 + 1. With a XTAL clock of 24 MHz this results in a frequency of
1.14 MHz. (their calculation might be based on a 27 MHz XTAL clock,
but this is not what we have on the Meson8 and Meson8b SoCs).
The ADC was still working with the 1.2MHz clock. In my own tests I did
not see a difference between 1.2 and 1.14 MHz (regardless of the clock
frequency used, the ADC results were identical).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
This resolves the merge issue pointed out by Stephen in
drivers/iio/adc/meson_saradc.c.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC,
it is irrelevant for the SAR ADC.
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
The Meson GXBB and newer SoCs have a few more registers than the older
Meson8 and Meson8b SoCs.
Use a separate regmap config to limit the older SoCs to the DELTA_10
register.
Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Meson8 and Meson8b do not have the MESON_SAR_ADC_REG11 register. The
bandgap setting for these SoCs is configured in the
MESON_SAR_ADC_DELTA_10 register instead.
Make the driver aware of this difference and use the correct bandgap
register depending on the SoC.
This has worked fine on Meson8 and Meson8b because the bootloader is
already initializing the bandgap setting.
Fixes: 6c76ed31cd05 ("iio: adc: meson-saradc: add Meson8b SoC compatibility")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Meson8 and Meson8b SoCs use the the SAR ADC gate clock provided by the
MESON_SAR_ADC_REG3 register within the SAR ADC register area.
According to the datasheet (and the existing MESON_SAR_ADC_REG3_CLK_EN
definition) the gate is on bit 30.
The fls() function returns the last set bit, which is "bit index + 1"
(fls(MESON_SAR_ADC_REG3_CLK_EN) returns 31). Fix this by switching to
__ffs() which returns the first set bit, which is bit 30 in our case.
This off by one error results in the ADC not being usable on devices
where the bootloader did not enable the clock.
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
The equivalent of both of these are now done via macro magic when
the relevant register calls are made. The actual structure
elements will shortly go away.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
|
|
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Hartmut Knaack <knaack.h@gmx.de>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-iio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
Check return value from call to of_match_device()
in order to prevent a NULL pointer dereference.
In case of NULL print error message and return -ENODEV
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
|
We want the staging fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
meson_sar_adc_clear_fifo passes a 0 as value-pointer to regmap_read().
In case of the meson-saradc driver this ends up in regmap_mmio_read(),
where the value-pointer is de-referenced unconditionally to assign the
value which was read.
Fix this by passing an actual pointer, even though all we want to do is
to discard the value.
As a side-effect this fixes a sparse warning ("Using plain integer as
NULL pointer") as reported by Paolo Cretaro.
Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Reported-by: Paolo Cretaro <paolocretaro@gmail.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
Meson GX SoCs however use some magic bits to prevent simultaneous (=
conflicting, because only consumer should use the FIFO buffer with the
ADC results) usage by the Linux kernel and the bootloader (the BL30
bootloader uses the SAR ADC to read the CPU temperature).
This patch changes guards all BL30 functionality so it is skipped on
SoCs which don't have it. Since the hardware itself doesn't know whether
BL30 is available the internal meson_sar_adc_data is extended so this
information can be provided per of_device_id.data inside the driver.
Additionally the clocks "adc_clk" and "adc_sel" are not provided by the
clock-controller itself. "adc_sel" is not available at all. "adc_clk"
is provided by the SAR ADC IP block itself on Meson8b (and earlier).
This is already supported by the meson_saradc driver.
Finally this introduces new of_device_ids for the Meson8 and Meson8b
SoCs so the driver can be wired up in the corresponding DT.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
These are only passed as of_device_id.data and never modified. Thus we
can mark them as static const, just like the of_device_id instances
where they are used.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
This patch adds calibration for the Meson SAR ADC.
Points 25% vref and 75% vref are used for calibration.
It uses a simple linear calibration function: SCALE * val + BIAS
Successfully tested on a Odroid C2.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
After sampling there should always be only one value in the FIFO.
This also applies to averaging mode as the averaging is done
chip-internally. So we don't have to loop and let the driver
complain if there's not exactly one value in the FIFO.
If the value belongs to a different channel then don't silently
swallow the value but complain.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
Switch from polling to interrupt mode.
Successfully tested on a S905GXBB-based Odroid C2.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
|
This adds support for the SAR (Successive Approximation Register) ADC
on the Amlogic Meson SoCs.
The code is based on the public S805 (Meson8b) and S905 (GXBB)
datasheets (see [0] and [1]), as well as by reading (various versions
of) the vendor driver and by inspecting the registers on the vendor
kernels of my testing-hardware.
Currently the GXBB, GXL and GXM SoCs are supported. GXBB hardware has
10-bit ADC resolution, while GXL and GXM have 12-bit ADC resolution.
The code was written to support older SoCs (Meson8 and Meson8b) as well,
but due to lack of actual testing-hardware no of_device_id was added for
these.
Two "features" from the vendor driver are currently missing:
- the vendor driver uses channel #7 for calibration (this improves the
accuracy of the results - in my tests the results were less than 3%
off without calibration compared to the vendor driver). Adding support
for this should be easy, but is not required for most applications.
- channel #6 is connected to the SoCs internal temperature sensor.
Adding support for this is probably not so easy since (based on the
u-boot sources) most SoC versions are using different registers and
algorithms for the conversion from "ADC value" to temperature.
Supported by the hardware but currently not supported by the driver:
- reading multiple channels at the same time (the hardware has a FIFO
buffer which stores multiple results)
- continuous sampling (this would require a way to enable this
individually because otherwise the ADC would be drawing power
constantly)
- interrupt support (similar to the vendor driver this new driver is
polling the results. It is unclear if the IRQ-mode is supported on
older (Meson6 or Meson8) hardware as well or if there are any errata)
[0]
http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
[1] http://dn.odroid.com/S905/DataSheet/S905_Public_Datasheet_V1.1.4.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
|
Neil Armstrong
Martin Blumenstingl
Nicholas Mc Guire
Greg Kroah-Hartman
Xingyu Chen
Yixun Lan
Dan Carpenter
Jonathan Cameron
Rob Herring
Gustavo A. R. Silva
Heiner Kallweit