linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2015-05-05	iw_cxgb4: Cleanup register defines/MACROS	Hariprasad S	1	-1/+3
	Cleanup macros and register defines for consistency Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
2015-01-16	iw_cxgb4: Cleanup register defines/MACROS defined in t4fw_ri_api.h	Hariprasad Shenai	1	-406/+406
	Cleanup all the MACROS that are defined in t4fw_ri_api.h and affected files Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-07-17	cxgb4/iw_cxgb4: Move common defines to cxgb4	Anish Bhatt	1	-1/+0
	This define is used by cxgb4i and iw_cxgb4, moving to avoid code duplication Signed-off-by: Anish Bhatt <anish@chelsio.com> Acked-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-06-10	iw_cxgb4: Choose appropriate hw mtu index and ISS for iWARP connections	Hariprasad Shenai	1	-0/+1
	Select the appropriate hw mtu index and initial sequence number to optimize hw memory performance. Add new cxgb4_best_aligned_mtu() which allows callers to provide enough information to be used to [possibly] select an MTU which will result in the TCP Data Segment Size (AKA Maximum Segment Size) to be an aligned value. If an RTR message exhange is required, then align the ISS to 8B - 1 + 4, so that after the SYN the send seqno will align on a 4B boundary. The RTR message exchange will leave the send seqno aligned on an 8B boundary. If an RTR is not required, then align the ISS to 8B - 1. The goal is to have the send seqno be 8B aligned when we send the first FPDU. Based on original work by Casey Leedom <leeedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: Casey Leedom <leedom@chelsio.com> Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-04-28	RDMA/cxgb4: Force T5 connections to use TAHOE congestion control	Steve Wise	1	-0/+14
	This is required to work around a T5 HW issue. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
2010-07-21	RDMA/cxgb4: Add module option to tweak delayed ack	Steve Wise	1	-0/+10
	Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
2010-04-21	RDMA/cxgb4: Add driver for Chelsio T4 RNIC	Steve Wise	1	-0/+829
	Add an RDMA/iWARP driver for Chelsio T4 Ethernet adapters. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>