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2015-02-04iommu: Update my email addressJoerg Roedel1-1/+1
The AMD address is dead for a long time already, replace it with a working one. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-08-26iommu/amd: Move struct iommu_dev_data to amd_iommu.cJoerg Roedel1-21/+0
The struct is only used there, so it doesn't need to be in the header file. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-07-31Merge branches 'x86/vt-d', 'x86/amd', 'arm/omap', 'ppc/pamu', 'arm/smmu', 'arm/exynos' and 'core' into nextJoerg Roedel1-6/+0
2014-07-09iommu/amd: Moving PPR fault flags macros definitionsAlexey Skidanov1-6/+0
Any kernel source registering the invalid PPR calback may include the header file with PPR fault flags macros definitions. Thus we move them to include/linux/amd-iommu.h Signed-off-by: Alexey Skidanov <Alexey.Skidanov@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-07-04iommu/amd: Add sysfs supportAlex Williamson1-0/+3
AMD-Vi support for IOMMU sysfs. This allows us to associate devices with a specific IOMMU device and examine the capabilities and features of that IOMMU. The AMD IOMMU is hosted on and actual PCI device, so we make that device the parent for the IOMMU class device. This initial implementaiton exposes only the capability header and extended features register for the IOMMU. # find /sys | grep ivhd /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:00.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:02.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:04.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:09.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:11.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:12.0 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:12.2 /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/devices/0000:00:13.0 ... /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/power /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/power/control ... /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/device /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/subsystem /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/amd-iommu /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/amd-iommu/cap /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/amd-iommu/features /sys/devices/pci0000:00/0000:00:00.2/iommu/ivhd0/uevent /sys/class/iommu/ivhd0 Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-07-04iommu/amd: Use iommu_group_get_for_dev()Alex Williamson1-1/+0
The common iommu_group_get_for_dev() allows us to greatly simplify our group lookup for a new device. Also, since we insert IVRS aliases into the PCI DMA alias quirks, we should alway come up with the same results as the existing code. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Cc: Joerg Roedel <joro@8bytes.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2014-04-05Merge tag 'iommu-updates-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuLinus Torvalds1-3/+8
Pull IOMMU upates from Joerg Roedel: "This time a few more updates queued up. - Rework VT-d code to support ACPI devices - Improvements for memory and PCI hotplug support in the VT-d driver - Device-tree support for OMAP IOMMU - Convert OMAP IOMMU to use devm_* interfaces - Fixed PASID support for AMD IOMMU - Other random cleanups and fixes for OMAP, ARM-SMMU and SHMOBILE IOMMU Most of the changes are in the VT-d driver because some rework was necessary for better hotplug and ACPI device support" * tag 'iommu-updates-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (75 commits) iommu/vt-d: Fix error handling in ANDD processing iommu/vt-d: returning free pointer in get_domain_for_dev() iommu/vt-d: Only call dmar_acpi_dev_scope_init() if DRHD units present iommu/vt-d: Check for NULL pointer in dmar_acpi_dev_scope_init() iommu/amd: Fix logic to determine and checking max PASID iommu/vt-d: Include ACPI devices in iommu=pt iommu/vt-d: Finally enable translation for non-PCI devices iommu/vt-d: Remove to_pci_dev() in intel_map_page() iommu/vt-d: Remove pdev from intel_iommu_attach_device() iommu/vt-d: Remove pdev from iommu_no_mapping() iommu/vt-d: Make domain_add_dev_info() take struct device iommu/vt-d: Make domain_remove_one_dev_info() take struct device iommu/vt-d: Rename 'hwdev' variables to 'dev' now that that's the norm iommu/vt-d: Remove some pointless to_pci_dev() calls iommu/vt-d: Make get_valid_domain_for_dev() take struct device iommu/vt-d: Make iommu_should_identity_map() take struct device iommu/vt-d: Handle RMRRs for non-PCI devices iommu/vt-d: Make get_domain_for_dev() take struct device iommu/vt-d: Make domain_context_mapp{ed,ing}() take struct device iommu/vt-d: Make device_to_iommu() cope with non-PCI devices ...
2014-03-24iommu/amd: Fix logic to determine and checking max PASIDSuravee Suthikulpanit1-3/+8
In reality, the spec can only support 16-bit PASID since INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16-bit PASID. So, we updated the PASID_MASK accordingly and invoke BUG_ON if the hardware is reporting PASmax more than 16-bit. Besides, max PASID is defined as ((2^(PASmax+1)) - 1). The current does not determine this correctly. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2014-02-19iommu/amd: Add include of <linux/irqreturn.h>Bjorn Helgaas1-0/+1
We currently include <linux/irqreturn.h> in <linux/pci.h>, but I'm about to remove that from linux/pci.h, so add explicit includes where needed. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-06-19perf/x86/amd: Add IOMMU Performance Counter resource managementSteven L Kinney1-3/+12
Add functionality to check the availability of the AMD IOMMU Performance Counters and export this functionality to other core drivers, such as in this case, a perf AMD IOMMU PMU. This feature is not bound to any specific AMD family/model other than the presence of the IOMMU with P-C enabled. The AMD IOMMU P-C support static counting only at this time. Signed-off-by: Steven Kinney <steven.kinney@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1370466709-3212-2-git-send-email-suravee.suthikulpanit@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-05-06Merge tag 'iommu-updates-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuLinus Torvalds1-0/+2
Pull IOMMU updates from Joerg Roedel: "The updates are mostly about the x86 IOMMUs this time. Exceptions are the groundwork for the PAMU IOMMU from Freescale (for a PPC platform) and an extension to the IOMMU group interface. On the x86 side this includes a workaround for VT-d to disable interrupt remapping on broken chipsets. On the AMD-Vi side the most important new feature is a kernel command-line interface to override broken information in IVRS ACPI tables and get interrupt remapping working this way. Besides that there are small fixes all over the place." * tag 'iommu-updates-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (24 commits) iommu/tegra: Fix printk formats for dma_addr_t iommu: Add a function to find an iommu group by id iommu/vt-d: Remove warning for HPET scope type iommu: Move swap_pci_ref function to drivers/iommu/pci.h. iommu/vt-d: Disable translation if already enabled iommu/amd: fix error return code in early_amd_iommu_init() iommu/AMD: Per-thread IOMMU Interrupt Handling iommu: Include linux/err.h iommu/amd: Workaround for ERBT1312 iommu/amd: Document ivrs_ioapic and ivrs_hpet parameters iommu/amd: Don't report firmware bugs with cmd-line ivrs overrides iommu/amd: Add ioapic and hpet ivrs override iommu/amd: Add early maps for ioapic and hpet iommu/amd: Extend IVRS special device data structure iommu/amd: Move add_special_device() to __init iommu: Fix compile warnings with forward declarations iommu/amd: Properly initialize irq-table lock iommu/amd: Use AMD specific data structure for irq remapping iommu/amd: Remove map_sg_no_iommu() iommu/vt-d: add quirk for broken interrupt remapping on 55XX chipsets ...
2013-04-19iommu/amd: Extend IVRS special device data structureJoerg Roedel1-0/+1
This patch extends the devid_map data structure to allow ioapic and hpet entries in ivrs to be overridden on the kernel command line. Reviewed-by: Shuah Khan <shuahkhan@gmail.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-04-02iommu/amd: Re-enable IOMMU event log interrupt after handling.Suravee Suthikulpanit1-0/+1
Current driver does not clear the IOMMU event log interrupt bit in the IOMMU status register after processing an interrupt. This causes the IOMMU hardware to generate event log interrupt only once. This has been observed in both IOMMU v1 and V2 hardware. This patch clears the bit by writing 1 to bit 1 of the IOMMU status register (MMIO Offset 2020h) Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-03-26iommu/amd: Remove calc_devid() and use PCI_DEVID() from PCIShuah Khan1-7/+0
Change to remove calc_devid() and use PCI_DEVID() from PCI instead. Signed-off-by: Shuah Khan <shuah.khan@hp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joerg Roedel <joro@8bytes.org>
2013-03-26iommu/amd: Remove local PCI_BUS() define and use PCI_BUS_NUM() from PCIShuah Khan1-3/+1
Change to remove local PCI_BUS() define and use the new PCI_BUS_NUM() interface from PCI. Signed-off-by: Shuah Khan <shuah.khan@hp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joerg Roedel <joro@8bytes.org>
2012-10-24iommu/amd: Properly account for virtual aliases in IOMMU groupsAlex Williamson1-0/+1
An alias doesn't always point to a physical device. When this happens we must first verify that the IOMMU group isn't rooted in a device above the alias. In this case the alias is effectively just another quirk for the devices aliased to it. Alternatively, the virtual alias itself may be the root of the IOMMU group. To support this, allow a group to be hosted on the alias dev_data for use by anything that might have the same alias. Signed-off-by: Alex williamson <alex.williamson@redhat.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-10-02Merge branches 'dma-debug', 'iommu/fixes', 'arm/tegra', 'arm/exynos', 'x86/amd', 'x86/vt-d' and 'x86/amd-irq-remapping' into nextJoerg Roedel1-2/+57
Conflicts: drivers/iommu/amd_iommu_init.c
2012-09-28iommu/amd: Add IRTE invalidation routineJoerg Roedel1-0/+3
Add routine to invalidate the IOMMU cache for interupt translations. Also include the IRTE caches when flushing all IOMMU caches. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-09-28iommu/amd: Allocate data structures to keep track of irq remapping tablesJoerg Roedel1-0/+9
To easily map device ids to interrupt remapping table entries a new lookup table is necessary. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-09-28iommu/amd: Add slab-cache for irq remapping tablesJoerg Roedel1-0/+9
The irq remapping tables for the AMD IOMMU need to be aligned on a 128 byte boundary. Create a seperate slab-cache to guarantee this alignment. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-09-28iommu/amd: Keep track of HPET and IOAPIC device idsJoerg Roedel1-0/+34
The IVRS ACPI table provides information about the IOAPICs and the HPETs available in the system and which PCI device ID they use in transactions. Save that information for later usage in interrupt remapping. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
2012-09-18iommu/amd: Fix some typosFrank Arnold1-2/+2
Fix some typos in comments and user-visible messages. No functional changes. Signed-off-by: Frank Arnold <frank.arnold@amd.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-07-17iommu/amd: Split out PCI related parts of IOMMU initializationJoerg Roedel1-2/+3
For interrupt remapping the relevant IOMMU initialization needs to run earlier at boot when the PCI subsystem is not yet initialized. To support that this patch splits the parts of IOMMU initialization which need PCI accesses out of the initial setup path so that this can be done later. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-07-17iommu/amd: Fix sparse warningsJoerg Roedel1-1/+7
A few sparse warnings fire in drivers/iommu/amd_iommu_init.c. Fix most of them with this patch. Also fix the sparse warnings in drivers/iommu/irq_remapping.c while at it. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-07-02iommu/amd: fix type bug in flush codeDan Carpenter1-1/+1
write_file_bool() modifies 32 bits of data, so "amd_iommu_unmap_flush" needs to be 32 bits as well or we'll corrupt memory. Fortunately it looks like the data is aligned with a gap after the declaration so this is harmless in production. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-06-04iommu/amd: Cache pdev pointer to root-bridgeJoerg Roedel1-0/+3
At some point pci_get_bus_and_slot started to enable interrupts. Since this function is used in the amd_iommu_resume path it will enable interrupts on resume which causes a warning. The fix will use a cached pointer to the root-bridge to re-enable the IOMMU in case the BIOS is broken. Cc: stable@vger.kernel.org Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-22iommu/amd: Set IOTLB invalidation timeoutJoerg Roedel1-0/+10
To protect the command buffer from hanging when a device does not respond to an IOTLB invalidation, set a timeout of 1s for outstanding IOTLB invalidations. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Add device errata handlingJoerg Roedel1-0/+1
Add infrastructure for errata-handling and handle two known erratas in the IOMMUv2 code. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Add function to get IOMMUv2 domain for pdevJoerg Roedel1-0/+4
The AMD IOMMUv2 driver needs to get the IOMMUv2 domain associated with a particular device. This patch adds a function to get this information. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Implement function to send PPR completionsJoerg Roedel1-0/+6
To send completions for PPR requests this patch adds a function which can be used by the IOMMUv2 driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Implement functions to manage GCR3 tableJoerg Roedel1-0/+1
This patch adds functions necessary to set and clear the GCR3 values associated with a particular PASID in an IOMMUv2 domain. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Implement IOMMUv2 TLB flushing routinesJoerg Roedel1-0/+1
The functions added with this patch allow to manage the IOMMU and the device TLBs for all devices in an IOMMUv2 domain. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Add support for IOMMUv2 domain modeJoerg Roedel1-0/+27
This patch adds support for protection domains that implement two-level paging for devices. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Implement notifier for PPR faultsJoerg Roedel1-1/+33
Add a notifer at which a module can attach to get informed about incoming PPR faults. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Put IOMMUv2 capable devices in pt_domainJoerg Roedel1-0/+4
If the device starts to use IOMMUv2 features the dma handles need to stay valid. The only sane way to do this is to use a identity mapping for the device and not translate it by the iommu. This is implemented with this patch. Since this lifts the device-isolation there is also a new kernel parameter which allows to disable that feature. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Add iommuv2 flag to struct amd_iommuJoerg Roedel1-0/+5
In mixed IOMMU setups this flag inidicates whether an IOMMU supports the v2 features or not. This patch also adds a global flag together with a function to query that flag from other code. The flag shows if at least one IOMMUv2 is in the system. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Enable GT mode when supported by IOMMUJoerg Roedel1-0/+1
This feature needs to be enabled before IOMMUv2 DTEs can be set up. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Setup PPR log when supported by IOMMUJoerg Roedel1-0/+14
Allocate and enable a log buffer for peripheral page faults when the IOMMU supports this feature. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Get the maximum number of PASIDs supportedJoerg Roedel1-0/+6
Read the number of PASIDs supported by each IOMMU in the system and take the smallest number as the maximum value supported by the IOMMU driver. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-12-12iommu/amd: Convert dev_table_entry to u64Joerg Roedel1-2/+2
Convert the contents of 'struct dev_table_entry' to u64 to allow updating the DTE wit 64bit writes as required by the spec. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-06-21Merge branches 'amd/transparent-bridge' and 'core'Joerg Roedel1-0/+585
Conflicts: arch/x86/include/asm/amd_iommu_types.h arch/x86/kernel/amd_iommu.c Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2011-06-21iommu/amd: Move missing parts to drivers/iommuJoerg Roedel1-0/+580
A few parts of the driver were missing in drivers/iommu. Move them there to have the complete driver in that directory. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
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