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path: root/drivers/irqchip/irq-gic-common.c (follow)
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2015-11-17irqchip/gic: Make sure all interrupts are deactivated at bootMarc Zyngier1-4/+9
When booting a GIC/GICv3 based system, we have no idea what state the firmware (or previous kernel in the case of kexec) has left the GIC, and some interrupts may still be active. In order to garantee that we have a clean state, make sure the active bits are cleared at init time. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Russell King <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/1447701208-18150-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-09-29irqchip/gicv3-its: Add HW revision detection and configurationRobert Richter1-0/+11
Some GIC revisions require an individual configuration to esp. add workarounds for HW bugs. This patch implements generic code to parse the hw revision provided by an IIDR register value and runs specific code if hw matches. A function is added that reads the IIDR registers for ITS (GITS_IIDR) and then goes through a list of init functions to be called for specific versions. Same could be done for GICV3 (GICD_IIDR), but there are no users yet for it. The patch is needed to implement workarounds for HW errata in Cavium's ThunderX GICV3 ITS. Signed-off-by: Robert Richter <rrichter@cavium.com> Reviewed-by: Marc Zygnier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1442869119-1814-5-git-send-email-rric@kernel.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-06-05irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKEDSudeep Holla1-17/+0
GIC requires to disable the interrupt before changing the trigger type. irqchip core provides IRQCHIP_SET_TYPE_MASKED flag and ensures that the interrupt is masked before calling chip.irq_set_type() if the irqchip sets the flag. This patch adds IRQCHIP_SET_TYPE_MASKED to GIC irqchip so that the core can manage disabling the interrupt while changing the trigger type. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1433501997-19205-1-git-send-email-sudeep.holla@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-01-26irqchip: gic: Allow interrupt level to be set for PPIsLiviu Dudau1-6/+12
During a recent cleanup of the arm64 DTs it has become clear that the handling of PPIs in xxxx_set_type() is incorrect. The ARM TRMs for GICv2 and later allow for "implementation defined" support for setting the edge or level type of the PPI interrupts and don't restrict the activation level of the signal. Current ARM implementations do restrict the PPI level type to IRQ_TYPE_LEVEL_LOW, but licensees of the IP can decide to shoot themselves in the foot at any time. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Acked-by: Marc Zyngier <Marc.Zyngier@arm.com> Cc: LAKML <linux-arm-kernel@lists.infradead.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Link: http://lkml.kernel.org/r/1421772779-25764-1-git-send-email-Liviu.Dudau@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-08-19irqchip: gic: Replace hex numbers with defines.Feng Kan1-6/+9
This is to cleanup some hex numbers used in the code and replace them with defines to make the code cleaner. Signed-off-by: Feng Kan <fkan@apm.com> Reviewed-by: Anup Patel <apatel@apm.com> Link: https://lkml.kernel.org/r/1406757419-18729-2-git-send-email-fkan@apm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-08irqchip: gic: Move some bits of GICv2 to a library-type fileMarc Zyngier1-0/+115
A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>