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path: root/drivers/irqchip/irq-stm32-exti.c (follow)
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2018-08-24Merge tag 'irqchip-4.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgentThomas Gleixner1-12/+13
Pull irqchip updates for 4.19, take #2 from Marc Zyngier: - bcm7038: compilation fix for !SMP - stm32: fix teardown on probe error - s3c24xx: fix compilation warning - renesas-irqc: r8a774a1 support - tango: chained irq setup simplification - gic-v3: allow wake-up sources
2018-08-13irqchip/stm32: Fix init error handlingDan Carpenter1-12/+13
If there are any errors in stm32_exti_host_init() then it leads to a NULL dereference in the callers. The function should clean up after itself. Fixes: f9fc1745501e ("irqchip/stm32: Add host and driver data structures") Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-07-19irqchip/stm32: Add exti0 translation for stm32mp1Ludovic Barre1-0/+1
This patch fixes a datasheet issue, in the draft version the "exti0" was not connected whereas is it. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-06-06irqchip/stm32: Fix non-SMP build warningArnd Bergmann1-3/+1
A CONFIG_SMP=n build emits a harmless compile-time warning: drivers/irqchip/irq-stm32-exti.c:495:12: error: 'stm32_exti_h_set_affinity' defined but not used [-Werror=unused-function] The #ifdef is inconsistent here, and it's better to use an IS_ENABLED() check that lets the compiler silently drop that function. Fixes: 927abfc4461e ("irqchip/stm32: Add stm32mp1 support with hierarchy domain") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Cc: Rob Herring <robh@kernel.org> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Link: https://lkml.kernel.org/r/20180605114347.1347128-1-arnd@arndb.de
2018-05-24irqchip/stm32: Add suspend/resume support for hierarchy domainLudovic Barre1-0/+49
This patch adds suspend/resume feature for exti hierarchy domain. -suspend function sets wake_active into imr of each banks -resume function restores the mask_cache interrupt into imr of each banks Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add stm32mp1 support with hierarchy domainLudovic Barre1-0/+322
Exti controller has been differently integrated on stm32mp1 SoC. A parent irq has only one external interrupt. A hierachy domain could be used. Handlers are call by parent, each parent interrupt could be masked and unmasked according to the needs. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Prepare common functionsLudovic Barre1-33/+58
This patch prepares functions which could be reused by next variant of stm32 exti controller. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add host and driver data structuresLudovic Barre1-48/+104
This patch adds host and driver data structures to support different stm32 exti controllers with variants. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add suspend supportLudovic Barre1-17/+52
This patch adds suspend feature. -Use default irq_set_wake function to store wakeup request. -Suspend function set wake_active into imr of each bank and save rising/falling trigger registers. -Resume function restore the mask_cache interrupt into imr of each bank and restore rising/falling trigger registers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add falling pending register supportLudovic Barre1-11/+36
This patch adds support of rising/falling pending registers. Falling pending register (fpr) is needed for next revision. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Checkpatch fixLudovic Barre1-2/+2
-WARNING: struct irq_domain_ops should normally be const -CHECK: Alignment should match open parenthesis Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Optimizes and cleans up stm32-exti irq_domainRadoslaw Pietrzyk1-13/+0
- In stm32_exti_alloc function, discards irq_domain_set_info with handle_simple_irq. This overwrite the setting defined while init of generic chips. Exti controller manages edge irq type. - Removes acking in chained irq handler as this is done by irq_chip itself inside handle_edge_irq - removes unneeded irq_domain_ops.xlate callback Acked-by: Ludovic Barre <ludovic.barre@st.com> Tested-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-01-29irqchip/stm32: Fix copyrightBenjamin Gaignard1-1/+2
Uniformize STMicroelectronics copyrights header and add SPDX identifier CC: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: jason@lakedaemon.net Cc: marc.zyngier@arm.com Cc: linux-arm-kernel@lists.infradead.org Link: https://lkml.kernel.org/r/20171130084500.23439-1-benjamin.gaignard@st.com
2017-11-07irqchip/stm32: Move the wakeup on interrupt maskLudovic Barre1-5/+5
Move irq_set_wake on interrupt mask, needed to wake up from low power mode as the event mask is not able to do so. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07irqchip/stm32: Fix initial valuesLudovic Barre1-0/+9
-After cold boot, imr default value depends on hardware configuration. -After hot reboot the registers must be cleared to avoid residue. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07irqchip/stm32: Add stm32h7 supportLudovic Barre1-0/+42
stm32h7 has up to 96 inputs (3 banks of 32 inputs max). Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-11-07irqchip/stm32: Add multi-bank managementLudovic Barre1-46/+103
-Prepare to manage multi-bank of external interrupts (N banks of 32 inputs). -Prepare to manage registers offsets by compatible (registers offsets could be different follow per stm32 platform). Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-08-23irqchip: Convert to using %pOF instead of full_nameRob Herring1-4/+4
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Lee Jones <lee@kernel.org> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-tegra@vger.kernel.org Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Alexandre Torgue <alexandre.torgue@st.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-09-21drivers/irqchip: Add STM32 external interrupts supportAlexandre TORGUE1-0/+201
The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, falling or both edges. Each line can also be masked independently. Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: arnd@arndb.de Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: bruherrera@gmail.com Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: lee.jones@linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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