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path: root/drivers/mmc/host/meson-gx-mmc.c (follow)
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2019-09-11mmc: Remove dev_err() usage after platform_get_irq()Stephen Boyd1-1/+0
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-07-11Merge tag 'mmc-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmcLinus Torvalds1-15/+55
Pull MMC updates from Ulf Hansson: "MMC core: - Let the dma map ops deal with bouncing and drop dma_max_pfn() from the dma-mapping interface for ARM - Convert the generic MMC DT doc to YAML schemas - Drop questionable support for powered-on re-init of SDIO cards at runtime resume and for SDIO HW reset - Prevent questionable re-init of powered-on removable SDIO cards at system resume - Cleanup and clarify some SDIO core code MMC host: - tmio: Make runtime PM enablement more flexible for variants - tmio/renesas_sdhi: Rename DT doc tmio_mmc.txt to renesas,sdhi.txt to clarify - sdhci-pci: Add support for Intel EHL - sdhci-pci-o2micro: Enable support for 8-bit bus - sdhci-msm: Prevent acquiring a mutex while holding a spin_lock - sdhci-of-esdhc: Improve clock management and tuning - sdhci_am654: Enable support for 4 and 8-bit bus on J721E - sdhci-sprd: Use pinctrl for a proper signal voltage switch - sdhci-sprd: Add support for HS400 enhanced strobe mode - sdhci-sprd: Enable PHY DLL and allow delay config to stabilize the clock - sdhci-sprd: Add support for optional gate clock - sunxi-mmc: Convert DT doc to YAML schemas - meson-gx: Add support for broken DRAM access for DMA MEMSTICK core: - Fixup error path of memstick_init()" * tag 'mmc-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (52 commits) mmc: sdhci_am654: Add dependency on MMC_SDHCI_AM654 mmc: alcor: remove a redundant greater or equal to zero comparison mmc: sdhci-msm: fix mutex while in spinlock mmc: sdhci_am654: Make some symbols static dma-mapping: remove dma_max_pfn mmc: core: let the dma map ops handle bouncing dt-binding: mmc: rename tmio_mmc.txt to renesas,sdhi.txt mmc: sdhci-sprd: Add pin control support for voltage switch dt-bindings: mmc: sprd: Add pinctrl support mmc: sdhci-sprd: Add start_signal_voltage_switch ops mmc: sdhci-pci: Add support for Intel EHL mmc: tmio: Use dma_max_mapping_size() instead of a workaround mmc: sdio: Drop unused in-parameter from mmc_sdio_init_card() mmc: sdio: Drop unused in-parameter to mmc_sdio_reinit_card() mmc: sdio: Don't re-initialize powered-on removable SDIO cards at resume mmc: sdio: Drop powered-on re-init at runtime resume and HW reset mmc: sdio: Move comment about re-initialization to mmc_sdio_reinit_card() mmc: sdio: Drop mmc_claim|release_host() in mmc_sdio_power_restore() mmc: sdio: Turn sdio_run_irqs() into static mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS ...
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 463Thomas Gleixner1-14/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of version 2 of the gnu general public license as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses the full gnu general public license is included in this distribution in the file called copying extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081202.258730266@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-10mmc: meson-gx: add dram-access-quirkNeil Armstrong1-15/+55
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access the data from DRAM, leading to a broken controller. But each MMC controller has 1,5KiB of SRAM after the registers, that can be used as bounce buffer to avoid direct DRAM access from the integrated DMAs (this SRAM may be used by the boot ROM when DRAM is not yet initialized). The quirk is to disable the chained descriptor for this controller, and use this SRAM memory zone as buffer for the bounce buffer fallback mode. The performance hit hasn't been evaluated, but the fix has been tested using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-06-10mmc: meson-gx-mmc: update with SPDX Licence identifierNeil Armstrong1-14/+1
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-28mmc: meson-gx: fix irq ackJerome Brunet1-3/+3
While cleaning the ISR of the meson-gx and acking only raised irqs, the ack of the irq was moved at the very last stage of the function. This was stable during the initial tests but it triggered issues with hs200, under specific loads (like booting android). Acking the irqs after calling the mmc_request_done() causes the problem. Moving the ack back to the original place solves the issue. Since the irq is edge triggered, it does not hurt to ack irq even earlier, so let's do it early in the ISR. Fixes: 9c5fdb07a28d ("mmc: meson-gx: ack only raised irq") Tested-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Brad Harper <bjharper@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: add signal resampling tuningJerome Brunet1-3/+70
Use signal resampling tuning for the UHS and HS200 modes. Instead of trying to get the *best* resampling setting with complex window calculation, we just stop on the first working setting. If the tuning setting later proves unstable, we will just continue the tuning where we left it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: remove Rx phase tuningJerome Brunet1-277/+13
This remove all the code related to phase settings. Using the Rx phase for tuning has not been reliable. We had several issues over the past months, on both v2 and v3 mmc chips After discussing the issue matter with Amlogic, They suggested to set a phase shift of 180 between Core and Tx and use signal resampling for the tuning. Since we won't be playing with the phase anymore, let's remove all the clock code related to it and set the appropriate value on init. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: avoid clock glitch when switching to DDR modesJerome Brunet1-30/+43
Activating DDR in the Amlogic mmc controller, among other things, will divide the output clock by 2. So by activating it with clock on, we are creating a glitch on the output. Instead, let's deal with DDR when the clock output is off, when setting the clock. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: disable HS400Jerome Brunet1-4/+7
At the moment, all our attempts to enable HS400 on Amlogic chipsets have been unsuccessful or unreliable. Until we can figure out how to enable this mode safely and reliably, let's force it off. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: correct irq flagJerome Brunet1-1/+1
There is no reason for another device to request the MMC irq. It should only be used the MMC device, so remove IRQ_SHARED and replace by IRQ_ONESHOT as we don't the irq to fire again until the irq thread is done Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: ack only raised irqJerome Brunet1-3/+3
This is merely a clean up. It makes sense to only ack raised irqs instead of acking everything all the time. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-05-06mmc: meson-gx: remove open coded read with timeoutJerome Brunet1-14/+4
There is already a function available to poll a register until a condition is met. Let's use it instead of open coding it. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-13mmc: meson-gx: fix interrupt nameMartin Blumenstingl1-1/+2
Commit bb364890323cca ("mmc: meson-gx: Free irq in release() callback") changed the _probe code to use request_threaded_irq() instead of devm_request_threaded_irq(). Unfortunately this removes a fallback for the interrupt name: devm_request_threaded_irq() uses the device name as fallback if the given IRQ name is NULL. request_threaded_irq() has no such fallback, thus /proc/interrupts shows "(null)" instead. Explicitly pass the dev_name() so we get the IRQ name shown in /proc/interrupts again. While here, also fix the indentation of the request_threaded_irq() parameter list. Fixes: bb364890323cca ("mmc: meson-gx: Free irq in release() callback") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-01-22mmc: meson-gx: enable signal re-sampling together with tuningAndreas Fenkart1-5/+9
card detection fails on "BeeLink Mini M8 SII" if enabled too early mmc1: error -110 whilst initialising MMC card Fixes: 71645e65729f ("mmc: meson-gx: add signal resampling") Signed-off-by: Andreas Fenkart <afenkart@gmail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-01-14mmc: meson-gx: Free irq in release() callbackRemi Pommarel1-7/+11
Because the irq was requested through device managed resources API (devm_request_threaded_irq()) it was freed after meson_mmc_remove() completion, thus after mmc_free_host() has reclaimed meson_host memory. As this irq is IRQF_SHARED, while using CONFIG_DEBUG_SHIRQ, its handler get called by free_irq(). So meson_mmc_irq() was called after the meson_host memory reclamation and was using invalid memory. We ended up with the following scenario: device_release_driver() meson_mmc_remove() mmc_free_host() /* Freeing host memory */ ... devres_release_all() devm_irq_release() __free_irq() meson_mmc_irq() /* Uses freed memory */ To avoid this, the irq is released in meson_mmc_remove() and in mseon_mmc_probe() error path before mmc_free_host() gets called. Reported-by: Elie Roudninski <xademax@gmail.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: add signal resamplingJerome Brunet1-1/+11
With some eMMC devices, there is still issues with the new phase settings. Enabling signal resampling seems to solve the problem for these. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: align default phase on soc vendor treeJerome Brunet1-7/+1
Align the default Core and Tx phase with the SoC vendor tree. Even if the Tx phase is different from what the documentation recommends, it seems to provide better results. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: remove useless lockJerome Brunet1-7/+0
The spinlock is only used within the irq handler so it does not seem very useful. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: make sure the descriptor is stopped on errorsJerome Brunet1-10/+63
On errors, if we don't stop the descriptor chain, it may continue to run and raise IRQ after we have called mmc_request_done(). This is bad because we won't be able to get cmd anymore and properly deal with the IRQ. This patch makes sure the descriptor chain is stopped before calling mmc_request_done() Fixes: 79ed05e329c3 ("mmc: meson-gx: add support for descriptor chain mode") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-21mmc: meson-gx: add device resetJerome Brunet1-0/+9
Trigger the reset line of the mmc controller while probing, if available. The reset should be optional for now, at least until all related DT nodes have the reset property. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-05-02mmc: meson: update doc to support Meson-AXG platformNan Li1-1/+1
Explicitly update the docomentation to support the Meson-AXG platform. Signed-off-by: Nan Li <nan.li@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com>
2018-05-02mmc: meson-axg: add support for the Meson-AXG platformNan Li1-10/+51
Introduce the compatible data to cover the register offset & mask change of the eMMC controller in Amlogic's Meson-AXG SoC. Signed-off-by: Nan Li <nan.li@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com>
2018-02-14Revert "mmc: meson-gx: include tx phase in the tuning process"Jerome Brunet1-18/+1
This reverts commit 0a44697627d17a66d7dc98f17aeca07ca79c5c20. This commit was initially intended to fix problems with hs200 and hs400 on some boards, mainly the odroid-c2. The OC2 (Rev 0.2) I have performs well in this modes, so I could not confirm these issues. We've had several reports about the issues being still present on (some) OC2, so apparently, this change does not do what it was supposed to do. Maybe the eMMC signal quality is on the edge on the board. This may explain the variability we see in term of stability, but this is just a guess. Lowering the max_frequency to 100Mhz seems to do trick for those affected by the issue Worse, the commit created new issues (CRC errors and hangs) on other boards, such as the kvim 1 and 2, the p200 or the libretech-cc. According to amlogic, the Tx phase should not be tuned and left in its default configuration, so it is best to just revert the commit. Fixes: 0a44697627d1 ("mmc: meson-gx: include tx phase in the tuning process") Cc: <stable@vger.kernel.org> # 4.14+ Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-02-05mmc: meson-gx-mmc: Explicitly include pinctr/consumer.hThierry Reding1-0/+1
The Meson GX MMC driver fails to build after commit 23c35f48f5fb ("pinctrl: remove include file from <linux/device.h>") because it relies on the pinctrl/consumer.h being pulled in by the device.h header implicitly. Include the header explicitly to avoid the build failure. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-12-15mmc: meson-gx-mmc: Fix platform_get_irq's error checkingArvind Yadav1-1/+1
The platform_get_irq() function returns negative if an error occurs. zero or positive number on success. platform_get_irq() error checking for zero is not correct. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-30mmc: meson-gx-mmc: catch all errors when getting regulatorsWolfram Sang1-1/+1
Bail out everytime when mmc_regulator_get_supply() returns an errno, not only when probing gets deferred. This is currently a no-op, because this function only returns -EPROBE_DEFER or 0 right now. But if it will throw another error somewhen, it will be for a reason. (This still doesn't change that getting regulators is optional, so 0 can still mean no regulators found). So, let us a) be future proof and b) have driver code which is easier to understand. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: include tx phase in the tuning processJerome Brunet1-1/+18
It has been reported that some platforms (odroid-c2) may require a different tx phase setting to operate at high speed (hs200 and hs400) To improve the situation, this patch includes tx phase in the tuning process. Fixes: d341ca88eead ("mmc: meson-gx: rework tuning function") Reported-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: fix rx phase resetJerome Brunet1-2/+4
Resetting the phase when POWER_ON is set the set_ios() call means that the phase is reset almost every time the set_ios() is called, while the expected behavior was to reset the phase on a power cycle. This had gone unnoticed until now because in all mode (except hs400) the tuning is done after the last to set_ios(). In such case, the tuning result is used anyway. In HS400, there are a few calls to set_ios() after the tuning is done, overwriting the tuning result. Resetting the phase on POWER_UP instead of POWER_ON solve the problem. Fixes: d341ca88eead ("mmc: meson-gx: rework tuning function") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-10-04mmc: meson-gx: make sure the clock is rounded downJerome Brunet1-2/+1
Using CLK_DIVIDER_ROUND_CLOSEST is unsafe as the mmc clock could be rounded to a rate higher the specified rate. Removing this flag ensure that, if the rate needs to be rounded, it will be rounded down. Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-31mmc: meson-gx: fix __ffsdi2 undefined on arm32Jerome Brunet1-7/+7
Using __bf_shf does not compile on arm 32 architecture. This has gone unnoticed till now cause the driver is only used on arm64. In addition, __bf_shf was already used in the driver without any issue. It was used on a constant value, so the call was probably optimized away. Replace __bf_shf by __ffs fixes the problem Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework tuning functionJerome Brunet1-50/+111
Rework tuning function of the rx phase. Now that the phase can be more precisely set using CCF, test more phase setting and find the largest working window. Then the tuning selected is the one at the center of the window. This rework allows to use new modes, such as UHS SDR50 Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: change default tx phaseJerome Brunet1-1/+7
Initial default tx phase was set to 0 while the datasheet recommends 270. Some cards fails to initialize with this setting and eMMC mode DDR52 does not work. Changing this setting to 270 fixes these issues, without any regression so far Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: implement voltage switch callbackJerome Brunet1-0/+22
Implement voltage switch callback (shamelessly copied from sunxi mmc driver). This allow, with the appropriate tuning function, to use SD ultra high speed modes. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: use CCF to handle the clock phasesJerome Brunet1-41/+176
Several phases can be controlled on the meson-gx controller, the core, tx and rx clock phase. The tx and rx uses delays to allow more fine grained setting of the phase. To properly compute the phase using delays, accessing the clock rate is necessary. Instead of ad-hoc functions, use the common clock framework to set the clock phases (and access the clock rate while doing it). Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: implement card_busy callbackJerome Brunet1-0/+13
Implement the card_busy callback to be able to verify that the card is done dealing with voltage switch, when the support is added later on. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: simplify interrupt handlerJerome Brunet1-54/+39
No functional change, just improve interrupt handler readability Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: work around clk-stop issueJerome Brunet1-6/+68
It seems that the mmc clock is also used and required, somehow, by the controller itself. It is shown during init, when writing to CFG while the divider is set to 0 will crash the SoC. During a voltage switch, the controller may crash and the card may then fail to exit busy state if the clock is stopped. To avoid this, it is best to keep the clock running for the controller, except during rate change. However, we still need to be able to gate the clock out of the SoC. Let's use the pinmux for this, and fallback to gpio mode (pulled-down) when we need to gate the clock Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: fix dual data rate mode frequenciesJerome Brunet1-12/+29
In DDR modes, meson mmc controller requires an input rate twice as fast as the output rate Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework clock init functionJerome Brunet1-48/+46
Thanks to devm, carrying the clock structure around after init is not necessary. Rework the function to remove these from the controller host data. Finally, set initial mmc clock rate before enabling it, simplifying the exit condition. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework clk_set functionJerome Brunet1-21/+9
Clean-up clk_set function to prepare the next changes (DDR and clk-stop) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: rework set_ios functionJerome Brunet1-13/+9
Remove conditional write of cfg register. Warn if set_clk fails for some reason. Consistently use host->dev instead of mixing with mmc_dev(mmc) Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: cfg init overwrite valuesJerome Brunet1-10/+4
cfg init function overwrite values set in the clk init function Remove the cfg pokes from the clk init. Actually, trying to use the CLK_AUTO, like initially tried in clk_init, would break the card initialization Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: initialize sane clk default before clock registerJerome Brunet1-10/+9
On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary. The change this fixed is: "mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag". Reported-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: clean up some constantsJerome Brunet1-3/+1
Remove unused clock rate defines. These should not be defined but requested from the clock framework. Also correct typo on the DELAY register Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flagJerome Brunet1-1/+1
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: meson-gx: fix mux mask definitionJerome Brunet1-1/+1
CCF generic mux will shift the mask using the value defined in shift Define the mask accordingly Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-06-12mmc: meson-gx: work around broken SDIO with certain WiFi chipsHeiner Kallweit1-0/+9
There have been reports about SDIO failing with certain WiFi chips in descriptor chain mode. SD / eMMC are working fine. So let's fall back to bounce buffer mode for command SD_IO_RW_EXTENDED. This was reported to fix the error. Fixes: 79ed05e329c3 "mmc: meson-gx: add support for descriptor chain mode" Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: meson-gx: add support for descriptor chain modeHeiner Kallweit1-16/+156
So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: meson-gx: add basic tuning for rx clock phaseHeiner Kallweit1-0/+49
This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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