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path: root/drivers/mmc/host/sdhci-esdhc.h (follow)
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2018-12-17mmc: sdhci-of-esdhc: workaround for unreliable pulse width detectionYangbo Lu1-0/+4
This was a SoC issue on LX2160A Rev1.0. eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] must be set to 0 to get 4 delay cells in the pulse width detection logic for eMMC HS400 mode. Otherwise it would cause unexpected HS400 issue. This patch is to clear this bit always for affected SoC when reset for all, since this bit doesn't affect other speed modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci-of-esdhc: add hs400 mode supportYangbo Lu1-0/+20
1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: sdhci-of-esdhc: add erratum A008171 supportYinbo Zhu1-0/+1
In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-08-30mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessingyangbo lu1-0/+3
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-06-20mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDRBenoît Thébaudeau1-0/+1
The eSDHC can only DMA from 32-bit-aligned addresses. This fixes the following test cases of mmc_test: 11: Badly aligned write 12: Badly aligned read 13: Badly aligned multi-block write 14: Badly aligned multi-block read Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add tuning supportyangbo lu1-0/+5
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add support for signal voltage switchyangbo lu1-0/+1
eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-04-24mmc: sdhci-of-esdhc: add peripheral clock supportyangbo lu1-0/+1
eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-02-13mmc: sdhci-of-esdhc: avoid clock glitch when frequency is changingyangbo lu1-0/+5
The eSDHC_PRSSTAT[SDSTB] bit indicates whether the internal card clock is stable. This bit is for the host driver to poll clock status when changing the clock frequency. It is recommended to clear eSDHC_SYSCTL[SDCLKEN] to remove glitch on the card clock when the frequency is changing. This patch is to disable SDCLKEN bit before changing frequency and enable it after SDSTB bit is set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-02-13mmc: sdhci-esdhc: clean up register definitionsyangbo lu1-19/+20
The eSDHC register definitions in header file were messy and confusing. This patch is to clean up these definitions. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-26mmc: sdhci-of-esdhc: support both BE and LE host controlleryangbo lu1-0/+2
To support little endian eSDHC controller, we redefine both BE and LE IO accessors. In the new accessors, use ioread*/iowrite* instead of in_be32/out_be32 and will select accessors according to endian mode in probe function. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-08-17mmc: sdhci-esdhc: add default quirk SDHCI_QUIRK_NO_HISPD_BITYangbo Lu1-1/+2
eSDHC supports high speed mode, but has no enabling bit for it. Add this quirk to avoid writing to eSDHC_PROCTL[DTW] by mistake. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-07-24mmc: sdhci-esdhc: Make 8BIT bus workJoakim Tjernlund1-1/+1
Support for 8BIT bus with was added some time ago to sdhci-esdhc but then missed to remove the 8BIT from the reserved bit mask which made 8BIT non functional. Fixes: 66b50a00992d ("mmc: esdhc: Add support for 8-bit bus width and..") Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2014-05-22mmc: sdhci: convert sdhci_set_clock() into a library functionRussell King1-1/+0
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
2014-05-22mmc: sdhci: move FSL ESDHC reset handling quirk into esdhc codeRussell King1-2/+1
The Freescale esdhc driver is the only driver which needs the interrupt registers restored after a reset. Move this quirk to be part of the ESDHC driver implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
2013-09-26mmc: sdhci-esdhc: move common esdhc_set_clock to platform driverDong Aisheng1-37/+0
We need a lot of imx6 specific things into common esdhc_set_clock for support SD3.0 and eMMC DDR mode which is not needed for power pc platforms, so esdhc_set_clock seems not so common anymore. Instead of keeping add platform specfics things into this common API, we choose to move that code into platform driver itself to handle. This can also exclude the dependency between imx and power pc on this headfile and is easy for maintain in the future. Signed-off-by: Dong Aisheng <b29396@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-07-05mmc: esdhc: Add support for 8-bit bus width and non-removable cardOded Gabbay1-0/+7
This patch adds support of connecting an MMC media using an 8-bit bus width connection to Freescale's P2020 H/W SDHC controller. During the probe function, the generic function mmc_of_parse is called to detect whether the controller is configured with 8-bit bus width. Also, the generic function detects if the non-removable property is set in the device tree. The function esdhc_pltfm_bus_width was added because the bus width configuration is platform specific. Signed-off-by: Oded Gabbay <ogabbay@advaoptical.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2013-06-27mmc: sdhci-esdhc: calculate sdclk divider from controller clockLucas Stach1-4/+5
The SDCLK is divided down from the host controller clock. Host controller clock may be different from the maximum SDCLK, so get it from the platform, instead of just using the max SDCLK. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-09-04mmc: sdhci-esdhc: break out early if clock is 0Shawn Guo1-3/+3
Since commit 30832ab56 ("mmc: sdhci: Always pass clock request value zero to set_clock host op") was merged, esdhc_set_clock starts hitting "if (clock == 0)" where ESDHC_SYSTEM_CONTROL has been operated. This causes SDHCI card-detection function being broken. Fix the regression by moving "if (clock == 0)" above ESDHC_SYSTEM_CONTROL operation. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
2012-01-11mmc: sdhci-esdhc: Change delay after setting clock from 100ms to 1msTony Lin1-1/+1
1ms is enough for hardware to change the clock to stable. 100ms is too long in the tasklet. Signed-off-by: Tony Lin <tony.lin@freescale.com> CC: Xiaobo Xie <X.Xie@freescale.com> CC: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-03-25mmc: sdhci-esdhc: remove SDHCI_QUIRK_NO_CARD_NO_RESET from esdhcRichard Zhu1-2/+1
sdhci-esdhc-imx does not need SDHCI_QUIRK_NO_CARD_NO_RESET. Make it OF-specific. Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com> Tested-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
2011-03-17mmc: sdhci-esdhc: broken card detection is not a default quirkWolfram Sang1-1/+0
It can be worked around using a GPIO which will be done for i.MX later. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Anton Vorontsov <cbouatmailru@gmail.com> Tested-by: Marc Reilly <marc@cpdesign.com.au> Tested-by: Eric Benard <eric@eukrea.com> Signed-off-by: Chris Ball <cjb@laptop.org>
2010-10-23mmc: sdhci-of-esdhc: factor out common stuffWolfram Sang1-0/+83
Put everything which can be shared between the OF and platform version of this driver into a local .h file. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Tested-by: Eric Bénard <eric@eukrea.com> [cjb: fix compile error: sdhci-esdhc.c->sdhci-esdhc.h] Signed-off-by: Chris Ball <cjb@laptop.org>
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