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2020-11-17mmc: host: Kconfig: fix spelling mistake "hardare" -> "hardware"Colin Ian King1-1/+1
There is a spelling mistake in the Kconfig file. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201114120819.416311-1-colin.king@canonical.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-17mmc: sdhci-msm: detect if tassadar_dll is used by using core versionDmitry Baryshkov1-10/+3
Detect if tassadar_dll is required by using core version rather than just specifying it in the sdhci_msm_variant_info. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/20201112173636.360186-1-dmitry.baryshkov@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-17mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllersAdrian Hunter1-2/+11
A UHS setting of SDR25 can give better results for High Speed mode. This is because there is no setting corresponding to high speed. Currently SDHCI sets no value, which means zero which is also the setting for SDR12. There was an attempt to change this in sdhci.c but it caused problems for some drivers, so it was reverted and the change was made to sdhci-brcmstb in commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS mode"). Several other drivers also do this. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v5.4+ Link: https://lore.kernel.org/r/20201112133656.20317-1-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-17mmc: mediatek: fix mem leak in msdc_drv_probeZheng Liang1-2/+4
It should use mmc_free_host to free mem in error patch of msdc_drv_probe. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zheng Liang <zhengliang6@huawei.com> Reviewed-by: Chaotian Jing <chaotian.jing@mediatek.com> Link: https://lore.kernel.org/r/20201112092530.32446-1-zhengliang6@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: sort includesWolfram Sang1-9/+9
Better prevent double includes. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201111100244.15823-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: don't hardcode SDIF valuesWolfram Sang2-3/+5
Use a macro to name the hardcoded values. Also, move the SDIF register definition into the SDHI driver because this is an SDHI extension. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201111100244.15823-3-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: improve HOST_MODE usageWolfram Sang1-8/+16
HOST_MODE should have a CTL_ prefix, too. This makes the code more readable because we immediately know what it is. Also, remove the hardcoded values with something readable, too. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201111100244.15823-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: remove superfluous SCLKENWolfram Sang1-3/+0
All previously called functions handle SCLKEN on their own, no need to enable it again in sdhi_reset(). Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110162151.37622-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: merge the SCC reset functionsWolfram Sang1-10/+4
There is no user of renesas_sdhi_reset_scc() anymore, only renesas_sdhi_disable_scc() so merge these functions into one. I guess the seperation was cruft anyhow. The BSP doesn't have it anymore and I can't recall the reason we had it. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110162151.37622-3-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: clear TAPEN when resetting, tooWolfram Sang1-1/+1
We want to clear TAPEN in a software reset, too, to have a completely known state. Especially when we doing the initial reset during boot to clear previous firmware states. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110162151.37622-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: simplify reset routine a littleWolfram Sang1-3/+2
The 'reset' pointer is only populated for Gen2+. So, we don't need to check for that flag inside the routine. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110142058.36393-5-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: populate SCC pointer at the proper placeWolfram Sang1-5/+2
The SCC pointer is currently filled whenever the SoC is Gen2+. This is wrong because there is a Gen2-variant without SCC (SDHI_VER_GEN2_SDR50). We have been lucky because the writes to unintended registers have not caused problems so far. But further refactoring work exposed the problem. So, move the pointer initialization to the place where we know that the SDHI instance supports tuning. And also populate the 'reset' pointer unconditionally to make sure the interrupt enable register is always properly set for Gen2+. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110142058.36393-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: probe into TMIO after SCC parameters have been setupWolfram Sang1-4/+4
Setting up the SCC parameters does not need a probed TMIO device. But in the near future, probing the TMIO device needs the SCC parameters setup. So, fix the ordering. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110142058.36393-3-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: renesas_sdhi: only reset SCC when its pointer is populatedWolfram Sang1-8/+10
Only re-initialize SCC and tuning when an SCC was found during probe(). This is currently a noop because all R-Car Gen2+ are considered to have an SCC. But this will change in a later patch, so we need this preparation. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201110142058.36393-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: owl-mmc: use true and false for bool variablesZou Wei1-2/+2
Fix coccicheck warnings: ./owl-mmc.c:524:2-18: WARNING: Assignment of 0/1 to bool variable ./owl-mmc.c:528:2-18: WARNING: Assignment of 0/1 to bool variable Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1604888706-63429-1-git-send-email-zou_wei@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: sdhci-pic32: Make pic32_sdhci_probe_platform() voidKaixu Xia1-9/+2
pic32_sdhci_probe_platform() always returned 0, so there's no reason for a return value. In addition, pic32_sdhci_probe() checked the return value for possible error which is unnecessary. Convert pic32_sdhci_probe_platform() to a void function and remove the return value check. Fix the following Coccinelle warning: ./drivers/mmc/host/sdhci-pic32.c:127:5-8: Unneeded variable: "ret". Return "0" on line 137 Reported-by: Tosk Robot <tencent_os_robot@tencent.com> Signed-off-by: Kaixu Xia <kaixuxia@tencent.com> Link: https://lore.kernel.org/r/1604847648-13036-1-git-send-email-kaixuxia@tencent.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: dw_mmc: replace spin_lock_irqsave by spin_lock in hard IRQTian Tao1-9/+8
The code has been in a irq-disabled context since it is hard IRQ. There is no necessity to do it again. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1604627813-59785-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: meson-gx: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski1-1/+1
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it is not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES): drivers/mmc/host/meson-gx-mmc.c:1252:34: warning: ‘meson_mmc_of_match’ defined but not used [-Wunused-const-variable=] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201103163046.14336-1-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: rtsx: Add test mode for RTS5261Rui Feng1-3/+16
This patch add test mode for RTS5261. If test mode is set, reader will switch to SD Express mode mandatorily, and this mode is used by factory testing only. Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/1604397269-2780-1-git-send-email-rui_feng@realsil.com.cn Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: mediatek: add HS400 enhanced strobe supportWenbin Mei1-0/+40
Add support for HS400ES mode to MediaTek MMC Card Driver. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Link: https://lore.kernel.org/r/20201102092822.5301-2-wenbin.mei@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: owl-mmc: replace spin_lock_irqsave by spin_lock in hard IRQTian Tao1-3/+2
The code has been in a irq-disabled context since it is hard IRQ. There is no necessity to do it again. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1604278337-55624-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: meson-mx-sdio: replace spin_lock_irqsave by spin_lock in hard IRQTian Tao1-3/+2
The code has been in a irq-disabled context since it is hard IRQ. There is no necessity to do it again. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/1604375323-33556-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: moxart: replace spin_lock_irqsave by spin_lock in hard IRQTian Tao1-3/+2
The code has been in a irq-disabled context since it is hard IRQ. There is no necessity to do it again. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1604021319-31338-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: davinci: remove unneeded semicolonTom Rix1-1/+1
A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20201031152708.2146690-1-trix@redhat.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: rtsx_pci: Add SD Express mode support for RTS5261Rui Feng1-0/+58
RTS5261 support SD mode and PCIe/NVMe mode. The workflow is as follows. 1.RTS5261 work in SD mode and set MMC_CAPS2_SD_EXP flag. 2.If card is plugged in, Host send CMD8 to ask card's PCIe availability. 3.If the card has PCIe availability and WP is not set, init_sd_express() will be invoked, RTS5261 switch to PCIe/NVMe mode. 4.Mmc driver handover it to NVMe driver. 5.If card is unplugged, RTS5261 will switch to SD mode. Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Link: https://lore.kernel.org/r/1603936703-3403-1-git-send-email-rui_feng@realsil.com.cn Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: mediatek: Replace spin_lock_irqsave by spin_lock in hard IRQTian Tao1-3/+2
The code has been in a irq-disabled context since it is hard IRQ. Therefore there no need to do it again. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1603068193-44688-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: mediatek: Add subsys clock control for MT8192 msdcWenbin Mei1-18/+56
MT8192 msdc is an independent sub system, we need control more bus clocks for it. Add support for the additional subsys clocks to allow it to be configured appropriately. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Link: https://lore.kernel.org/r/20201014030846.12428-5-wenbin.mei@mediatek.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: sdhci-acpi: AMDI0040: Allow changing HS200/HS400 driver strengthRaul E Rangel1-3/+35
This change will allow platform designers better control over signal integrity by allowing them to tune the HS200 and HS400 driver strengths. The driver strength was previously hard coded to A to solve boot problems with certain platforms. This driver strength does not universally apply to all platforms so we need a knob to adjust it. All older platforms currently have the SDR104 preset hard coded to A in the firmware. This means that switching from the hard coded value in the kernel to reading the SDR104 preset is a no-op for these platforms. Newer platforms will have properly set presets. So this change will support both new and old platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Victor Ding <victording@google.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20201027084612.528301-1-victording@google.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: sunxi: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski1-1/+2
The driver can match only via DT table so it should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it is not relevant for sunxi). This fixes compile warning: drivers/mmc/host/sunxi-mmc.c:1181:34: warning: ‘sunxi_mmc_of_match’ defined but not used [-Wunused-const-variable=] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20201026153810.89512-3-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: s3cmci: enable compile testingKrzysztof Kozlowski1-2/+2
The driver can be compile tested to increase build coverage. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201026153810.89512-2-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-16mmc: s3cmci: include GPIO descriptor consumer headerKrzysztof Kozlowski1-1/+1
The driver uses GPIO Descriptor Consumer Interface so include proper header to fix compile test errors like: drivers/mmc/host/s3cmci.c: In function ‘s3cmci_check_sdio_irq’: drivers/mmc/host/s3cmci.c:304:7: error: implicit declaration of function ‘gpiod_get_value’; did you mean ‘gpio_get_value’? [-Werror=implicit-function-declaration] drivers/mmc/host/s3cmci.c: In function ‘s3cmci_probe_pdata’: drivers/mmc/host/s3cmci.c:1451:19: error: implicit declaration of function ‘devm_gpiod_get_index’ [-Werror=implicit-function-declaration] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201026153810.89512-1-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-10Revert "mmc: renesas_sdhi: workaround a regression when reinserting SD cards"Wolfram Sang1-13/+0
This reverts commit db1af1e9712920f47b5dc6a995fca3eec05ea85e. It was only a workaround to hide a regression. We now have proper fixes. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201106072549.1495-4-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-10mmc: tmio: bring tuning HW to a sane state with MMC_POWER_OFFWolfram Sang1-0/+3
When powering off a card, we need to disable the tuning HW (like SCC for the Renesas SDHI) to get to a sane state and allow for re-tuning new cards. This was hidden before because we wrongly did that in hw_reset() before which was an unintended use of hw_reset(). Now that we corrected the use of hw_reset() meanwhile, we revealed this shortcoming and need to fix it properly by explicitly calling the downgrade callback. Fixes: 6e7d4de10890 ("mmc: renesas_sdhi: move wrong 'hw_reset' to 'reset'") Suggested-by: Takeshi Saito <takeshi.saito.xv@renesas.com> Reviewed-by: Takeshi Saito <takeshi.saito.xv@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201106072549.1495-3-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-10mmc: tmio: when resetting, reset DMA controller, tooWolfram Sang1-2/+2
When applying a revert, the assumption that DMA only needs to be cleared in specific cases was wrong. We want to reset the DMA controller every time the rest of the HW gets reset, too. Fixes: 34e3211e5492 ("Revert "mmc: tmio: fix reset operation"") Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201106072549.1495-2-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-10mmc: sdhci-of-esdhc: Handle pulse width detection erratum for more SoCsYangbo Lu1-0/+2
Apply erratum workaround of unreliable pulse width detection to more affected platforms (LX2160A Rev2.0 and LS1028A Rev1.0). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Fixes: 48e304cc1970 ("mmc: sdhci-of-esdhc: workaround for unreliable pulse width detection") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201110071314.3868-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-10mmc: renesas_sdhi_core: Add missing tmio_mmc_host_free() at removeYoshihiro Shimoda1-0/+1
The commit 94b110aff867 ("mmc: tmio: add tmio_mmc_host_alloc/free()") added tmio_mmc_host_free(), but missed the function calling in the sh_mobile_sdhi_remove() at that time. So, fix it. Otherwise, we cannot rebind the sdhi/mmc devices when we use aliases of mmc. Fixes: 94b110aff867 ("mmc: tmio: add tmio_mmc_host_alloc/free()") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1604654730-29914-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-30Merge tag 'mmc-v5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmcLinus Torvalds3-2/+34
Pull MMC host fixes from Ulf Hansson: - sdhci: Fix performance regression with auto CMD auto select - sdhci-of-esdhc: Fix initialization for eMMC HS400 mode - sdhci-of-esdhc: Fix timeout bug for tuning commands * tag 'mmc-v5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: sdhci-of-esdhc: make sure delay chain locked for HS400 mmc: sdhci-of-esdhc: set timeout to max before tuning mmc: sdhci: Use Auto CMD Auto Select only when v4_mode is true
2020-10-28mmc: sdhci-of-esdhc: make sure delay chain locked for HS400Yangbo Lu2-0/+19
For eMMC HS400 mode initialization, the DLL reset is a required step if DLL is enabled to use previously, like in bootloader. This step has not been documented in reference manual, but the RM will be fixed sooner or later. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20201020081116.20918-1-yangbo.lu@nxp.com Fixes: 54e08d9a95ca ("mmc: sdhci-of-esdhc: add hs400 mode support") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-24Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-56/+18
Pull ARM SoC platform updates from Olof Johansson: "SoC changes, a substantial part of this is cleanup of some of the older platforms that used to have a bunch of board files. In particular: - Remove non-DT i.MX platforms that haven't seen activity in years, it's time to remove them. - A bunch of cleanup and removal of platform data for TI/OMAP platforms, moving over to genpd for power/reset control (yay!) - Major cleanup of Samsung S3C24xx and S3C64xx platforms, moving them closer to multiplatform support (not quite there yet, but getting close). There are a few other changes too, smaller fixlets, etc. For new platform support, the primary ones are: - New SoC: Hisilicon SD5203, ARM926EJ-S platform. - Cpufreq support for i.MX7ULP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (121 commits) ARM: mstar: Select MStar intc ARM: stm32: Replace HTTP links with HTTPS ones ARM: debug: add UART early console support for SD5203 ARM: hisi: add support for SD5203 SoC ARM: omap3: enable off mode automatically clk: imx: imx35: Remove mx35_clocks_init() clk: imx: imx31: Remove mx31_clocks_init() clk: imx: imx27: Remove mx27_clocks_init() ARM: imx: Remove unused definitions ARM: imx35: Retrieve the IIM base address from devicetree ARM: imx3: Retrieve the AVIC base address from devicetree ARM: imx3: Retrieve the CCM base address from devicetree ARM: imx31: Retrieve the IIM base address from devicetree ARM: imx27: Retrieve the CCM base address from devicetree ARM: imx27: Retrieve the SYSCTRL base address from devicetree ARM: s3c64xx: bring back notes from removed debug-macro.S ARM: s3c24xx: fix Wunused-variable warning on !MMU ARM: samsung: fix PM debug build with DEBUG_LL but !MMU MAINTAINERS: mark linux-samsung-soc list non-moderated ARM: imx: Remove remnant board file support pieces ...
2020-10-23mmc: sdhci-of-esdhc: set timeout to max before tuningMichael Walle1-0/+11
On rare occations there is the following error: mmc0: Tuning timeout, falling back to fixed sampling clock There are SD cards which takes a significant longer time to reply to the first CMD19 command. The eSDHC takes the data timeout value into account during the tuning period. The SDHCI core doesn't explicitly set this timeout for the tuning procedure. Thus on the slow cards, there might be a spurious "Buffer Read Ready" interrupt, which in turn triggers a wrong sequence of events. In the end this will lead to an unsuccessful tuning procedure and to the above error. To workaround this, set the timeout to the maximum value (which is the best we can do) and the SDHCI core will take care of the proper timeout handling. Fixes: ba49cbd0936e ("mmc: sdhci-of-esdhc: add tuning support") Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201022222337.19857-1-michael@walle.cc Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-15mmc: sdhci: Use Auto CMD Auto Select only when v4_mode is trueJisheng Zhang1-2/+4
sdhci-of-dwcmshc meets an eMMC read performance regression with below command after commit 427b6514d095 ("mmc: sdhci: Add Auto CMD Auto Select support"): dd if=/dev/mmcblk0 of=/dev/null bs=8192 count=100000 Before the commit, the above command gives 120MB/s After the commit, the above command gives 51.3 MB/s So it looks like sdhci-of-dwcmshc expects Version 4 Mode for Auto CMD Auto Select. Fix the performance degradation by ensuring v4_mode is true to use Auto CMD Auto Select. Fixes: 427b6514d095 ("mmc: sdhci: Add Auto CMD Auto Select support") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201015174115.4cf2c19a@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-09mmc: sdhci_am654: Fix module autoloadFaiz Abbas1-0/+1
Add a MODULE_DEVICE_TABLE() entry so that the driver is autoloaded when built as a module. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20201008100129.13917-1-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-08mmc: renesas_sdhi: workaround a regression when reinserting SD cardsWolfram Sang1-0/+13
After the conversions of the reset routines, re-inserting SD cards didn't work anymore. Apply this temporary workaround to have working SD cards during the merge window. The issue will be fixed properly until the final release. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201008092533.76588-1-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-07mmc: sdhci-pci-gli: Add CQHCI Support for GL9763EBen Chuang1-2/+148
Add CQHCI initialization and implement CQHCI operations for GL9763E. Use bit19 of the register (0x888) to decide whether to disable command queuing. If the bit is set, the command queuing will be disabled. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20201005105509.11343-1-ben.chuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-05mmc: sdhci-acpi: AMDI0040: Set SDHCI_QUIRK2_PRESET_VALUE_BROKENRaul E Rangel1-0/+37
This change fixes HS400 tuning for devices with invalid presets. SDHCI presets are not currently used for eMMC HS/HS200/HS400, but are used for DDR52. The HS400 retuning sequence is: HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400 This means that when HS400 tuning happens, we transition through DDR52 for a very brief period. This causes presets to be enabled unintentionally and stay enabled when transitioning back to HS200 or HS400. Some firmware has invalid presets, so we end up with driver strengths that can cause I/O problems. Fixes: 34597a3f60b1 ("mmc: sdhci-acpi: Add support for ACPI HID of AMD Controller with HS400") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200928154718.1.Icc21d4b2f354e83e26e57e270dc952f5fe0b0a40@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-28mmc: sdhci_am654: Enable tuning for SDR50Faiz Abbas1-0/+6
According to the SW tuning App note[1], tuning is required for all UHS speed modes. Tuning for SDR50 is not enabled in Capabilities by default so enable it from the CTL_CFG registers. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-28mmc: sdhci_am654: Add support for software tuningFaiz Abbas1-0/+41
With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-28mmc: sdhci_am654: Add support for input tap delayFaiz Abbas1-30/+84
DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. With this addition, make sure that DLL is always switched off at the beginning of the set_clock() call to simplify configuration. This also removes the need for the dll_on member in struct sdhci_am654_data. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-28mmc: sdhci_am654: Fix hard coded otap delay array sizeFaiz Abbas1-21/+21
Change hard coded array size value to depend on struct timing_data array size. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923105206.7988-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-28mmc: sdhci-of-esdhc: fix reference clock source selectionYangbo Lu1-6/+12
The bit ESDHC_PERIPHERAL_CLK_SEL to select using peripheral clock or platform clock is not able to be reset by SDHCI_RESET_ALL. So driver needs to initialize it as 1 or 0 once, to override the different value which may be configured in bootloader. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lore.kernel.org/r/20200927082304.9232-1-yangbo.lu@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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