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2022-01-11Merge tag 'for-linus-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifsLinus Torvalds1-1/+1
Pull JFFS2, UBI and UBIFS updates from Richard Weinberger: "JFFS2: - Fix for a deadlock in jffs2_write_begin() UBI: - Fixes in comments UBIFS: - Expose error counters in sysfs - Many bugfixes found by Hulk Robot and others" * tag 'for-linus-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs: jffs2: GC deadlock reading a page that is used in jffs2_write_begin() ubifs: read-only if LEB may always be taken in ubifs_garbage_collect ubifs: fix double return leb in ubifs_garbage_collect ubifs: fix slab-out-of-bounds in ubifs_change_lp ubifs: fix snprintf() length check ubifs: Document sysfs nodes ubifs: Export filesystem error counters ubifs: Error path in ubifs_remount_rw() seems to wrongly free write buffers ubifs: Make use of the helper macro kthread_run() ubi: Fix a mistake in comment ubifs: Fix spelling mistakes
2022-01-11Merge tag 'mtd/for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linuxLinus Torvalds43-1264/+2985
Pull MTD updates from Miquel Raynal: "MTD core changes: - mtdchar: Prevent unbounded allocation in MEMWRITE ioctl - gen_probe: Use bitmap_zalloc() when applicable - Introduce an expert mode for forensics and debugging purposes - Clear out unregistered devices a bit more - Provide unique name for nvmem device - Remove unused header file <linux/mtd/latch-addr-flash.h> - Fixed breaking list in __mtd_del_partition. MTD device changes: - Warn about failure to unregister mtd device in sst25l, mchp48l640, mchp23k256, and dataflash drivers. Raw NAND core changes: - Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller changes: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller changes: - OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt - Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry - Onenand: - Remove redundant variable ooblen - MPC5121: - Remove unused variable in ads5121_select_chip() - GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable - Ingenic: - JZ4740 needs 'oob_first' read page function - Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer driver changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Hyperbus changes: - Couple of fixes in Renesas hyperbus rpc-if driver to avoid crash on module remove and for missing check for error value in probe" * tag 'mtd/for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (71 commits) mtd: spi-nor: Remove debugfs entries that duplicate sysfs entries mtd: spi-nor: micron-st: write 2 bytes when disabling Octal DTR mode mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode mtd: spi-nor: core: use 2 data bytes for template ops mtd: spi-nor: Constify part specific fixup hooks mtd: spi-nor: core: Remove reference to spi-nor.c mtd: rawnand: gpmi: Use platform_get_irq_byname() to get the interrupt mtd: rawnand: omap_elm: Use platform_get_irq() to get the interrupt mtd: rawnand: omap2: Select GPMC device driver for ARCH_K3 memory: omap-gpmc: Use a compatible match table when checking for NAND controller memory: omap-gpmc: Add support for GPMC on AM64 SoC dt-bindings: memory-controllers: ti,gpmc: Add compatible for AM64 memory: omap-gpmc: Use platform_get_irq() to get the interrupt MAINTAINERS: Add an entry for Renesas NAND controller mtd: rawnand: renesas: Add new NAND controller driver dt-bindings: mtd: renesas: Describe Renesas R-Car Gen3 & RZ/N1 NAND controller mtd: rawnand: gpmi: remove unneeded variable mtd: rawnand: omap2: drop unused variable mtd: rawnand: omap2: fix force_8bit flag behaviour for DMA mode mtd: rawnand: omap2: Add compatible for AM64 SoC ...
2022-01-10Merge tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-9/+53
Pull ARM SoC driver updates from Arnd Bergmann: "There are cleanups and minor bugfixes across several SoC specific drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone, Renesas, ZynqMP Noteworthy new features are: - The op-tee firmware driver gains support for asynchronous notifications from secure-world firmware. - Qualcomm platforms gain support for new SoC types in various drivers: power domain, cache controller, RPM sleep, soc-info - Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as well as a new USIv2 driver that handles various types of serial communiction (uart, i2c, spi) - Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers, as well as memory controller support for RZ/G2L (R9A07G044). - Apple M1 gains support for the PMGR power management driver" * tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits) soc: qcom: rpmh-rsc: Fix typo in a comment soc: qcom: socinfo: Add SM6350 and SM7225 dt-bindings: arm: msm: Don't mark LLCC interrupt as required dt-bindings: firmware: scm: Add SM6350 compatible dt-bindings: arm: msm: Add LLCC for SM6350 soc: qcom: rpmhpd: Sort power-domain definitions and lists soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280 soc: qcom: rpmhpd: Rename rpmhpd struct names soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao soc: qcom: socinfo: add SM8450 ID soc: qcom: rpmhpd: Add SM8450 power domains dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding soc: qcom: smem: Update max processor count dt-bindings: arm: qcom: Document SM8450 SoC and boards dt-bindings: firmware: scm: Add SM8450 compatible dt-bindings: arm: cpus: Add kryo780 compatible soc: qcom: rpmpd: Add support for sm6125 dt-bindings: qcom-rpmpd: Add sm6125 power domains soc: qcom: aoss: constify static struct thermal_cooling_device_ops PM: AVS: qcom-cpr: Use div64_ul instead of do_div ...
2021-12-31Merge tag 'nand/for-5.17' into mtd/nextMiquel Raynal11-394/+1767
Raw NAND core: * Export nand_read_page_hwecc_oob_first() GPMC memory controller for OMAP2 NAND controller: * GPMC: - Add support for AM64 SoC and allow build on K3 platforms - Use a compatible match table when checking for NAND controller - Use platform_get_irq() to get the interrupt Raw NAND controller drivers: * OMAP2 NAND controller: - Document the missing 'rb-gpios' DT property - Drop unused variable - Fix force_8bit flag behaviour for DMA mode - Move to exec_op interface - Use platform_get_irq() to get the interrupt * Renesas: - Add new NAND controller driver with its bindings and MAINTAINERS entry * Onenand: - Remove redundant variable ooblen * MPC5121: - Remove unused variable in ads5121_select_chip() * GPMI: - Add ERR007117 protection for nfc_apply_timings - Remove explicit default gpmi clock setting for i.MX6 - Use platform_get_irq_byname() to get the interrupt - Remove unneeded variable * Ingenic: - JZ4740 needs 'oob_first' read page function * Davinci: - Rewrite function description - Avoid duplicated page read - Don't calculate ECC when reading page Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'spi-nor/for-5.17' into mtd/nextMiquel Raynal21-827/+1080
SPI NOR core changes: - Add Pratyush as SPI NOR co-maintainer. - Flash parameters initialization was done in a spaghetti way. Clean flash parameters initialization. - Rework the flash_info flags and clarify where one should be used. - Initialize all flash parameters based on JESD216 SFDP where possible. Flash parameters and settings that are SFDP discoverable should not be duplicated via flash_info flags at flash declaration. - Remove debugfs entries that duplicate sysfs entries. SPI NOR manufacturer drivers changes: - Use late_init() hook in various drivers to make it clear that those flash parameters are either not declared in the JESD216 SFDP standard, or the SFDP tables which define those flash parameters are not defined by the flash. - Fix mtd size for s3an flashes. - Write 2 bytes when disabling Octal DTR mode: 1 byte long transactions are not allowed in 8D-8D-8D mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'cfi/for-5.17' into mtd/nextMiquel Raynal1-3/+5
Hyperbus changes for v5.17-rc1 Hyperbus changes: Couple of fixes in Renesas hyperbus rpc-if driver to avoid crash on module remove and for missing check for error value in probe. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-31Merge tag 'memory-controller-drv-omap-5.17' into nand/nextMiquel Raynal2-5/+2
Memory controller drivers for v5.17 - OMAP GPMC 1. Add support for AM64 SoC. 2. Minor improvement: use platform_get_irq(). [miquel.raynal@bootlin.com: A first commit introduced a new omap compatible and another moved the IDs to a header which created a conflict: moving the new ID as well in the header fixed it.] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2021-12-29mtd: spi-nor: Remove debugfs entries that duplicate sysfs entriesTudor Ambarus1-12/+0
SPI NOR sysfs defines partname and jedec_id device attributes, which duplicate the information from debugfs. Since the sysfs directory structure and the attributes in each directory define an ABI between the kernel and user space, thus it can never be removed, remove the debugfs entries so that we don't duplicate the information. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211217122636.474976-2-tudor.ambarus@microchip.com
2021-12-23ubi: Fix a mistake in commentKai Song1-1/+1
Fixes: 2a734bb8d502 ("UBI: use debugfs for the extra checks knobs") There is a mistake in docstrings, it should be ubi_debugfs_exit_dev instead of dbg_debug_exit_dev. Signed-off-by: Kai Song <songkai01@inspur.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2021-12-23mtd: spi-nor: micron-st: write 2 bytes when disabling Octal DTR modePratyush Yadav1-5/+17
The Octal DTR configuration is stored in the CFR0V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. The next byte address contains the CFR1V register, which contains the number of dummy cycles. This is very fortunate since the enable path changes the value of this register. Reset the value to its default when disabling Octal DTR mode. This way, both changes to the flash state made when enabling can be reverted in one single transaction. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210531181757.19458-4-p.yadav@ti.com
2021-12-23mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR modePratyush Yadav1-5/+13
The Octal DTR configuration is stored in the CFR5V register. This register is 1 byte wide. But 1 byte long transactions are not allowed in 8D-8D-8D mode. Since the next byte address does not contain any register, it is safe to write any value to it. Write a 0 to it. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210531181757.19458-3-p.yadav@ti.com
2021-12-23mtd: spi-nor: core: use 2 data bytes for template opsPratyush Yadav1-2/+2
The template ops used in spi_nor_spimem_check_pp() and spi_nor_spimem_check_readop() currently set the data phase to 1 byte long. This is problematic for 8D-8D-8D protocol where odd length data phase is invalid since one cycle transfers 2 bytes and odd number of bytes would mean half a cycle is left over. This could result in a controller rejecting the op as "not supported" even though it actually supports the protocol. Change the data length to 2 bytes in these templates. One might argue that this should only be done for 8D-8D-8D operations but when talking about these templates, there is no functional difference between one and two bytes, even in STR modes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20210531181757.19458-2-p.yadav@ti.com
2021-12-23mtd: spi-nor: Constify part specific fixup hooksTudor Ambarus6-7/+7
Constify 'struct spi_nor_fixups' in order to respect flash_info structure declaration. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211106102915.153552-1-tudor.ambarus@microchip.com
2021-12-23mtd: spi-nor: core: Remove reference to spi-nor.cFlavio Suligoi1-2/+2
Remove the references to the old spi-nor.c file. The old drivers/mtd/spi-nor/spi-nor.c file is not more present and now some of its code is contained in: drivers/mtd/spi-nor/core.c Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> [tudor.ambarus@microchip.com: - remove change in Documentation/driver-api/mtd/spi-nor.rst. The documentation has to be rewritten entirely. - update commit message] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20210126092516.1431913-1-f.suligoi@asem.it
2021-12-22mtd: rawnand: gpmi: Use platform_get_irq_byname() to get the interruptLad Prabhakar1-7/+4
platform_get_resource_byname(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_byname(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211221212609.31290-3-prabhakar.mahadev-lad.rj@bp.renesas.com
2021-12-22mtd: rawnand: omap_elm: Use platform_get_irq() to get the interruptLad Prabhakar1-9/+7
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211221212609.31290-2-prabhakar.mahadev-lad.rj@bp.renesas.com
2021-12-22mtd: rawnand: omap2: Select GPMC device driver for ARCH_K3Roger Quadros1-0/+1
The GPMC device driver is required for NAND controller to work on K3 Architecture. Select it if required. Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20211221131757.2030-5-rogerq@kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-22memory: omap-gpmc: Use a compatible match table when checking for NAND controllerRoger Quadros1-4/+1
As more compatibles can be added to the GPMC NAND controller driver use a compatible match table. Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20211221131757.2030-4-rogerq@kernel.org [krzysztof: remove "is_nand" variable] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-21mtd: rawnand: renesas: Add new NAND controller driverMiquel Raynal3-0/+1432
Introduce Renesas NAND controller driver which currently supports the following features on R-Car Gen3 and RZ/N1 SoCs: - All ONFI timing modes - Different configurations of its internal ECC controller - On-die (not tested) and software ECC support - Several chips (not tested) - Subpage accesses - DMA and PIO This controller was originally provided by Evatronix before being bought by Cadence. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Ralph Siemsen <ralph.siemsen@linaro.org> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/linux-mtd/20211217142033.353599-3-miquel.raynal@bootlin.com
2021-12-20Merge tag 'tegra-for-5.17-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/driversArnd Bergmann1-8/+50
drivers: Changes for v5.17-rc1 This is an assortment of driver patches that rely on some of the changes in the for-5.17/soc branch. These have all been acked by the respective maintainers and go through the Tegra tree to more easily handle the build dependency. * tag 'tegra-for-5.17-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: staging: tegra-vde: Support generic power domain spi: tegra20-slink: Add OPP support mtd: rawnand: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support usb: chipidea: tegra: Add runtime PM and OPP support soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: Enable runtime PM during OPP state-syncing Link: https://lore.kernel.org/r/20211217162253.1801077-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-17mtd: rawnand: gpmi: remove unneeded variableMinghao Chi1-4/+1
Return status directly from function called. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211213112627.436745-1-chi.minghao@zte.com.cn
2021-12-17mtd: rawnand: omap2: drop unused variableRoger Quadros1-4/+0
devsize is not used anywhere in code. Drop it. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211209090458.24830-7-rogerq@kernel.org
2021-12-17mtd: rawnand: omap2: fix force_8bit flag behaviour for DMA modeRoger Quadros1-0/+10
In DMA mode we were not considering the force_8bit flag. Fix it by using regular non-DMA 8-bit I/O if force_8bit flag is set. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211209090458.24830-6-rogerq@kernel.org
2021-12-17mtd: rawnand: omap2: Add compatible for AM64 SoCRoger Quadros1-0/+1
AM64 SoC contains the GPMC NAND controller. Add compatible for it. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211209090458.24830-5-rogerq@kernel.org
2021-12-17mtd: rawnand: omap2: move to exec_op interfaceRoger Quadros1-279/+211
Stop using legacy interface and move to the exec_op interface. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211209090458.24830-4-rogerq@kernel.org
2021-12-17mtd: rawnand: omap2: Allow build on K3 platformsRoger Quadros1-1/+1
K3 platforms come with GPMC. Enable GPMC build for K3 platforms. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211209090458.24830-3-rogerq@kernel.org
2021-12-16mtd: rawnand: tegra: Add runtime PM and OPP supportDmitry Osipenko1-8/+50
The NAND on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now NAND must be resumed using runtime PM API in order to initialize the NAND power state. Add runtime PM and OPP support to the NAND driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-09mtdchar: prevent unbounded allocation in MEMWRITE ioctlMichał Kępień1-23/+87
In the mtdchar_write_ioctl() function, memdup_user() is called with its 'len' parameter set to verbatim values provided by user space via a struct mtd_write_req. Both the 'len' and 'ooblen' fields of that structure are 64-bit unsigned integers, which means the MEMWRITE ioctl can trigger unbounded kernel memory allocation requests. Fix by iterating over the buffers provided by user space in a loop, processing at most mtd->erasesize bytes in each iteration. Adopt some checks from mtd_check_oob_ops() to retain backward user space compatibility. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Michał Kępień <kernel@kempniu.pl> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211130113149.21848-1-kernel@kempniu.pl
2021-12-09mtd: gen_probe: Use bitmap_zalloc() when applicableChristophe JAILLET1-5/+4
'chip_map' is a bitmap. So use 'bitmap_zalloc()' to simplify code, improve the semantic and avoid some open-coded arithmetic in allocator arguments. Also change the corresponding 'kfree()' into 'bitmap_free()' to keep consistency. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/a6fe58dffe553a3e79303777d3ba9c60d7613c5b.1637510255.git.christophe.jaillet@wanadoo.fr
2021-12-09mtd: Introduce an expert mode for forensics and debugging purposesMiquel Raynal4-0/+19
When developping NAND controller drivers or when debugging filesystem corruptions, it is quite common to need hacking locally into the MTD/NAND core in order to get access to the content of the bad blocks. Instead of having multiple implementations out there let's provide a simple yet effective specific MTD-wide debugfs entry to fully disable these checks on purpose. A warning is added to inform the user when this mode gets enabled. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211118114659.1282855-1-miquel.raynal@bootlin.com
2021-12-09mtd: onenand: remove redundant variable ooblenColin Ian King1-2/+2
Variable ooblen is being initialized with a value that is never read. The variable is never used after this, so it is redundant and can be removed. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211205230729.79337-1-colin.i.king@gmail.com
2021-12-07mtd: spi-nor: issi: is25lp256: Init flash based on SFDPTudor Ambarus1-1/+1
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4_4B 0xec, for erases SPINOR_OP_BE_4K_4B 0x21, and for writes SPINOR_OP_PP_4B 0x12. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211207140254.87681-15-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDPTudor Ambarus1-1/+1
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4_4B 0xec, for erases SPINOR_OP_BE_4K_4B 0x21, and for writes SPINOR_OP_PP_1_1_4_4B 0x34. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211207140254.87681-14-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: spansion: s25fl256s0: Skip SFDP parsingTudor Ambarus1-1/+2
s25fl256s0 does not define the SFDP tables nor implements the RDSFDP 0x5a command. Skip the SFDP parsing in order to avoid issuing an unsupported command to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211207140254.87681-13-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: winbond: w25q256jvm: Init flash based on SFDPTudor Ambarus1-2/+1
Get rid of the static initialization of the flash parameters and init them when parsing SFDP. Generated a 256 Kbyte random data and did an erase, write, read back and compare test. The flash uses for reads SPINOR_OP_READ_1_4_4 0xeb, for erases SPINOR_OP_BE_4K 0x20, and for writes SPINOR_OP_PP 0x02. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211207140254.87681-12-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: core: Move spi_nor_set_addr_width() in spi_nor_setup()Tudor Ambarus1-50/+52
spi_nor_setup() configures the SPI NOR memory. Setting the addr width is too a configuration, hence we can move the spi_nor_set_addr_width() in spi_nor_setup(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20211207140254.87681-11-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: core: Init all flash parameters based on SFDP where possibleTudor Ambarus1-78/+119
New flash additions that support SFDP should be declared with PARSE_SFDP and with all the other flags that are not SFDP discoverable. Keep the old way of initializing the flash, until all the flashes are converted to use either PARSE_SFDP or SPI_NOR_SKIP_SFDP. Flashes that declare PARSE_SFDP do not have a roll-back mechanism because if spi_nor_parse_sfdp() returns an error it means that either BFPT is not supported, thus SFDP is not supported and the user didn't correctly declared the flash_info entry, or some memalloc failed. Either way we should return an error. The rest of the SFDP tables are optional, if one of the optional SFDP tables fails, we just continue. We would like to get rid of the default_init() hook, so the spi_nor_manufacturer_init_params() is not called in the new sequnce of flash initialization. Split spi_nor_info_init_params() in spi_nor_init_default_params() and spi_nor_no_sfdp_init_params(). spi_nor_init_default_params() is called for all the flashes regardless if they support SFDP or not. spi_nor_no_sfdp_init_params() is called just for the flashes that do not define SFDP and initializes parameters and setting solely based on flash_info data. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-10-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: Introduce spi_nor_init_fixup_flags()Tudor Ambarus1-8/+20
Group NOR flags initialization. Introduce a dedicated function for setting the fixup_flags and emphasise when those flash_info flags should be set: when the SNOR_F_4B_OPCODES/SNOR_F_IO_MODE_EN_VOLATILE setttings can not be discovered by SFDP for this particular flash because the SFDP table that indicates this support is not defined in the flash. In case the table for his support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. No functional change intended in this patch. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-9-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: Introduce spi_nor_init_flags()Tudor Ambarus1-38/+51
Used to initialize the NOR flags for settings that are not defined in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP. This moves the setting of SNOR_F_READY_XSR_RDY and SNOR_F_HAS_LOCK late in the init call, without any functional change expected. The rest of the flags were already set after the spi_nor_init_params(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-8-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: Rework the flash_info flagsTudor Ambarus17-566/+695
Clarify for what the flash_info flags are used for. Split them in four categories and a bool: 1/ FLAGS: flags that indicate support that is not defined by the JESD216 standard in its SFDP tables. 2/ NO_SFDP_FLAGS: these flags are used when the flash does not define the SFDP tables. These flags indicate support that can be discovered via SFDP. Used together with SPI_NOR_SKIP_SFDP flag. 3/ FIXUP_FLAGS: flags that indicate support that can be discovered via SFDP ideally, but can not be discovered for this particular flash because the SFDP table that indicates this support is not defined by the flash. In case the table for this support is defined but has wrong values, one should instead use a post_sfdp() hook to set the SNOR_F equivalent flag. 4/ MFR_FLAGS: manufacturer private flags. Used in the manufacturer fixup hooks to differentiate support between flashes of the same manufacturer. 5/ PARSE_SFDP: sets info->parse_sfdp to true. All flash_info entries that support SFDP should be converted to set info->parse_sfdp to true. SPI NOR flashes that statically declare one of the SPI_NOR_{DUAL, QUAD, OCTAL, OCTAL_DTR}_READ flags and do not support the RDSFDP command are gratuiously receiving the RDSFDP command in the attempt of parsing the SFDP tables. It is not desirable to issue commands that are not supported, so introduce PARSE_SFDP to help on this situation. New flash additions/updates should be declared/updated to use either PARSE_SFDP or SPI_NOR_SKIP_SFDP. Once all the flash_info entries are converted to use SPI_NOR_SKIP_SFDP or PARSE_SFDP, we can get rid of the SPI_NOR_SKIP_SFDP flag and use just the bool nor->info->parse_sfdp to determine whether to parse SFDP or not. SPI_NOR_SKIP_SFDP flag is kept just as a way to differentiate whether a flash is converted to the new flags logic or not. Support that can be discovered when parsing SFDP should not be duplicated by explicit flags at flash declaration. All the flash parameters will be discovered when parsing SFDP. Sometimes manufacturers wrongly define some fields in the SFDP tables. If that's the case, SFDP data can be amended with the fixups() hooks. It is not common, but if the SFDP tables are entirely wrong, and it does not worth the hassle to tweak the SFDP parameters by using the fixups hooks, or if the flash does not define the SFDP tables at all, then statically init the flash with the SPI_NOR_SKIP_SFDP flag and specify the rest of flash capabilities with the flash info flags. With time, we want to convert all flashes to use PARSE_SFDP and stop triggering the SFDP parsing with the SPI_NOR_{DUAL, QUAD, OCTAL*}_READ flags. Getting rid of the SPI_NOR_{OCTAL, OCTAL_DTR}_READ trigger is easily achievable, the rest are a long term goal. Manufacturer specific flags like USE_CLSR, USE_FSR, SPI_NOR_XSR_RDY, will be removed in a future series. No functional changes intended in this patch. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-7-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: core: Introduce flash_info mfr_flagsTudor Ambarus2-11/+40
Used in the manufacturer fixup hooks to differentiate support between flashes of the same manufacturer. Not used in the SPI NOR core. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-6-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only when SFDP is definedTudor Ambarus2-29/+24
spi_nor_post_sfdp_fixups() was called even when there were no SFDP tables defined. late_init() should be instead used for flashes that do not define SFDP tables. Use spi_nor_post_sfdp_fixups() just to fix SFDP data. post_sfdp() hook is as of now used just by s28hs512t, mt35xu512aba, and both support SFDP, there's no functional change with this patch. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-5-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: Introduce spi_nor_set_mtd_info()Tudor Ambarus4-29/+35
Used to init all the mtd_info fields. Move the mtd_info init the last thing in the spi_nor_scan(), so that we avoid superfluous initialization of the mtd_info fields in case of errors. While here use common naming scheme for functions that are setting mtd_info fields: s/spi_nor_register_locking_ops/spi_nor_set_mtd_locking_ops s/spi_nor_otp_init/spi_nor_set_mtd_otp_ops The functions names are self explanatory, get rid of the comment for the OTP function. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-4-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: core: Don't use mtd_info in the NOR's probe sequence of callsTudor Ambarus2-5/+4
Use NOR parameters in the probe's sequence of calls, thus nor->params->size instead of nor->mtd.size and let the mtd_info fields be used by the mtd calls (mtd->_erase, mtd->_read, mtd->_write). mtd_info fields should not be used during probe because we haven't registered mtd yet. It's safe to drop xilinx's setting of nor->mtd.size, now that we use nor->params->size in spi_nor_set_addr_width(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-3-tudor.ambarus@microchip.com
2021-12-07mtd: spi-nor: Fix mtd size for s3an flashesTudor Ambarus1-1/+2
As it was before the blamed commit, s3an_nor_scan() was called after mtd size was set with params->size, and it overwrote the mtd size value with '8 * nor->page_size * nor->info->n_sectors' when XSR_PAGESIZE was set. With the introduction of s3an_post_sfdp_fixups(), we missed to update the mtd size for the s3an flashes. Fix the mtd size by updating both nor->params->size, (which will update the mtd_info size later on) and nor->mtd.size (which is used in spi_nor_set_addr_width()). Fixes: 641edddb4f43 ("mtd: spi-nor: Add s3an_post_sfdp_fixups()") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211207140254.87681-2-tudor.ambarus@microchip.com
2021-12-03mtd: rawnand: mpc5121: Remove unused variable in ads5121_select_chip()Geert Uytterhoeven1-1/+0
drivers/mtd/nand/raw/mpc5121_nfc.c: In function ‘ads5121_select_chip’: drivers/mtd/nand/raw/mpc5121_nfc.c:294:19: warning: unused variable ‘mtd’ [-Wunused-variable] 294 | struct mtd_info *mtd = nand_to_mtd(nand); | ^~~ Fixes: 758b56f58b66bebc ("mtd: rawnand: Pass a nand_chip object to chip->select_chip()") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211122132138.3899138-1-geert@linux-m68k.org
2021-12-03mtd: dataflash: Add device-tree SPI IDsJon Hunter1-0/+8
Commit 5fa6863ba692 ("spi: Check we have a spi_device_id for each DT compatible") added a test to check that every SPI driver has a spi_device_id for each DT compatiable string defined by the driver and warns if the spi_device_id is missing. The spi_device_ids are missing for the dataflash driver and the following warnings are now seen. WARNING KERN SPI driver mtd_dataflash has no spi_device_id for atmel,at45 WARNING KERN SPI driver mtd_dataflash has no spi_device_id for atmel,dataflash Fix this by adding the necessary spi_device_ids. Fixes: 96c8395e2166 ("spi: Revert modalias changes") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211130112443.107730-1-jonathanh@nvidia.com
2021-12-03mtd: rawnand: fsmc: Fix timing computationHerve Codina1-8/+24
Under certain circumstances, the timing settings calculated by the FSMC NAND controller driver were inaccurate. These settings led to incorrect data reads or fallback to timing mode 0 depending on the NAND chip used. The timing computation did not take into account the following constraint given in SPEAr3xx reference manual: twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL Enhance the timings calculation by taking into account this additional constraint. This change has no impact on slow timing modes such as mode 0. Indeed, on mode 0, computed values are the same with and without the patch. NANDs which previously stayed in mode 0 because of fallback to mode 0 can now work at higher speeds and NANDs which were not working at all because of the corrupted data work at high speeds without troubles. Overall improvement on a Micron/MT29F1G08 (flash_speed tool): mode0 mode3 eraseblock write speed 3220 KiB/s 4511 KiB/s eraseblock read speed 4491 KiB/s 7529 KiB/s Fixes: d9fb079571833 ("mtd: nand: fsmc: add support for SDR timings") Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211119150316.43080-5-herve.codina@bootlin.com
2021-12-03mtd: rawnand: fsmc: Take instruction delay into accountHerve Codina1-0/+4
The FSMC NAND controller should apply a delay after the instruction has been issued on the bus. The FSMC NAND controller driver did not handle this delay. Add this waiting delay in the FSMC NAND controller driver. Fixes: 4da712e70294 ("mtd: nand: fsmc: use ->exec_op()") Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211119150316.43080-4-herve.codina@bootlin.com
2021-12-03mtd: rawnand: Fix nand_choose_best_timings() on unsupported interfaceHerve Codina1-2/+2
When the NV-DDR interface is not supported by the NAND chip, the value of onfi->nvddr_timing_modes is 0. In this case, the best_mode variable value in nand_choose_best_nvddr_timings() is -1. The last for-loop is skipped and the function returns an uninitialized value. If this returned value is 0, the nand_choose_best_sdr_timings() is not executed and no 'best timing' are set. This leads the host controller and the NAND chip working at default mode 0 timing even if a better timing can be used. Fix this uninitialized returned value. nand_choose_best_sdr_timings() is pretty similar to nand_choose_best_nvddr_timings(). Even if onfi->sdr_timing_modes should never be seen as 0, nand_choose_best_sdr_timings() returned value is fixed. Fixes: a9ecc8c814e9 ("mtd: rawnand: Choose the best timings, NV-DDR included") Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211119150316.43080-3-herve.codina@bootlin.com
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