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2019-11-11mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1Tudor Ambarus1-4/+4
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Extend the SR Read Back testTudor Ambarus1-19/+39
Test that all the bits from Status Register 1 and Status Register 2 were written correctly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Rework the disabling of block write protectionTudor Ambarus1-90/+50
spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-11mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()Tudor Ambarus1-5/+115
Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: fix delayed error detection on HyperFlashSergei Shtylyov1-25/+33
The commit 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") added checking for the status register error bits into chip_good() to only return 1 if these bits are 0s. Unfortunately, this means that polling using chip_good() always reaches a timeout condition when erase or program failure bits are set. Let's fully delegate the task of determining the error conditions to cfi_check_err_status() and make chip_good() only look for the Device Ready/Busy condition. Fixes: 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: only check errors when ready in cfi_check_err_status()Sergei Shtylyov1-0/+4
Cypress S26K{L|S}P{128|256|512}S datasheet says that the error bits in the status register are only valid when the "device ready" bit 7 is set. Add the check for the device ready bit in cfi_check_err_status() as that function isn't always called with this bit set. Fixes: 4844ef80305d ("mtd: cfi_cmdset_0002: Add support for polling status register") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_0002: don't free cfi->cfiq in error path of cfi_amdstd_setup()Hou Tao1-1/+0
Else there may be a double-free problem, because cfi->cfiq will be freed by mtd_do_chip_probe() if both the two invocations of check_cmd_set() return failure. Signed-off-by: Hou Tao <houtao1@huawei.com> Reviewed-by: Richard Weinberger <richard@nod.at> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_cmdset_*: kill useless 'ret' variable initializersSergei Shtylyov3-18/+18
The 'ret' local variables are typically initialized to 0 but this value is often unused, thus we can kill those initializers. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-09mtd: cfi_util: use DIV_ROUND_UP() in cfi_udelay()Sergei Shtylyov1-1/+1
Use DIV_ROUND_UP() in cfi_udelay() instead of open-coding it... Doing this also helpfully gets rid of two complaints from 'scripts/checkpatch.pl --strict': CHECK: spaces preferred around that '+' (ctx:VxV) #29: FILE: drivers/mtd/chips/cfi_util.c:29: + msleep((us+999)/1000); ^ CHECK: spaces preferred around that '/' (ctx:VxV) #29: FILE: drivers/mtd/chips/cfi_util.c:29: + msleep((us+999)/1000); ^ Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Print debug message when the read back test failsTudor Ambarus1-1/+6
Demystify where the EIO error occurs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Check all the bits written, not just the BP onesTudor Ambarus1-5/+4
Check that all the bits written in the write_sr_and_check() method match the status_new received value. Failing to write the other bits is dangerous too, extend the check. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Fix errno on Quad Enable methodsTudor Ambarus1-3/+3
When the Read-Modify-Write-Read-Back Quad Enable methods failed on the Read-Back, they returned -EINVAL. Since this is an I/O error, return -EIO. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Drop spansion_quad_enable()Tudor Ambarus1-53/+5
Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Describe all the Reg OpsTudor Ambarus1-11/+127
Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()Tudor Ambarus1-51/+23
Merge static int spi_nor_write_sr(struct spi_nor *nor, u8 val) static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) into static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) The Status Register can be written with one or two bytes. Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Move the WE and wait calls inside Write SR methodsTudor Ambarus1-64/+44
Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()Tudor Ambarus1-6/+2
spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case of errors. The callers didn't check their return value, make them of type void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Rename label as it is no longer genericTudor Ambarus1-11/+11
Rename 'sst_write_err' label to 'out' as it is no longer generic for all the errors in the sst_write() method, and may introduce confusion. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-07mtd: spi-nor: Check for errors after each Register OperationTudor Ambarus1-21/+60
Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Print debug info inside Reg Ops methodsTudor Ambarus1-42/+127
Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07mtd: spi-nor: Use dev_dbg insted of dev_err for low level infoTudor Ambarus1-21/+21
What most users care about is "my dev is not working properly". All low level information should be discovered when activating the debug traces. Keep error messages just for the following cases: - when the SR/FSR report program or erase fails, or attempts of modifying a protected sector, - when the JEDEC ID is not recognized, - when the resume() call fails, - when the spi_nor_check() fails. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-02mtd: spi-nor: fix silent truncation in spi_nor_read_raw()Sergei Shtylyov1-1/+1
spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: fix silent truncation in spi_nor_read()Sergei Shtylyov1-1/+1
spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e1233bd ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flashMika Westerberg1-0/+1
Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-11-02mtd: spi-nor: Print device info in case of errorTudor Ambarus1-2/+2
Print identifying information about struct device. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Constify data to write to the Status RegisterTudor Ambarus1-2/+2
Constify the data to write to the Status Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Fix retlen handling in sst_write()Tudor Ambarus1-4/+5
In case the write of the first byte failed, retlen was incorrectly incremented to *retlen += actual; on the exit path. retlen should be incremented when actual data was written to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop redundant error reports in Reg Ops callersTudor Ambarus1-40/+10
Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()Tudor Ambarus1-25/+30
Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr()Tudor Ambarus1-18/+20
Let the callers pass the pointer to the DMA-able buffer where the value of the Flag Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Caller stops compare the return value of spi_nor_read_fsr() with negative, spi_nor_read_fsr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()Tudor Ambarus1-53/+64
Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Don't overwrite errno from Reg OpsTudor Ambarus1-7/+6
Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop explicit cast to int to already int valueTudor Ambarus1-9/+6
ret is already of type int. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Stop compare with negative in Reg Ops methodsTudor Ambarus1-10/+13
spi_mem_exec_op() nor->controller_ops->write_reg() nor->controller_ops->read_reg() spi_nor_wait_till_ready() Return 0 on success, -errno otherwise. Stop compare with negative and compare with zero in all the register operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Group all Reg Ops to avoid forward declarationsTudor Ambarus1-213/+213
Group all register methods up in the file, to avoid forward declarations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Drop duplicated new lineTudor Ambarus1-1/+0
Two new lines, one after another, drop one. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-11-01mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methodsTudor Ambarus1-54/+56
All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-30mtd: rawnand: remove unecessary checking if dmac is NULLPiotr Sroka1-2/+2
Remove unecessary checking if dmac is NULL. If Cadence nand controller driver uses DMA engine then cdns_ctrl->dmac cannot be NULL. It is verified during driver initialization. If Cadence nand controller driver does not use DMA engine then CPU IO read/write are executed instead of slave DMA transfer. In that case cdns_ctrl->dmac is not used at all. Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Piotr Sroka <piotrs@cadence.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: cadence: Remove dev_err() on platform_get_irq() failureYueHaibing1-3/+2
platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: mxic: Remove dev_err() on platform_get_irq() failureYueHaibing1-3/+1
platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: brcmnand: Fix NULL pointer assignmentFlorian Fainelli1-1/+1
Sparse complained about the following: drivers/mtd/nand/raw/brcmnand/brcmnand.c:921:40: warning: Using plain integer as NULL pointer fix this issue by assigning the pointer to NULL. Fixes: c1ac2dc34b51 ("mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: rawnand: denali: remove the old unified controller/chip DT supportMasahiro Yamada1-51/+4
Commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips") supported the new binding for the separate controller/chip representation, keeping the backward compatibility. All the device trees in upstream migrated to the new binding. Remove the support for the old binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: spear_smi: Fix Write Burst modeMiquel Raynal1-1/+37
Any write with either dd or flashcp to a device driven by the spear_smi.c driver will pass through the spear_smi_cpy_toio() function. This function will get called for chunks of up to 256 bytes. If the amount of data is smaller, we may have a problem if the data length is not 4-byte aligned. In this situation, the kernel panics during the memcpy: # dd if=/dev/urandom bs=1001 count=1 of=/dev/mtd6 spear_smi_cpy_toio [620] dest c9070000, src c7be8800, len 256 spear_smi_cpy_toio [620] dest c9070100, src c7be8900, len 256 spear_smi_cpy_toio [620] dest c9070200, src c7be8a00, len 256 spear_smi_cpy_toio [620] dest c9070300, src c7be8b00, len 233 Unhandled fault: external abort on non-linefetch (0x808) at 0xc90703e8 [...] PC is at memcpy+0xcc/0x330 The above error occurs because the implementation of memcpy_toio() tries to optimize the number of I/O by writing 4 bytes at a time as much as possible, until there are less than 4 bytes left and then switches to word or byte writes. Unfortunately, the specification states about the Write Burst mode: "the next AHB Write request should point to the next incremented address and should have the same size (byte, half-word or word)" This means ARM architecture implementation of memcpy_toio() cannot reliably be used blindly here. Workaround this situation by update the write path to stick to byte access when the burst length is not multiple of 4. Fixes: f18dbbb1bfe0 ("mtd: ST SPEAr: Add SMI driver for serial NOR flash") Cc: Russell King <linux@armlinux.org.uk> Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-10-29mtd: physmap_of: add a hook for Intel IXP4xx flash probingLinus Walleij5-0/+166
In order to support device tree probing of IXP4xx NOR flash chips, a certain big-endian or mixed-endian memory access pattern need to be used. I have opted to use the pattern set by previous plug-ins to physmap for Gemini and Versatile, just override some functions and reuse most of the physmap core code as it is to minimize maintenance. Parts of drivers/mtd/ixp4xx.c are copied into this file. After we have IXP4xx converted fully to device tree, the drivers/mtd/ixp4xx.c file will be deleted and this will be the only access pattern to the IXP4xx flash. I did not keep the quirk in the flash write function after probe, where the old code for a while checks for access to odd addresses, fails and assigns a "faster" write function once it has convinced probe to only use 2-byte accesses. As we mandate that this device should be using bank-width = <2> this should not be a problem unless misconfigured. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-29mtd: maps: l440gx: Avoid printing address to dmesgFuqian Huang1-1/+1
Avoid printing the address of l440gx_map.virt every time l440gx init. Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-10-23compat_ioctl: move drivers to compat_ptr_ioctlArnd Bergmann1-33/+3
Each of these drivers has a copy of the same trivial helper function to convert the pointer argument and then call the native ioctl handler. We now have a generic implementation of that, so use it. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Reviewed-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Reviewed-by: Jason Gunthorpe <jgg@mellanox.com> Reviewed-by: Jiri Kosina <jkosina@suse.cz> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-10-23mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definitionTudor Ambarus1-8/+7
n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', to comply with the SPI NOR int (*read_reg)() method. The 'const' qualifier has no meaning for parameters passed by value, drop it. Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, drop it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: Introduce 'struct spi_nor_controller_ops'Tudor Ambarus7-96/+136
Move all SPI NOR controller driver specific ops in a dedicated structure. 'struct spi_nor' becomes lighter. Use size_t for lengths in 'int (*write_reg)()' and 'int (*read_reg)()'. Rename wite/read_buf to buf, the name of the functions are suggestive enough. Constify buf in int (*write_reg). Comply with these changes in the SPI NOR controller drivers. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignmentTudor Ambarus1-1/+0
The pointer to 'struct spi_nor' is kzalloc'ed above in the code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-10-23mtd: spi-nor: add support for en25qh16DENG Qingfang1-0/+2
Tested on HiWiFi C526A Datasheet is available at: http://www.xinyahong.com/upLoad/product/month_1411/201411201256018276.pdf Signed-off-by: DENG Qingfang <dqfext@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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