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2017-08-08net: dsa: mediatek: add adjust link support for user portsJohn Crispin2-0/+39
Manually adjust the port settings of user ports once PHY polling has completed. This patch extends the adjust_link callback to configure the per port PMCR register, applying the proper values polled from the PHY. Without this patch flow control was not always getting setup properly. Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkavalli@openmesh.com> Signed-off-by: Muciri Gatimu <muciri@openmesh.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-20net: dsa: b53: Add missing ARL entries for BCM53125Florian Fainelli1-0/+1
The BCM53125 entry was missing an arl_entries member which would basically prevent the ARL search from terminating properly. This switch has 4 ARL entries, so add that. Fixes: 1da6df85c6fb ("net: dsa: b53: Implement ARL add/del/dump operations") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-19net: dsa: mv88e6xxx: Enable CMODE config support for 6390XMartin Hundebøll1-0/+1
Commit f39908d3b1c45 ('net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10') added support for setting the CMODE for the 6390X family, but only enabled it for 9290 and 6390 - and left out 6390X. Fix support for setting the CMODE on 6390X also by assigning mv88e6390x_port_set_cmode() to the .port_set_cmode function pointer in mv88e6390x_ops too. Fixes: f39908d3b1c4 ("net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10") Signed-off-by: Martin Hundebøll <mnhu@prevas.dk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-25net: dsa: mv88e6xxx: fix error code in mv88e6390_serdes_power()Dan Carpenter1-1/+1
We're accidentally returning the wrong variable. "cmode" is uninitialized at this point so it causes a static checker warning. Fixes: 6335e9f2446b ("net: dsa: mv88e6xxx: mv88e6390X SERDES support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-23net: dsa: bcm_sf2: Remove special handling of "internal" phy-modeFlorian Fainelli1-11/+5
The PHY library now supports an "internal" phy-mode, thus making our custom parsing code now unnecessary. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: better IEEE Prio Mapping Table descriptionVivien Didelot2-7/+8
Kill the remaining shift macro in favor of calculating at compile time its value from the more descriptive mask, which gives us a better representation of the register layout. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 remaining macrosVivien Didelot2-35/+57
Prefix and document the remaining Global 2 registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Watchdog macrosVivien Didelot2-43/+52
The Marvell 88E6352 family has a Global 2 register dedicated to the watchdog setup. But the 88E6390 turned it into an indirect table. Prefix and document that. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Switch MAC macrosVivien Didelot2-2/+7
Prefix and document the Global 2 Switch MAC registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 EEPROM macrosVivien Didelot2-25/+38
Prefix and document the Global 2 EEPROM registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 PVT macrosVivien Didelot2-12/+21
Prefix and document the Global 2 Cross-chip Port VLAN registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 MGMT macrosVivien Didelot2-13/+21
Prefix and document the Global 2 MGMT registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Device Mapping macrosVivien Didelot2-5/+7
Prefix and document the Global 2 Device Mapping macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: prefix Global 2 Trunk macrosVivien Didelot2-14/+17
Prefix and document the Global 2 Trunk registers macros. At the same time, fix the hask -> hash typo and use the mv88e6xxx_port_mask helper. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: clarify SMI PHY functionsVivien Didelot2-100/+143
Marvell chips with an SMI PHY access in Global 2 registers handle both Clause 22 and Clause 45 of IEEE 802.3. The 88E6390 family has addition bits to target the internal or external PHYs connected to the device, and a Setup function in addition to the default (register) Access function. Prefix the SMI PHY Command and Data registers macros, implement clear helpers for Clause 22 and 44 Access functions, rename variable to match the SMI and switch vocabulary (device and register addresses for Clause 22 and port and device class for Clause 45.) Finally do not use complex macros but simple 16-bit mask to document the registers organization. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-20net: dsa: mv88e6xxx: add irl_init_all opVivien Didelot4-50/+116
Some Marvell chips have an Ingress Rate Limit unit. But the command values slightly differs between models: 88E6352 use 3-bit for operations while 88E6390 use different 2-bit operations. This commit kills the IRL flags in favor of a new operation implementing the "Init all resources to the initial state" operation. This fixes the operation of 88E6390 family where 0x1000 means Read the selected resource 0, register 0 on port 16, instead of init all. A mv88e6xxx_irl_setup helper is added to wrap the operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-16net: dsa: loop: Implement ethtool statisticsFlorian Fainelli1-2/+77
When a DSA driver implements ethtool statistics, we also override the master network device's ethtool statistics with the CPU port's statistics and this has proven to be a possible source of bugs in the past. Enhance the dsa_loop.c driver to provide statistics under the forme of ok/error reads and writes from the per-port PHY read/writes. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-16net: dsa: loop: Inline unregister_fixed_phys()Florian Fainelli1-10/+5
This is a simple function that only gets used in the driver's remove function, inline it there. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Prio and Tag macrosVivien Didelot2-19/+32
Prefix and document the remaining Global IP and IEEE Priority and Core Tag Type registers and give them a clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Stats macrosVivien Didelot3-30/+41
Prefix and document the Global Stats Operation and Counter registers and give them a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Monitor Control macrosVivien Didelot2-43/+60
Prefix and document the Global Monitor Control Register macros (which became the Global Monitor & MGMT Control Register with 88E6390) and give a clear 16-bit registers representation. Use __bf_shf to get the shift value at compile time instead of adding new defined macros for it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Control macrosVivien Didelot3-46/+50
Prefix and document the Global Control and Control 2 registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global VTU macrosVivien Didelot4-68/+90
Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global ATU macrosVivien Didelot3-68/+85
Prefix and document the Global ATU Registers macros and give clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Switch MAC macrosVivien Didelot3-22/+37
Prefix and document the Global Switch MAC Address Register macros and give clear 16-bit register representation. At the same time, move mv88e6xxx_g1_set_switch_mac in global1.c, where it belongs. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Status macrosVivien Didelot4-31/+33
Prefix and document the Global Status Register macros and give clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: Remove master_netdev and use dst->cpu_dp->netdevFlorian Fainelli2-4/+4
In preparation for supporting multiple CPU ports, remove dst->master_netdev and ds->master_netdev and replace them with only one instance of the common object we have for a port: struct dsa_port::netdev. ds->master_netdev is currently write only and would be helpful in the case where we have two switches, both with CPU ports, and also connected within each other, which the multi-CPU port patch series would address. While at it, introduce a helper function used in net/dsa/slave.c to immediately get a reference on the master network device called dsa_master_netdev(). Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix remaining port macrosVivien Didelot3-13/+32
For implicit namespacing and clarity, prefix the remaining common Port Registers macros with MV88E6XXX_PORT. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port IEEE Priority mapping macrosVivien Didelot2-29/+38
For implicit namespacing and clarity, prefix the common Port IEEE Priority Remapping registers macros with MV88E6095_PORT_IEEE_PRIO. The 88E6390 family turned the 0x18 register into a single indirect table, document that at the same time. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Also fix the following checkpatch checks with a temporary variable: CHECK: Alignment should match open parenthesis #65: FILE: drivers/net/dsa/mv88e6xxx/port.c:932: + err = mv88e6xxx_port_ieeepmt_write(chip, port, + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP, Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Association Vector macrosVivien Didelot2-7/+10
For implicit namespacing and clarity, prefix the common Port Association Vector Register macros with MV88E6XXX_PORT_ASSOC_VECTOR. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Egress Rate Control macrosVivien Didelot3-5/+12
For implicit namespacing and clarity, prefix the common Port Egress Rate Control and Port Egress Rate Control 2 registers macros with MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 2 macrosVivien Didelot3-48/+50
For implicit namespacing and clarity, prefix the common Port Control 2 Register macros with MV88E6XXX_PORT_CTL2 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6095_PORT_CTL2_CPU_PORT_MASK.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Default VLAN macrosVivien Didelot3-9/+14
For implicit namespacing and clarity, prefix the common Port Default VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Based VLAN macrosVivien Didelot2-7/+9
For implicit namespacing and clarity, prefix the common Port Based VLAN Register macros with MV88E6XXX_PORT_BASE_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 1 macrosVivien Didelot2-10/+15
For implicit namespacing and clarity, prefix the common Port Control 1 Register macros with MV88E6XXX_PORT_CTL1. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control macrosVivien Didelot3-77/+79
For implicit namespacing and clarity, prefix the common Port Control Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6185_PORT_CTL0_USE_TAG.) The reason for CTL0 is to make it clear between the badly named "Port Control", "Port Control 1" and "Port Control 2" registers. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Switch ID macrosVivien Didelot2-57/+61
For implicit namespacing and clarity, prefix the common Switch ID Register macros with MV88E6XXX_PORT_SWITCH_ID. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers, this means shifting their values by 4. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Jamming macrosVivien Didelot2-9/+22
For implicit namespacing and clarity, prefix the common Port Jamming Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6097_PORT_JAM_CTL.) The 88E6390 family renamed the register to Flow Control and turned it into an indirect table. Document that as well. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port MAC Control macrosVivien Didelot2-56/+64
For implicit namespacing and clarity, prefix the common MAC Control Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Status macrosVivien Didelot4-54/+56
For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ between implementations with a chosen reference model (e.g. MV88E6352_PORT_STS_EEE.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: prefix PHY macrosVivien Didelot2-7/+8
Prefix the PHY_* macros with a Marvell specific MV88E6XXX_ prefix. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: rework jumbo size operationVivien Didelot4-23/+36
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: rework pause limit operationVivien Didelot4-32/+37
All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in a 16-bit register. New ones have an indirect table using 8-bit data. The mv88e6xxx library functions (such as in port.c) must not contain driver logic, but only generic helpers. This patch changes the port_pause_config operation for port_pause_limit taking two u8 arguments for input and output limits. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: do not prefix ops with g1Vivien Didelot2-56/+56
The mv88e6xxx_ops describe functionalities, regardless their locations (which can be Global1, Global2, or whatever register set.) Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port and set_egress_port. No functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: use bridge state valuesVivien Didelot2-21/+22
Reuse the BR_STATE_* values to abstract a port STP state value. This provides shorter names and better control over the DSA switch operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: add egress mode enumerationVivien Didelot4-8/+32
As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv888e6xxx: do not use netdev printingVivien Didelot2-37/+33
The mv888e6xxx driver accesses a port's netdev mostly for printing. This is bad for 2 reasons: DSA and CPU ports do not have a netdev pointer; it doesn't give us a correct picture of why a DSA driver might need to access a port's netdev. Instead simply use dev_* printing functions with chip->dev (or ds->dev depending on the scope, both guaranteed to exist), with a p%d prefix for the target port. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: do not skip ports on VLAN delVivien Didelot1-4/+0
The mv88e6xxx driver currently tries to be smart and remove by itself a VLAN entry from the VTU when the driven switch sees no user ports as members of the VLAN. This is bad in a multi-chip switch fabric, since a chip in between others may have no bridge port members, but still needs to be aware of the VID in order to correctly pass frames in the data path. Now that the DSA core explicitly manages DSA and CPU ports, do not skip them when checking remaining VLAN members. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: exclude all ports in new VLANVivien Didelot1-4/+3
Now that the DSA core adds the CPU and DSA ports itself to the new VLAN entry, there is no need to include them as members of this VLAN when initializing a new VTU entry. As of now, initialize a new VTU entry with all ports excluded. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: define membership on VLAN addVivien Didelot1-5/+11
Define the target port membership of the VLAN entry in mv88e6xxx_port_vlan_add where ds is scoped. Allow the DSA core to call later the port_vlan_add operation for CPU or DSA ports, by using the Unmodified membership for these ports, as in the current behavior. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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