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2017-06-16net: dsa: loop: Implement ethtool statisticsFlorian Fainelli1-2/+77
When a DSA driver implements ethtool statistics, we also override the master network device's ethtool statistics with the CPU port's statistics and this has proven to be a possible source of bugs in the past. Enhance the dsa_loop.c driver to provide statistics under the forme of ok/error reads and writes from the per-port PHY read/writes. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-16net: dsa: loop: Inline unregister_fixed_phys()Florian Fainelli1-10/+5
This is a simple function that only gets used in the driver's remove function, inline it there. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Prio and Tag macrosVivien Didelot2-19/+32
Prefix and document the remaining Global IP and IEEE Priority and Core Tag Type registers and give them a clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Stats macrosVivien Didelot3-30/+41
Prefix and document the Global Stats Operation and Counter registers and give them a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Monitor Control macrosVivien Didelot2-43/+60
Prefix and document the Global Monitor Control Register macros (which became the Global Monitor & MGMT Control Register with 88E6390) and give a clear 16-bit registers representation. Use __bf_shf to get the shift value at compile time instead of adding new defined macros for it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Control macrosVivien Didelot3-46/+50
Prefix and document the Global Control and Control 2 registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global VTU macrosVivien Didelot4-68/+90
Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global ATU macrosVivien Didelot3-68/+85
Prefix and document the Global ATU Registers macros and give clear 16-bit registers representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Switch MAC macrosVivien Didelot3-22/+37
Prefix and document the Global Switch MAC Address Register macros and give clear 16-bit register representation. At the same time, move mv88e6xxx_g1_set_switch_mac in global1.c, where it belongs. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-15net: dsa: mv88e6xxx: prefix Global Status macrosVivien Didelot4-31/+33
Prefix and document the Global Status Register macros and give clear 16-bit register representation. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: Remove master_netdev and use dst->cpu_dp->netdevFlorian Fainelli2-4/+4
In preparation for supporting multiple CPU ports, remove dst->master_netdev and ds->master_netdev and replace them with only one instance of the common object we have for a port: struct dsa_port::netdev. ds->master_netdev is currently write only and would be helpful in the case where we have two switches, both with CPU ports, and also connected within each other, which the multi-CPU port patch series would address. While at it, introduce a helper function used in net/dsa/slave.c to immediately get a reference on the master network device called dsa_master_netdev(). Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix remaining port macrosVivien Didelot3-13/+32
For implicit namespacing and clarity, prefix the remaining common Port Registers macros with MV88E6XXX_PORT. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port IEEE Priority mapping macrosVivien Didelot2-29/+38
For implicit namespacing and clarity, prefix the common Port IEEE Priority Remapping registers macros with MV88E6095_PORT_IEEE_PRIO. The 88E6390 family turned the 0x18 register into a single indirect table, document that at the same time. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Also fix the following checkpatch checks with a temporary variable: CHECK: Alignment should match open parenthesis #65: FILE: drivers/net/dsa/mv88e6xxx/port.c:932: + err = mv88e6xxx_port_ieeepmt_write(chip, port, + MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP, Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Association Vector macrosVivien Didelot2-7/+10
For implicit namespacing and clarity, prefix the common Port Association Vector Register macros with MV88E6XXX_PORT_ASSOC_VECTOR. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Egress Rate Control macrosVivien Didelot3-5/+12
For implicit namespacing and clarity, prefix the common Port Egress Rate Control and Port Egress Rate Control 2 registers macros with MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 2 macrosVivien Didelot3-48/+50
For implicit namespacing and clarity, prefix the common Port Control 2 Register macros with MV88E6XXX_PORT_CTL2 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6095_PORT_CTL2_CPU_PORT_MASK.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Default VLAN macrosVivien Didelot3-9/+14
For implicit namespacing and clarity, prefix the common Port Default VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Based VLAN macrosVivien Didelot2-7/+9
For implicit namespacing and clarity, prefix the common Port Based VLAN Register macros with MV88E6XXX_PORT_BASE_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control 1 macrosVivien Didelot2-10/+15
For implicit namespacing and clarity, prefix the common Port Control 1 Register macros with MV88E6XXX_PORT_CTL1. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Control macrosVivien Didelot3-77/+79
For implicit namespacing and clarity, prefix the common Port Control Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6185_PORT_CTL0_USE_TAG.) The reason for CTL0 is to make it clear between the badly named "Port Control", "Port Control 1" and "Port Control 2" registers. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Switch ID macrosVivien Didelot2-57/+61
For implicit namespacing and clarity, prefix the common Switch ID Register macros with MV88E6XXX_PORT_SWITCH_ID. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers, this means shifting their values by 4. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Jamming macrosVivien Didelot2-9/+22
For implicit namespacing and clarity, prefix the common Port Jamming Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6097_PORT_JAM_CTL.) The 88E6390 family renamed the register to Flow Control and turned it into an indirect table. Document that as well. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port MAC Control macrosVivien Didelot2-56/+64
For implicit namespacing and clarity, prefix the common MAC Control Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-13net: dsa: mv88e6xxx: prefix Port Status macrosVivien Didelot4-54/+56
For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ between implementations with a chosen reference model (e.g. MV88E6352_PORT_STS_EEE.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: prefix PHY macrosVivien Didelot2-7/+8
Prefix the PHY_* macros with a Marvell specific MV88E6XXX_ prefix. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: rework jumbo size operationVivien Didelot4-23/+36
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: rework pause limit operationVivien Didelot4-32/+37
All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in a 16-bit register. New ones have an indirect table using 8-bit data. The mv88e6xxx library functions (such as in port.c) must not contain driver logic, but only generic helpers. This patch changes the port_pause_config operation for port_pause_limit taking two u8 arguments for input and output limits. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: do not prefix ops with g1Vivien Didelot2-56/+56
The mv88e6xxx_ops describe functionalities, regardless their locations (which can be Global1, Global2, or whatever register set.) Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port and set_egress_port. No functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: use bridge state valuesVivien Didelot2-21/+22
Reuse the BR_STATE_* values to abstract a port STP state value. This provides shorter names and better control over the DSA switch operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv88e6xxx: add egress mode enumerationVivien Didelot4-8/+32
As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-09net: dsa: mv888e6xxx: do not use netdev printingVivien Didelot2-37/+33
The mv888e6xxx driver accesses a port's netdev mostly for printing. This is bad for 2 reasons: DSA and CPU ports do not have a netdev pointer; it doesn't give us a correct picture of why a DSA driver might need to access a port's netdev. Instead simply use dev_* printing functions with chip->dev (or ds->dev depending on the scope, both guaranteed to exist), with a p%d prefix for the target port. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: do not skip ports on VLAN delVivien Didelot1-4/+0
The mv88e6xxx driver currently tries to be smart and remove by itself a VLAN entry from the VTU when the driven switch sees no user ports as members of the VLAN. This is bad in a multi-chip switch fabric, since a chip in between others may have no bridge port members, but still needs to be aware of the VID in order to correctly pass frames in the data path. Now that the DSA core explicitly manages DSA and CPU ports, do not skip them when checking remaining VLAN members. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: exclude all ports in new VLANVivien Didelot1-4/+3
Now that the DSA core adds the CPU and DSA ports itself to the new VLAN entry, there is no need to include them as members of this VLAN when initializing a new VTU entry. As of now, initialize a new VTU entry with all ports excluded. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-08net: dsa: mv88e6xxx: define membership on VLAN addVivien Didelot1-5/+11
Define the target port membership of the VLAN entry in mv88e6xxx_port_vlan_add where ds is scoped. Allow the DSA core to call later the port_vlan_add operation for CPU or DSA ports, by using the Unmodified membership for these ports, as in the current behavior. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-07net: dsa: mv88e6xxx: Have 6161/6123 use EDSA tagsAndrew Lunn1-2/+2
The mv88e6161 and mv88e6123 are capable of using EDSA tags when passing frames from the host to the switch and back. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-06Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller1-3/+3
Just some simple overlapping changes in marvell PHY driver and the DSA core code. Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-06net: dsa: mv88e6xxx: fix 6085 frame mode maskingVivien Didelot1-1/+1
The register bits used for the frame mode were masked with DSA (0x1) instead of the mask value (0x3) in the 6085 implementation of port_set_frame_mode. Fix this. Fixes: 56995cbc3540 ("net: dsa: mv88e6xxx: Refactor CPU and DSA port setup") Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: mv88e6161 uses mv88e6320 stats snapshotAndrew Lunn1-2/+2
The mv88e6161 was using the wrong method to perform statistics snapshot. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: 6161 uses global 2 for PHY accessAndrew Lunn1-4/+4
Access to the internal PHYs of the 6161 and 6123 go through global 2 SMI registers. Fix the ops structure. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: move the Global 2 macrosVivien Didelot3-103/+103
Move the GLOBAL2_* macros where they belong, in the related global2.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: move the Global 1 macrosVivien Didelot3-141/+142
Move the GLOBAL_* macros where they belong, in the related global1.h header. Include it in global2.c which uses GLOBAL_STATUS_IRQ_DEVICE. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: move the Port macrosVivien Didelot2-160/+160
Move the PORT_* macros where they belong, in the related port.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: move PHY macrosVivien Didelot2-4/+3
Move the PHY_* macros where they belong, in the related phy.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-04net: dsa: mv88e6xxx: rename chip headerVivien Didelot13-16/+19
The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. At the same time, ensure that relative header inclusions are separated by a newline and sorted alphabetically. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-31dsa: add DSA switch driver for Microchip KSZ9477Woojung Huh8-0/+3398
The KSZ9477 is a fully integrated layer 2, managed, 7 ports GigE switch with numerous advanced features. 5 ports incorporate 10/100/1000 Mbps PHYs. The other 2 ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. The SGMII port may interface to a fiber optic transceiver. This driver currently supports vlan, fdb, mdb & mirror dsa switch operations. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Woojung Huh <Woojung.Huh@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-31net: dsa: remove dev arg of dsa_register_switchVivien Didelot6-6/+6
The current dsa_register_switch function takes a useless struct device pointer argument, which always equals ds->dev. Drivers either call it with ds->dev, or with the same device pointer passed to dsa_switch_alloc, which ends up being assigned to ds->dev. This patch removes the second argument of the dsa_register_switch and _dsa_register_switch functions. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-31net: dsa: mv88e6xxx: rename PHY PPU functionsVivien Didelot1-19/+19
Respect the implicit naming convention used in all register sets specific files, by renaming the mv88e6xxx_ppu_* functions with the mv88e6xxx_phy_* prefix. This is simply a s/xxx_ppu/xxx_phy_ppu/ substitution. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-31net: dsa: mv88e6xxx: rename PHY PPU accessorsVivien Didelot3-14/+17
Make it clear that mv88e6xxx_phy_ppu_{read,write} are an implementation of the .phy_{read,write} operations, by renaming them with the mv88e6185 prefix, since 88E6185 it is the reference switch model supported in an upstream board (ZII Dev Rev B), which makes use of them. Distinguish the signatures of implementation specific and generic PHY functions in the phy.h header. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-31net: dsa: mv88e6xxx: provide a PHY setup helperVivien Didelot3-9/+11
Similarly to the VTU, PVT and ATU setup, provide a mv88e6xxx_phy_setup helper which wraps mv88e6xxx_ppu_enable, so that no more PPU-related functions are exposed outside of phy.c. Thus make mv88e6xxx_ppu_enable static. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-30net: dsa: b53: remove unused dev argumentVivien Didelot1-5/+3
The port net device passed to b53_fdb_copy is not used. Remove it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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