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path: root/drivers/net/ethernet/atheros (follow)
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2013-01-03net: remove unnecessary NET_ADDR_RANDOM "bitclean"Jiri Pirko2-2/+0
NET_ADDR_SET is set in dev_set_mac_address() no need to alter dev->addr_assign_type value in drivers. Signed-off-by: Jiri Pirko <jiri@resnulli.us> Signed-off-by: David S. Miller <davem@davemloft.net>
2013-01-03net: set dev->addr_assign_type correctlyJiri Pirko2-2/+2
Not a bitfield, but a plain value. Signed-off-by: Jiri Pirko <jiri@resnulli.us> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-12-07drivers/net: fix up function prototypes after __dev* removalsGreg Kroah-Hartman4-9/+5
The __dev* removal patches for the network drivers ended up messing up the function prototypes for a bunch of drivers. This patch fixes all of them back up to be properly aligned. Bonus is that this almost removes 100 lines of code, always a nice surprise. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-12-03net/atheros: remove __dev* attributesBill Pemberton5-30/+31
CONFIG_HOTPLUG is going away as an option. As result the __dev* markings will be going away. Remove use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit. Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Cc: Jay Cliburn <jcliburn@gmail.com> Cc: Chris Snook <chris.snook@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-10-06sections: fix section conflicts in drivers/netAndi Kleen2-2/+2
Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: David Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-09-12Merge branch 'pci/stephen-const' into nextBjorn Helgaas2-2/+2
* pci/stephen-const: make drivers with pci error handlers const scsi: make pci error handlers const netdev: make pci_error_handlers const PCI: Make pci_error_handlers const
2012-09-07netdev: make pci_error_handlers constStephen Hemminger2-2/+2
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-08-23atl1c: Use PCI Express Capability accessorsJiang Liu1-1/+1
Use PCI Express Capability access functions to simplify atl1c driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-20atl1c: fix issue of io access mode for AR8152 v2.1Cloud Ren2-1/+20
When io access mode is enabled by BOOTROM or BIOS for AR8152 v2.1, the register can't be read/write by memory access mode. Clearing Bit 8 of Register 0x21c could fixed the issue. Signed-off-by: Cloud Ren <cjren@qca.qualcomm.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-16ethernet: Use eth_random_addrJoe Perches3-3/+3
Convert the existing uses of random_ether_addr to the new eth_random_addr. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-10Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller1-1/+0
Conflicts: net/batman-adv/bridge_loop_avoidance.c net/batman-adv/bridge_loop_avoidance.h net/batman-adv/soft-interface.c net/mac80211/mlme.c With merge help from Antonio Quartulli (batman-adv) and Stephen Rothwell (drivers/net/usb/qmi_wwan.c). The net/mac80211/mlme.c conflict seemed easy enough, accounting for a conversion to some new tracing macros. Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-10drivers/net/ethernet: Fix (nearly-)kernel-doc comments for various functionsBen Hutchings6-148/+99
Fix incorrect start markers, wrapped summary lines, missing section breaks, incorrect separators, and some name mismatches. Delete a few that are content-free. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-07-08atl1c: fix issue of transmit queue 0 timed outCloud Ren1-1/+0
some people report atl1c could cause system hang with following kernel trace info: --------------------------------------- WARNING: at.../net/sched/sch_generic.c:258 dev_watchdog+0x1db/0x1d0() ... NETDEV WATCHDOG: eth0 (atl1c): transmit queue 0 timed out ... --------------------------------------- This is caused by netif_stop_queue calling when cable Link is down. So remove netif_stop_queue, because link_watch will take it over. Signed-off-by: xiong <xiong@qca.qualcomm.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Cloud Ren <cjren@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-06-06ethernet: Remove casts to same typeJoe Perches5-30/+24
Adding casts of objects to the same type is unnecessary and confusing for a human reader. For example, this cast: int y; int *p = (int *)&y; I used the coccinelle script below to find and remove these unnecessary casts. I manually removed the conversions this script produces of casts with __force, __iomem and __user. @@ type T; T *p; @@ - (T *)p + p A function in atl1e_main.c was passed a const pointer when it actually modified elements of the structure. Change the argument to a non-const pointer. A function in stmmac needed a __force to avoid a sparse warning. Added it. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: remove PHY polling from atl1c_change_mtuHuang, Xiong1-8/+0
PHY polling code for FPGA is considered in every MDIO R/W API. no need to add additional code to atl1c_change_mtu. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: David Liu <dwliu@qca.qaulcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: Disable L0S when no cable linkHuang, Xiong1-1/+1
L0S might be unstable if no cable link, only enable it when link up. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: do MAC-reset when PHY link downHuang, Xiong1-27/+47
There may be tx-skbs still pending in HW when PHY link down. Reset MAC will make the DMA engine go to the start point. and release all pending skbs. Note: Reset MAC will clear any interrupt status and mask. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: cancel task when interface closedHuang, Xiong1-0/+5
common_task might be running while close routine is called, wait/cancel it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: enlarge L1 response waiting timerHuang, Xiong1-1/+1
The hardware incorrectly process L0S/L1 entrance if the chipset/root response after specific/shorter timer and cause system hang. Enlarge the timeout value to avoid this issue. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: refine mac address related codeHuang, Xiong3-74/+57
On some platform with EEPROM/OTP existing, the BIOS could overwrite a new MAC address for the NIC. so, the permanent mac address should be from BIOS. the address is restored when driver removing. Voltage raising isn't applicable for l1d. Replace swab32 with htonl for big/little endian platform. related Registers are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: remove code of closing register writable attributionHuang, Xiong1-6/+0
The Close-action is done by atl1c_reset_pcie, remove it from atl1c_get_permanent_address. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: clear WoL status when reset pcieHuang, Xiong2-5/+3
WoL status is read-clear and should be cleared when in S0 status. putting it in atl1c_reset_pcie is more suitable than in atl1c_get_permanent_address. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-30atl1c: add PHY link event(up/down) patchHuang, Xiong4-0/+92
On some platforms the PHY settings need to change depending on the cable link status to get better stability. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: refine start/enable code for MAC moduleHuang, Xiong1-63/+30
merge TXQ/RXQ/MAC start/enable code to one function as they are started/enabled at the same time, just like stop/disable them in the function of atl1c_stop_mac. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: add function atl1c_power_savingHuang, Xiong3-126/+108
This function is used for suspend of S1/S3/S4 and driver remove. It sets MAC/PHY based on the WoL configuation to get lower power consumption. atl1c_phy_power_saving is renamed to atl1c_phy_to_ps_link, this function is just make PHY enter a link/speed mode to eat less power. REG_MAC_CTRL register is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: remove PHY reset/init for link down eventHuang, Xiong1-2/+0
it's unnecessary to reset/init phy when link down. Only L1/L2 chip (supported by atlx) need such action. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: update PHY reset related routineHuang, Xiong3-200/+346
Many magic data are re-configured for PHY during its reset operation based on chip type to get better compability and stability. REG_PHY_CTRL register may be configured by BIOS before enter OS. so, the driver can't directly write to it without any Read-Op. this change also affect suspend and phy_disable routines. PHY debug ports and extension registers are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: remove PHY polling from atl1c_openHuang, Xiong1-7/+0
PHY polling code for FPGA is considered in every MDIO R/W API. no need to add additional code to atl1c_open. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: refine SERDES-clock related codeHuang, Xiong3-27/+49
bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause the write-reg operation fail without cable connected. so, please do connect the cable when apply this patch to the driver to make sure these 2bits are cleared by new driver. The revised code is move to al1c_reset_mac. SERDES register definition is refined as well. when do reset MAC, speed/duplex control right should be transferred to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW. SERDES register definition is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: remove PHY contrl in atl1c_reset_pcieHuang, Xiong1-9/+2
atl1c_reset_phy follows atl1c_reset_pcie in the whole driver, so, it's unnecessary to add PHY control code in atl1c_reset_pcie. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: refine phy-register read/write functionHuang, Xiong3-61/+197
phy register is read/write via MDIO control module --- that module will be affected by the hibernate status, to access phy regs in hib stutus, slow frequency clk must be selected. To access phy extension register, the MDIO related registers are refined/updated, a _core function is re-wroted for both regular PHY regs and extension regs. existing PHY r/w function is revised based on the _core. PHY extension registers will be used for the comming patches. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-26atl1c: remove REG_PHY_STATUSHuang, Xiong2-9/+0
this register is used for l1e(dev=1026) l1c/l1d/l2cb don't use it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: remove MDIO_REG_ADDR_MASK in atl1c_mdio_read/writeHuang, Xiong1-2/+2
MDIO_REG_ADDR_MASK is already applied in function atl1c_write_phy_reg and atl1c_read_phy_reg Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: fix WoL(magic) issue for l2cb 1.1Huang, Xiong2-28/+52
l2cb 1.1 hardware has a bug for magic wakeup, the workaround is to add pattern enable. WoL related registers are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: refine atl1c_pcie_patchHuang, Xiong2-18/+48
bit PCIE_PHYMISC_FORCE_RCV_DET is only for l1c&l2c to fix WoL issue, other chips set bit5 of REG_MASTER_CTRL --- this way could save more power than the former, and the bit should be kept all time. l2cb 1.x has special setting for L0S/L1 l2cb 1.x & l1d 1.x should clear Vendor Message on some platforms, otherwise it will cause the root complex hang. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: refine/update ASPM configurationHuang, Xiong2-122/+111
some platforms(BIOS or OS) may change ASPM configuration in PCI Express Link Control Register directly and dynamically regardless the device driver installation. Checking if ASPM support during the driver init phase by reading PCI Express Link Contrl Register doesn't make sense. This refine/update assume L0S/L1 is defalut enabled as hw->ctrl_flags inited. atl1c_set_aspm will set real configuration based on chip capability to hardware register. atl1c_disable_l0s_l1 and register definition of REG_PM_CTRL are refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patchHuang, Xiong1-1/+6
bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend clear it after resume to enable pclk(PCIE clock) switch to low frequency(25M) in some circumstances to save power. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: refine reg definition of REG_MASTER_CTRLHuang, Xiong2-19/+24
refine/update register REG_MASTER_CTRL definition according with hardware spec. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: clear PCIE error status in atl1c_reset_pcieHuang, Xiong2-17/+11
clear PCIE error status (error log is write-1-clear). REG_PCIE_UC_SEVERITY is removed as it's a standard pcie register, and using kernle API to access it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: remove dmar_dly_cnt and dmaw_dly_cntHuang, Xiong2-4/+0
dmar_dly_cnt and dmaw_dly_cnt aren't used by hardware/driver any more. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: update right threshold for TSOHuang, Xiong3-5/+9
atl1c_configure_tx used a wrong value of MAX_TX_OFFLOAD_THRESH(9KB) for TSO threshold. the right value should be 7KB Fast Ethernet controller doesn't support Jumbo frame. Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: add module parameter for l1c_wait_until_idleHuang, Xiong2-15/+24
l1c_wait_until_idle is called for serval modules (TXQ/RXQ/TXMAC/RXMAC). specific moudle have specific idle/busy status in reg REG_IDLE_STATUS. the previous code return wrongly if all modules are in idle status, regardless the 'stop' action is applied on individual module. Refine the reg REG_IDLE_STATUS definition as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-19atl1c: threshold for ASPM is changed based on chip capabilityHuang, Xiong1-3/+4
threshold setting to control ASPM for diff chips are different. currently, all gigabit-capability chips have limited-ASPM under 100M throughput. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: restore max-read-request-size in Device Conrol RegisterHuang, Xiong2-11/+11
in some platforms, we found the max-read-request-size in Device Control Register is set to 0 by (BIOS?) during bootup, this will cause the performance(throughput) very bad. Restore it to a min-value. register definition of REG_DEVICE_CTRL is removed, using kernel API to access it as it's a standard pcie register. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: using fixed TXQ configuration for l2cb and l1cHuang, Xiong2-19/+28
using fixed TXQ config for l2cb and l1c regardless dmar_block to make tx-DMA more stable. register REG_TXQ_CTRL is refined as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: remove dmaw_blockHuang, Xiong2-5/+0
dmaw_block is never used in the driver, remove it. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: correct wrong definition of REG_DMA_CTRLHuang, Xiong2-43/+32
some fields of REG_DMA_CTRL(15C0) are wrong, replace with the newest one. haredware uses fixed dma-write-block size, remove dmaw_block related code in function atl1c_configure_dma. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: wrong register used to stop TXQHuang, Xiong1-1/+1
function atl1c_stop_mac uses wrong register of REG_TWSI_CTRL to stop mac, replace it with REG_TXQ_CTRL. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: remove code related to rxq 1/2/3Huang, Xiong2-19/+13
remove code related to rxq 1/2/3 since multi-q not support. refine REG_RXQ_CTRL definition as well. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2012-04-18atl1c: split 2 32bit registers of TPD to 4 16bit registersHuang, Xiong3-39/+22
TPD producer/consumer index is 16bit wide. 16bit read/write reduce the dependency of the 2 tpd rings (hi and lo) rename reg(157C/1580) to keep name coninsistency. Signed-off-by: xiong <xiong@qca.qualcomm.com> Tested-by: Liu David <dwliu@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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