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2018-11-16net: mvneta: Don't advertise 2.5G modesMaxime Chevallier1-9/+3
Using 2.5G speed relies on the SerDes lanes being configured accordingly. The lanes have to be reconfigured to switch between 1G and 2.5G, and for now only the bootloader does this configuration. In the case we add a Comphy driver to handle switching the lanes dynamically, it's better for now to stick with supporting only 1G and add advertisement for 2.5G once we really are capable of handling both speeds without problem. Since the interface mode is initialy taken from the DT, we want to make sure that adding comphy support won't break boards that don't update their dtb. Fixes: da58a931f248 ("net: mvneta: Add support for 2500Mbps SGMII") Reported-by: Andrew Lunn <andrew@lunn.ch> Reported-by: Russell King <linux@armlinux.org.uk> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-11-09net: mvneta: correct typoAlexandre Belloni1-2/+2
The reserved variable should be named reserved1. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-30net: mvpp2: Fix affinity hint allocationMarc Zyngier2-4/+15
The mvpp2 driver has the curious behaviour of passing a stack variable to irq_set_affinity_hint(), which results in the kernel exploding the first time anyone accesses this information. News flash: userspace does, and irqbalance will happily take the machine down. Great stuff. An easy fix is to track the mask within the queue_vector structure, and to make sure it has the same lifetime as the interrupt itself. Fixes: e531f76757eb ("net: mvpp2: handle cases where more CPUs are available than s/w threads") Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-25octeontx2-af: Use GFP_ATOMIC under spin lockWei Yongjun1-1/+1
The function nix_update_mce_list() is called from nix_update_bcast_mce_list(), and a spin lock is held here, so we should use GFP_ATOMIC instead. Fixes: 4b05528ebf0c ("octeontx2-af: Update bcast list upon NIXLF alloc/free") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-24octeontx2-af: Copy the right amount of memoryDan Carpenter1-1/+1
This is a copy and paste bug where we copied the sizeof() from the chunk before. We're copying more data than intended but the destination is a union so it doesn't cause memory corruption. Fixes: ffb0abd7e9cb ("octeontx2-af: NIX AQ instruction enqueue support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Support for NIXLF's UCAST/PROMISC/ALLMULTI modesSunil Goutham4-1/+105
By default NIXLF is set in UCAST mode. This patch adds a new mailbox message which when sent by a RVU PF changes this default mode. When promiscuous mode is needed, the reserved promisc entry for each of RVU PF is setup to match against ingress channel number only, so that all pkts on that channel are accepted and forwarded to the mode change requesting PF_FUNC's NIXLF. PROMISC and ALLMULTI modes are supported only for PFs, for VFs only UCAST mode is supported. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Support for setting MAC addressSunil Goutham3-1/+35
Added a new mailbox message for a PF/VF to set/update it's NIXLF's MAC address. Also updates unicast NPC MCAM entry with this address as matching DMAC. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Support for changing RSS algorithmSunil Goutham4-1/+108
This patch adds support for a RVU PF/VF to change NIX Rx flowkey algorithm index in NPC RX RSS_ACTION. eg: a ethtool command changing RSS algorithm for a netdev interface would trigger this change in NPC. If PF/VF doesn't specify any MCAM entry index then default UCAST entry of the NIXLF attached to PF/VF will be updated with RSS_ACTION and flowkey index. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: NIX Rx flowkey configuration for RSSSunil Goutham3-0/+187
Configure NIX RX flowkey algorithm configuration to support RSS (receive side scaling). Currently support for only L3/L4 2-tuple and 4-tuple hash of IPv4/v6/TCP/UDP/SCTP is added. HW supports upto 32 different flowkey algorithms which SW can define, this patch defines 9. NPC RX ACTION has to point to one of these flowkey indices for RSS to work. The configuration is dependent on NPC parse result's layer info. So if NPC KPU profile changes suchthat LID/LTYPE values of above said protocols change then this configuration will most likely be effected. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Install ucast and bcast pkt forwarding rulesSunil Goutham4-0/+375
Upon NIXLF_ALLOC install a unicast forwarding rule in NPC MCAM like below - Match pkt DMAC with NIXLF attached PF/VF's MAC address. - Ingress channel - Action is UCAST - Forward to PF_FUNC of this NIXLF And broadcast pkt forwarding rule as - Match L2B bit in MCAM search key - Ingress channel - Action is UCAST, for now, later it will be changed to MCAST. Only PFs can install this rule Upon NIXLF_FREE disable all MCAM entries in use by that NIXLF. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Add LMAC channel info to NIXLF_ALLOC responseStanislaw Kardach4-0/+18
Add LMAC channel info like Rx/Tx channel base and count to NIXLF_ALLOC mailbox message response. This info is used by NIXLF attached RVU PF/VF to configure SQ's default channel, TL3_TL2_LINKX_CFG and to install MCAM rules in NPC based on matching ingress channel number. Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: NPC MCAM and LDATA extract minimal configurationSunil Goutham4-0/+181
This patch adds some minimal configuration for NPC MCAM and LDATA extraction which is sufficient enough to install ucast/bcast/promiscuous forwarding rules. Below is the config done - LDATA extraction config to extract DMAC from pkt to offset 64bit in MCAM search key. - Set MCAM lookup keysize to 224bits - Set MCAM TX miss action to UCAST_DEFAULT - Set MCAM RX miss action to DROP Also inorder to have guaranteed space in MCAM to install ucast forwarding rule for each of RVU PF/VF, reserved one MCAM entry for each of NIXLF for ucast rule. And two entries for each of RVU PF. One for bcast pkt replication and other for promiscuous mode which allows all pkts received on a HW CGX/LBK channel. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Enable packet length and csum validationSunil Goutham2-0/+28
Config NPC layer info from KPU profile into protocol checker to identify outer L2/IPv4/TCP/UDP headers in a packet. And enable IPv4 checksum validation. L3/L4 and L4 CSUM validation will be enabled by PF/VF drivers by configuring NIX_AF_LF(0..127)_RX_CFG via mbox i.e 'nix_lf_alloc_req->rx_cfg' Also enable setting of NPC_RESULT_S[L2B] when an outer L2 broadcast address is detected. This will help in installing NPC MCAM rules for broadcast packets. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Support for VTAG strip and captureVamsi Attunuru4-1/+101
Added support for PF/VF drivers to configure NIX to capture and/or strip VLAN tag from ingress packets. Signed-off-by: Vamsi Attunuru <vamsi.attunuru@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Update bcast list upon NIXLF alloc/freeSunil Goutham1-0/+133
Upon NIXLF ALLOC/FREE, add or remove corresponding PF_FUNC from the broadcast packet replication list of the CGX LMAC mapped RVU PF. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Broadcast packet replication supportSunil Goutham2-0/+220
Allocate memory for mcast/bcast/mirror replication entry contexts, replication buffers (used by HW) and config HW with corresponding memory bases. Added support for installing MCEs via NIX AQ mbox. For now support is restricted to broadcast pkt replication, hence MCE table size and number of replication buffers allocated are less. Each CGX LMAC mapped RVU PF is assigned a MCE table of size 'num VFs of that PF + PF'. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Config pkind for CGX mapped PFsGeetha sowjanya7-2/+90
For each CGX LMAC that is mapped to a RVU PF, allocate a pkind and config the same in CGX. For a received packet at CGX LMAC interface this pkind is used by NPC block to start parsing of packet. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Config NPC KPU engines with parser profileSunil Goutham6-1/+385
This patch configures all 16 KPUs and iKPU (pkinds) with the KPU parser profile defined in npc_profile.h. Each KPU engine has a 128 entry CAM, only CAM entries which are listed in the profile are enabled and rest are left disabled. Also - Memory is allocated for pkind's bitmap and PFFUNC, interface channel mapping. - Added all CSR offsets of NPC HW block. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Add NPC KPU profileHao Zheng2-0/+5852
NPC block is responsible for parsing and forwarding packets to different NIXLFs. NPC has 16 KPU engines (Kangaroo parse engine) and one iKPU which represents pkinds. Each physical port either CGX/LBK is assigned a pkind and upon receiving a packet HW takes that port's pkind and starts parsing as per the KPU engines config. This patch adds header files which contain configuration profile/array for each of the iKPU and 16 KPU engines. Signed-off-by: Hao Zheng <hao.zheng@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Reset NIXLF's Rx/Tx statsVamsi Attunuru3-1/+34
This patch adds a new mailbox message to reset a NIXLF's receive and transmit HW stats. Signed-off-by: Vamsi Attunuru <vamsi.attunuru@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: NIX Tx scheduler queue config supportSunil Goutham5-5/+199
This patch adds support for a PF/VF driver to configure NIX transmit scheduler queues via mbox. Since PF/VF doesn't know the absolute HW index of the NIXLF attached to it, AF traps the register config and overwrites with the correct NIXLF index. HW supports shaping, colouring and policing of packets with these multilevel traffic scheduler queues. Instead of introducing different mbox message formats for different configurations and making both AF & PF/VF driver implementation cumbersome, access to the scheduler queue's CSRs is provided via mbox. AF checks whether the sender PF/VF has the corresponding queue allocated or not and dumps the config to HW. With a single mbox msg 20 registers can be configured. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: NIX Tx scheduler queues alloc/freeSunil Goutham4-4/+265
Added support for a PF/VF to allocate or free NIX transmit scheduler queues via mbox. For setting up pkt transmission priorities between queues, the scheduler queues have to be contiguous w.r.t their HW indices. So both contiguous and non-contiguous allocations are supported. Upon receiving NIX_TXSCH_FREE mbox msg all scheduler queues allocated to sending PFFUNC (PF/VF) will be freed. Selective free is not supported. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Remove set but not used variables 'devnum, is_pf'YueHaibing1-22/+3
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/marvell/octeontx2/af/rvu.c: In function 'rvu_detach_rsrcs': drivers/net/ethernet/marvell/octeontx2/af/rvu.c:855:6: warning: variable 'devnum' set but not used [-Wunused-but-set-variable] drivers/net/ethernet/marvell/octeontx2/af/rvu.c:853:7: warning: variable 'is_pf' set but not used [-Wunused-but-set-variable] drivers/net/ethernet/marvell/octeontx2/af/rvu.c: In function 'rvu_mbox_handler_ATTACH_RESOURCES': drivers/net/ethernet/marvell/octeontx2/af/rvu.c:1054:7: warning: variable 'is_pf' set but not used [-Wunused-but-set-variable] drivers/net/ethernet/marvell/octeontx2/af/rvu.c:1053:6: warning: variable 'devnum' set but not used [-Wunused-but-set-variable] It never used since introduction in commit 746ea74241fa ("octeontx2-af: Add RVU block LF provisioning support") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-22octeontx2-af: Remove set but not used variable 'block'YueHaibing1-3/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c: In function 'rvu_npa_init': drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c:446:20: warning: variable 'block' set but not used [-Wunused-but-set-variable] It never used since introduction in commit 7a37245ef23f ("octeontx2-af: NPA block admin queue init") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Support for disabling NIX RQ/SQ/CQ contextsGeetha sowjanya3-3/+129
This patch adds support for a RVU PF/VF to disable all RQ/SQ/CQ contexts of a NIX LF via mbox. This will be used by PF/VF drivers upon teardown or while freeing up HW resources. A HW context which is not INIT'ed cannot be modified and a RVU PF/VF driver may or may not INIT all the RQ/SQ/CQ contexts. So a bitmap is introduced to keep track of enabled NIX RQ/SQ/CQ contexts, so that only enabled hw contexts are disabled upon LF teardown. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NIX AQ instruction enqueue supportSunil Goutham4-9/+680
Add support for a RVU PF/VF to submit instructions to NIX AQ via mbox. Instructions can be to init/write/read RQ/SQ/CQ/RSS contexts. In case of read, context will be returned as part of response to the mbox msg received. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Alloc bitmaps for NIX Tx scheduler queuesSunil Goutham3-1/+114
Allocate bitmaps and memory for PFVF mapping info for maintaining NIX transmit scheduler queues maintenance. PF/VF drivers will request for alloc, free e.t.c of Tx schedulers via mailbox. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NIX LSO config for TSOv4/v6 offloadSunil Goutham4-0/+138
Config LSO formats for TSOv4 and TSOv6 offloads. These formats tell HW which fields in the TCP packet's headers have to be updated while performing segmentation offload. Also report PF/VF drivers the LSO format indices as part of response to NIX_LF_ALLOC mbox msg. These indices are used in SQE extension headers while framing SQE for pkt transmission with TSO offload. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NIX block LF initializationSunil Goutham4-0/+308
Upon receiving NIX_LF_ALLOC mbox message allocate memory for NIXLF's CQ, SQ, RQ, CINT, QINT and RSS HW contexts and configure respective base iova HW. Enable caching of contexts into NIX NDC. Return SQ buffer (SQB) size, this PF/VF MAC address etc info e.t.c to the mbox msg sender. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NIX block admin queue initSunil Goutham5-1/+220
Initialize NIX admin queue (AQ) i.e alloc memory for AQ instructions and for the results. All NIX LFs will submit instructions to AQ to init/write/read RQ/SQ/CQ/RSS contexts and in case of read, get context from result memory. Also before configuring/using NIX block calibrate X2P bus and check if NIX interfaces like CGX and LBK are in active and working state. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Support for disabling NPA Aura/Pool contextsGeetha sowjanya3-0/+110
This patch adds support for a RVU PF/VF to disable all Aura/Pool contexts of a NPA LF via mbox. This will be used by PF/VF drivers upon teardown or while freeing up HW resources. A HW context which is not INIT'ed cannot be modified and a RVU PF/VF driver may or may not INIT all the Aura/Pool contexts. So a bitmap is introduced to keep track of enabled NPA Aura/Pool contexts, so that only enabled hw contexts are disabled upon LF teardown. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NPA AQ instruction enqueue supportSunil Goutham5-0/+427
Add support for a RVU PF/VF to submit instructions to NPA AQ via mbox. Instructions can be to init/write/read Aura/Pool/Qint contexts. In case of read, context will be returned as part of response to the mbox msg received. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NPA block LF initializationSunil Goutham5-3/+214
Upon receiving NPA_LF_ALLOC mbox message allocate memory for NPALF's aura, pool and qint contexts and configure the same to HW. Enable caching of contexts into NPA NDC. Return pool related info like stack size, num pointers per stack page e.t.c to the mbox msg sender. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: NPA block admin queue initSunil Goutham6-2/+309
Initialize NPA admin queue (AQ) i.e alloc memory for AQ instructions and for the results. All NPA LFs will submit instructions to AQ to init/write/read Aura/Pool contexts and in case of read, get context from result memory. Added some common APIs for allocating memory for a queue and get IOVA in return, these APIs will be used by NIX AQ and for other purposes. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Enable or disable CGX internal loopbackGeetha sowjanya5-0/+72
Add support to enable or disable internal loopback mode in CGX. New mbox IDs CGX_INTLBK_ENABLE/DISABLE added for this. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Forward CGX link notifications to PFsLinu Cherian6-12/+368
Upon receiving notification from firmware the CGX event handler in the AF driver gets the current link info such as status, speed, duplex etc from CGX driver and sends it across to PFs who have registered to receive such notifications. To support above - Mbox messaging support for sending msgs from AF to PF has been added. - Added mbox msgs so that PFs can register/unregister for link events. - Link notifications are sent to PF under two scenarioss. 1. When a asynchronous link change notification is received from firmware with notification flag turned on for that PF. 2. Upon notification turn on request, the current link status is send to the PF. Also added a new mailbox msg using which RVU PF/VF can retrieve their mapped CGX LMAC's current link info. Link info includes status, speed, duplex and lmac type. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Support for MAC address filters in CGXVidhya Raman5-0/+183
This patch adds support for setting MAC address filters in CGX for PF interfaces. Also PF interfaces can be put in promiscuous mode. Dataplane PFs access this functionality using mailbox messages to the AF driver. Signed-off-by: Vidhya Raman <vraman@marvell.com> Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Support to retrieve CGX LMAC statsChristina Jacob5-0/+76
This patch adds support for a RVU PF/VF driver to retrieve it's mapped CGX LMAC Rx and Tx stats from AF via mbox. New mailbox msg is added is added. Signed-off-by: Christina Jacob <cjacob@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: CGX Rx/Tx enable/disable mbox handlersSunil Goutham5-0/+73
Added new mailbox msgs for RVU PF/VFs to request AF to enable/disable their mapped CGX::LMAC Rx & Tx. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-17octeontx2-af: Improve register polling loopSunil Goutham1-3/+3
Instead of looping on a integer timeout, use time_before(jiffies), so that maximum poll time is capped. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-15octeontx2-af: remove unused cgx_fwi_link_changeArnd Bergmann1-17/+0
The newly added driver causes a warning about a function that is not used anywhere: drivers/net/ethernet/marvell/octeontx2/af/cgx.c:320:12: error: 'cgx_fwi_link_change' defined but not used [-Werror=unused-function] Remove it for now, until a user gets added. If we want to use this function from another module, we also need a declaration in a header file, which is currently missing, so it would have to change anyway. Fixes: 1463f382f58d ("octeontx2-af: Add support for CGX link management") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-11octeontx2-af: Remove set but not used variable 'dev'YueHaibing1-3/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/marvell/octeontx2/af/cgx.c: In function 'cgx_fwi_event_handler': drivers/net/ethernet/marvell/octeontx2/af/cgx.c:257:17: warning: variable 'dev' set but not used [-Wunused-but-set-variable] It never be used since introduction in commit 1463f382f58d ("octeontx2-af: Add support for CGX link management") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Register for CGX lmac eventsLinu Cherian3-4/+108
Added support in RVU AF driver to register for CGX LMAC link status change events from firmware and managing them. Processing part will be added in followup patches. - Introduced eventqueue for posting events from cgx lmac. Queueing mechanism will ensure that events can be posted and firmware can be acked immediately and hence event reception and processing are decoupled. - Events gets added to the queue by notification callback. Notification callback is expected to be atomic, since it is called from interrupt context. - Events are dequeued and processed in a worker thread. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Add support for CGX link managementLinu Cherian4-4/+668
CGX LMAC initialization, link status polling etc is done by low level secure firmware. For link management this patch adds a interface or communication mechanism between firmware and this kernel CGX driver. - Firmware interface specification is defined in cgx_fw_if.h. - Support to send/receive commands/events to/form firmware. - events/commands implemented * link up * link down * reading firmware version Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Nithya Mani <nmani@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Set RVU PFs to CGX LMACs mappingLinu Cherian5-3/+89
Each of the enabled CGX LMAC is considered a physical interface and RVU PFs are mapped to these. VFs of these SRIOV PFs will be virtual interfaces and share CGX LMAC along with PF. This mapping info will be used later on for Rx/Tx pkt steering. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Add Marvell OcteonTX2 CGX driverSunil Goutham4-2/+133
This patch adds basic template for Marvell OcteonTX2's CGX ethernet interface driver. Just the probe. RVU AF driver will use APIs exported by this driver for various things like PF to physical interface mapping, loopback mode, interface stats etc. Hence marged both drivers into a single module. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Reconfig MSIX base with IOVAGeetha sowjanya2-3/+32
HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence create a IOMMU mapping for the physcial address configured by firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Configure block LF's MSIX vector offsetSunil Goutham4-3/+357
Firmware configures a certain number of MSIX vectors to each of enabled RVU PF/VF. When a block LF is attached to a PF/VF, number of MSIX vectors needed by that LF are set aside (out of PF/VF's total MSIX vectors) and LF's msix_offset is configured in HW. Also added support for a RVU PF/VF to retrieve that block LF's MSIX vector offset information from AF via mbox. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Add RVU block LF provisioning supportSunil Goutham4-10/+523
Added support for a RVU PF/VF to request AF via mailbox to attach or detach NPA/NIX/SSO/SSOW/TIM/CPT block LFs. Also supports partial detachment and modifying current LF attached count of a certian block type. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-10octeontx2-af: Scan blocks for LFs provisioned to PF/VFSunil Goutham3-2/+178
Scan all RVU blocks to find any 'LF to RVU PF/VF' mapping done by low level firmware. If found any, mark them as used in respective block's LF bitmap and also save mapped PF/VF's PF_FUNC info. This is done to avoid reattaching a block LF to a different RVU PF/VF. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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