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2020-04-23net/mlx5: Update vport.c to new cmd interfaceLeon Romanovsky1-75/+67
Do mass update of vport.c to reuse newly introduced mlx5_cmd_exec_in*() interfaces. Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
2020-04-22dpaa2-eth: use bulk enqueue in .ndo_xdp_xmitIoana Ciornei2-29/+30
Take advantage of the bulk enqueue feature in .ndo_xdp_xmit. We cannot use the XDP_XMIT_FLUSH since the architecture is not capable to store all the frames dequeued in a NAPI cycle so we instead are enqueueing all the frames received in a ndo_xdp_xmit call right away. After setting up all FDs for the xdp_frames received, enqueue multiple frames at a time until all are sent or the maximum number of retries is hit. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: split the .ndo_xdp_xmit callback into two stagesIoana Ciornei1-36/+40
Instead of having a function that both creates a frame descriptor from an xdp_frame and enqueues it, split this into two stages. Add the dpaa2_eth_xdp_create_fd that just transforms an xdp_frame into a FD while the actual enqueue callback is called directly from the ndo for each frame. This is particulary useful in conjunction with bulk enqueue. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Acked-by: Jesper Dangaard Brouer <brouer@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: use the bulk ring mode enqueue interfaceIoana Ciornei2-14/+22
Update the dpaa2-eth driver to use the bulk enqueue function introduced with the change to QBMAN ring mode. At the moment, no functional changes are made but rather the driver just transitions to the new interface while still enqueuing just one frame at a time. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22dpaa2-eth: return num_enqueued frames from enqueue callbackIoana Ciornei2-13/+26
The enqueue dpaa2-eth callback now returns the number of successfully enqueued frames. This is a preliminary patch necessary for adding support for bulk ring mode enqueue. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: stmmac: Add support for VLAN promiscuous modeChuah, Kim Tatt3-0/+69
For dwmac4, enable VLAN promiscuity when MAC controller is requested to enter promiscuous mode. Signed-off-by: Chuah, Kim Tatt <kim.tatt.chuah@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: Tan, Tee Min <tee.min.tan@intel.com> Signed-off-by: Wong Vee Khee <vee.khee.wong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22r8169: use devm_mdiobus_registerHeiner Kallweit1-8/+2
Use new function devm_mdiobus_register() to simplify the driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: lift protocol restriction for flow_match_eth_addrs keysVladimir Oltean1-5/+0
An attempt was made in commit fe3490e6107e ("net: mscc: ocelot: Hardware ofload for tc flower filter") to avoid clashes between MAC_ETYPE rules and IP rules. Because the protocol blacklist should have included ETH_P_ALL too, it created some confusion, but now the situation should be dealt with a bit better by the patch immediately previous to this one ("net: mscc: ocelot: refine the ocelot_ace_is_problematic_mac_etype function"). So now we can remove that check. MAC_ETYPE rules with a protocol of ETH_P_IP, ETH_P_IPV6, ETH_P_ARP and ETH_P_ALL _are_ supported, with some restrictions regarding per-port exclusivity which are enforced now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: refine the ocelot_ace_is_problematic_mac_etype functionVladimir Oltean1-4/+14
The commit mentioned below was a bit too harsh, and while it restricted the invalid key combinations which are known to not work, such as: tc filter add dev swp0 ingress proto ip \ flower src_ip 192.0.2.1 action drop tc filter add dev swp0 ingress proto all \ flower src_mac 00:11:22:33:44:55 action drop it also restricted some which still should work, such as: tc filter add dev swp0 ingress proto ip \ flower src_ip 192.0.2.1 action drop tc filter add dev swp0 ingress proto 0x22f0 \ flower src_mac 00:11:22:33:44:55 action drop What actually does not match "sanely" is a MAC_ETYPE rule on frames having an EtherType of ARP, IPv4, IPv6, in addition to SNAP and OAM frames (which the ocelot tc-flower implementation does not parse yet, so the function might need to be revisited again in the future). So just make the function recognize the problematic MAC_ETYPE rules by EtherType - thus the VCAP IS2 can be forced to match even on those packets. This patch makes it possible for IP rules to live on a port together with MAC_ETYPE rules that are non-all, non-arp, non-ip and non-ipv6. Fixes: d4d0cb741d7b ("net: mscc: ocelot: deal with problematic MAC_ETYPE VCAP IS2 rules") Reported-by: Allan W. Nielsen <allan.nielsen@microchip.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-22net: mscc: ocelot: support matching on EtherTypeVladimir Oltean1-3/+19
Currently, the filter's protocol is ignored except for a few special cases (IPv4 and IPv6). The EtherType can be matched inside VCAP IS2 by using a MAC_ETYPE key. So there are 2 cases in which EtherType matches are supported: - As part of a larger MAC_ETYPE rule, such as: tc filter add dev swp0 ingress protocol ip \ flower skip_sw src_mac 42:be:24:9b:76:20 action drop - Standalone (matching on protocol only): tc filter add dev swp0 ingress protocol arp \ flower skip_sw action drop As before, if the protocol is not specified, is it implicitly "all" and the EtherType mask in the MAC_ETYPE half key is set to zero. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: stmmac: Enable SERDES power up/down sequenceVoon Weifeng3-0/+235
This patch is to enable Intel SERDES power up/down sequence. The SERDES converts 8/10 bits data to SGMII signal. Below is an example of HW configuration for SGMII mode. The SERDES is located in the PHY IF in the diagram below. <-----------------GBE Controller---------->|<--External PHY chip--> +----------+ +----+ +---+ +----------+ | EQoS | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External | | MAC | |xPCS| |IF | | PHY | +----------+ +----+ +---+ +----------+ ^ ^ ^ ^ | | | | +---------------------MDIO-------------------------+ PHY IF configuration and status registers are accessible through mdio address 0x15 which is defined as mdio_adhoc_addr. During D0, The driver will need to power up PHY IF by changing the power state to P0. Likewise, for D3, the driver sets PHY IF power state to P3. Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: broadcom: convert to devm_platform_ioremap_resource_byname()Dejin Zheng1-22/+11
Use the function devm_platform_ioremap_resource_byname() to simplify source code which calls the functions platform_get_resource_byname() and devm_ioremap_resource(). Remove also a few error messages which became unnecessary with this software refactoring. Suggested-by: Markus Elfring <Markus.Elfring@web.de> Signed-off-by: Dejin Zheng <zhengdejin5@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21e1000: remove unneeded conversion to boolJason Yan1-1/+1
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/net/ethernet/intel/e1000/e1000_main.c:1479:44-49: WARNING: conversion to bool not needed here Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21i40e: Remove unneeded conversion to boolJason Yan1-2/+2
The '==' expression itself is bool, no need to convert it to bool again. This fixes the following coccicheck warning: drivers/net/ethernet/intel/i40e/i40e_main.c:1614:52-57: WARNING: conversion to bool not needed here drivers/net/ethernet/intel/i40e/i40e_main.c:11439:52-57: WARNING: conversion to bool not needed here Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: enable PTP programmable pinYangbo Lu1-2/+4
Enable PTP programmable pin. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: support 4 PTP programmable pinsYangbo Lu1-0/+121
Support 4 PTP programmable pins with only PTP_PF_PEROUT function for now. The PTP_PF_EXTTS function will be supported in the future, and it should be implemented separately for Felix and Ocelot, because of different hardware interrupt implementation in them. Since the hardware is not able to support absolute start time, the periodic clock request only allows start time 0 0. But nsec could be accepted for PPS case for phase adjustment. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: add wave programming registers definitionsYangbo Lu1-0/+2
Add wave programming registers definitions for Ocelot platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: fix timestamp info if ptp clock does not workYangbo Lu1-0/+6
The timestamp info should be only software timestamp capabilities if ptp clock does not work. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net: mscc: ocelot: move ocelot ptp clock code out of ocelot.cYangbo Lu6-250/+230
The Ocelot PTP clock driver had been embedded into ocelot.c driver. It had supported basic gettime64/settime64/adjtime/adjfine functions by now which were used by both Ocelot switch and Felix switch. This patch is to move current ptp clock code out of ocelot.c driver maintaining as a single ocelot_ptp.c. For futher new features implementation, the common code could be put in ocelot_ptp.c and the switch specific code should be in specific switch driver. The interrupt implementation in SoC is different between Ocelot and Felix. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net/nfp: Update driver to use global kernel versionLeon Romanovsky2-5/+0
Change nfp driver to use globally defined kernel version. Reported-by: Borislav Petkov <bp@suse.de> Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21net/hns: Remove custom driver version in favour of global oneLeon Romanovsky3-11/+0
Use globally defined kernel version instead of custom driver variant. Reported-by: Borislav Petkov <bp@suse.de> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-21drivers: Remove inclusion of vermagic headerLeon Romanovsky4-4/+1
Get rid of linux/vermagic.h includes, so that MODULE_ARCH_VERMAGIC from the arch header arch/x86/include/asm/module.h won't be redefined. In file included from ./include/linux/module.h:30, from drivers/net/ethernet/3com/3c515.c:56: ./arch/x86/include/asm/module.h:73: warning: "MODULE_ARCH_VERMAGIC" redefined 73 | # define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY | In file included from drivers/net/ethernet/3com/3c515.c:25: ./include/linux/vermagic.h:28: note: this is the location of the previous definition 28 | #define MODULE_ARCH_VERMAGIC "" | Fixes: 6bba2e89a88c ("net/3com: Delete driver and module versions from 3com drivers") Co-developed-by: Borislav Petkov <bp@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Shannon Nelson <snelson@pensando.io> # ionic Acked-by: Sebastian Reichel <sre@kernel.org> # power Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Drop too many parentheses in bcmgenet_probe()Andy Shevchenko1-1/+1
No need to have parentheses around plain pointer variable or negation operator. Drop them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Use get_unligned_beXX() and put_unaligned_beXX()Andy Shevchenko1-9/+4
It's convenient to use get_unligned_beXX() and put_unaligned_beXX() helpers to get or set MAC instead of open-coded variants. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Use devm_clk_get_optional() to get the clocksAndy Shevchenko1-7/+12
Conversion to devm_clk_get_optional() makes it explicit that clocks are optional. This change allows to handle deferred probe in case clocks are defined, but not yet probed. Due to above changes bail out in error case. While here, check potential error when enable main clock. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Drop useless OF codeAndy Shevchenko1-13/+0
There is nothing which needs a set of OF headers, followed by redundant OF node ID check. Drop them for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: bcmgenet: Drop ACPI_PTR() to avoid compiler warningAndy Shevchenko1-1/+1
When compiled with CONFIG_ACPI=n, ACPI_PTR() will be no-op, and thus genet_acpi_match table defined, but not used. Compiler is not happy about such data. Drop ACPI_PTR() for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20Merge tag 'mlx5-updates-2020-04-20' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linuxDavid S. Miller17-183/+229
Saeed Mahameed says: ==================== mlx5-updates-2020-04-20 This series includes misc updates and clean ups to mlx5 driver: 1) improve some comments from Hu Haowen. 2) Handles errors of netif_set_real_num_{tx,rx}_queues, from Maxim 3) IPsec and FPGA related code cleanup to prepare for ASIC devices IPsec offloads, from Raed 4) Allow partial mask for tunnel options, from Roi. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20r8169: change wmb to smb_wmb in rtl8169_start_xmitHeiner Kallweit1-2/+2
A barrier is needed here to ensure that rtl_tx sees the descriptor changes (DescOwn set) before the updated tp->cur_tx value. Else it may wrongly assume that the transfer has been finished already. For this purpose smp_wmb() is sufficient. No separate barrier is needed for ordering the descriptor changes with the MMIO doorbell write. The needed barrier is included in the non-relaxed writel() used by rtl8169_doorbell(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net/mlx5e: Get the latest values from counters in switchdev modeZhu Yanjun1-1/+6
In the switchdev mode, when running "cat /sys/class/net/NIC/statistics/tx_packets", the ppcnt register is accessed to get the latest values. But currently this command can not get the correct values from ppcnt. From firmware manual, before getting the 802_3 counters, the 802_3 data layout should be set to the ppcnt register. When the command "cat /sys/class/net/NIC/statistics/tx_packets" is run, before updating 802_3 data layout with ppcnt register, the monitor counters are tested. The test result will decide the 802_3 data layout is updated or not. Actually the monitor counters do not support to monitor rx/tx stats of 802_3 in switchdev mode. So the rx/tx counters change will not trigger monitor counters. So the 802_3 data layout will not be updated in ppcnt register. Finally this command can not get the latest values from ppcnt register with 802_3 data layout. Fixes: 5c7e8bbb0257 ("net/mlx5e: Use monitor counters for update stats") Signed-off-by: Zhu Yanjun <yanjunz@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: Kconfig: convert imply usage to weak dependencySaeed Mahameed1-4/+4
MLX5_CORE uses the 'imply' keyword to depend on VXLAN, PTP_1588_CLOCK, MLXFW and PCI_HYPERV_INTERFACE. This was useful to force vxlan, ptp, etc.. to be reachable to mlx5 regardless of their config states. Due to the changes in the cited commit below, the semantics of 'imply' was changed to not force any restriction on the implied config. As a result of this change, the compilation of MLX5_CORE=y and VXLAN=m would result in undefined references, as VXLAN now would stay as 'm'. To fix this we change MLX5_CORE to have a weak dependency on these modules/configs and make sure they are reachable, by adding: depend on symbol || !symbol. For example: VXLAN=m MLX5_CORE=y, this will force MLX5_CORE to m Fixes: def2fbffe62c ("kconfig: allow symbols implied by y to become m") Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Cc: Masahiro Yamada <masahiroy@kernel.org> Cc: Nicolas Pitre <nico@fluxnic.net> Cc: Arnd Bergmann <arnd@arndb.de> Reported-by: Randy Dunlap <rdunlap@infradead.org>
2020-04-20net/mlx5e: Don't trigger IRQ multiple times on XSK wakeup to avoid WQ overrunsMaxim Mikityanskiy4-5/+15
XSK wakeup function triggers NAPI by posting a NOP WQE to a special XSK ICOSQ. When the application floods the driver with wakeup requests by calling sendto() in a certain pattern that ends up in mlx5e_trigger_irq, the XSK ICOSQ may overflow. Multiple NOPs are not required and won't accelerate the process, so avoid posting a second NOP if there is one already on the way. This way we also avoid increasing the queue size (which might not help anyway). Fixes: db05815b36cb ("net/mlx5e: Add XSK zero-copy support") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: CT: Change idr to xarray to protect parallel tuple id allocationPaul Blakey1-11/+12
After allowing parallel tuple insertion, we get the following trace: [ 5505.142249] ------------[ cut here ]------------ [ 5505.148155] WARNING: CPU: 21 PID: 13313 at lib/radix-tree.c:581 delete_node+0x16c/0x180 [ 5505.295553] CPU: 21 PID: 13313 Comm: kworker/u50:22 Tainted: G OE 5.6.0+ #78 [ 5505.304824] Hardware name: Supermicro Super Server/X10DRT-P, BIOS 2.0b 03/30/2017 [ 5505.313740] Workqueue: nf_flow_table_offload flow_offload_work_handler [nf_flow_table] [ 5505.323257] RIP: 0010:delete_node+0x16c/0x180 [ 5505.349862] RSP: 0018:ffffb19184eb7b30 EFLAGS: 00010282 [ 5505.356785] RAX: 0000000000000000 RBX: ffff904ac95b86d8 RCX: ffff904b6f938838 [ 5505.365190] RDX: 0000000000000000 RSI: ffff904ac954b908 RDI: ffff904ac954b920 [ 5505.373628] RBP: ffff904b4ac13060 R08: 0000000000000001 R09: 0000000000000000 [ 5505.382155] R10: 0000000000000000 R11: 0000000000000040 R12: 0000000000000000 [ 5505.390527] R13: ffffb19184eb7bfc R14: ffff904b6bef5800 R15: ffff90482c1203c0 [ 5505.399246] FS: 0000000000000000(0000) GS:ffff904c2fc80000(0000) knlGS:0000000000000000 [ 5505.408621] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 5505.415739] CR2: 00007f5d27006010 CR3: 0000000058c10006 CR4: 00000000001626e0 [ 5505.424547] Call Trace: [ 5505.428429] idr_alloc_u32+0x7b/0xc0 [ 5505.433803] mlx5_tc_ct_entry_add_rule+0xbf/0x950 [mlx5_core] [ 5505.441354] ? mlx5_fc_create+0x23c/0x370 [mlx5_core] [ 5505.448225] mlx5_tc_ct_block_flow_offload+0x874/0x10b0 [mlx5_core] [ 5505.456278] ? mlx5_tc_ct_block_flow_offload+0x63d/0x10b0 [mlx5_core] [ 5505.464532] nf_flow_offload_tuple.isra.21+0xc5/0x140 [nf_flow_table] [ 5505.472286] ? __kmalloc+0x217/0x2f0 [ 5505.477093] ? flow_rule_alloc+0x1c/0x30 [ 5505.482117] flow_offload_work_handler+0x1d0/0x290 [nf_flow_table] [ 5505.489674] ? process_one_work+0x17c/0x580 [ 5505.494922] process_one_work+0x202/0x580 [ 5505.500082] ? process_one_work+0x17c/0x580 [ 5505.505696] worker_thread+0x4c/0x3f0 [ 5505.510458] kthread+0x103/0x140 [ 5505.514989] ? process_one_work+0x580/0x580 [ 5505.520616] ? kthread_bind+0x10/0x10 [ 5505.525837] ret_from_fork+0x3a/0x50 [ 5505.570841] ---[ end trace 07995de9c56d6831 ]--- This happens from parallel deletes/adds to idr, as idr isn't protected. Fix that by using xarray as the tuple_ids allocator instead of idr. Fixes: 7da182a998d6 ("netfilter: flowtable: Use work entry per offload command") Reviewed-by: Roi Dayan <roid@mellanox.com> Signed-off-by: Paul Blakey <paulb@mellanox.com> Reviewed-by: Oz Shlomo <ozsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: Fix failing fw tracer allocation on s390Niklas Schnelle1-3/+3
On s390 FORCE_MAX_ZONEORDER is 9 instead of 11, thus a larger kzalloc() allocation as done for the firmware tracer will always fail. Looking at mlx5_fw_tracer_save_trace(), it is actually the driver itself that copies the debug data into the trace array and there is no need for the allocation to be contiguous in physical memory. We can therefor use kvzalloc() instead of kzalloc() and get rid of the large contiguous allcoation. Fixes: f53aaa31cce7 ("net/mlx5: FW tracer, implement tracer logic") Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: improve some commentsHu Haowen1-1/+1
Replaced "its" with "it's". Signed-off-by: Hu Haowen <xianfengting221@163.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: Read embedded cpu bit only onceParav Pandit1-2/+1
Embedded CPU bit doesn't change with PCI resume/suspend. Hence read it only once while probing the PCI device. Signed-off-by: Parav Pandit <parav@mellanox.com> Reviewed-by: Bodong Wang <bodong@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5e: Handle errors from netif_set_real_num_{tx,rx}_queuesMaxim Mikityanskiy2-13/+48
netif_set_real_num_tx_queues and netif_set_real_num_rx_queues may fail. Now that mlx5e supports handling errors in the preactivate hook, this commit leverages that functionality to handle errors from those functions and roll back all changes on failure. Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5e: Allow partial data mask for tunnel optionsRoi Dayan1-10/+22
We use mapping to save and restore the tunnel options. Save also the tunnel options mask. Signed-off-by: Roi Dayan <roid@mellanox.com> Reviewed-by: Paul Blakey <paulb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5e: Set of completion request bit should not clear other adjacent bitsTariq Toukan1-1/+1
In notify HW (ring doorbell) flow, we set the bit to request a completion on the TX descriptor. When doing so, we should not unset other bits in the same byte. Currently, this does not fix a real issue, as we still don't have a flow where both MLX5_WQE_CTRL_CQ_UPDATE and any adjacent bit are set together. Fixes: 542578c67936 ("net/mlx5e: Move helper functions to a new txrx datapath header") Fixes: 864b2d715300 ("net/mlx5e: Generalize tx helper functions for different SQ types") Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Reviewed-by: Aya Levin <ayal@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: IPsec, Refactor SA handle creation and destructionRaed Salem5-48/+63
Currently the SA handle is created and managed as part of the common code for different IPsec supporting HW, this handle is passed to HW to be used on Rx to identify the SA handle that was used to return the xfrm state to stack. The above implementation pose a limitation on managing this handle. Refactor by moving management of this field to the specific HW code. Downstream patches will introduce the Connect-X support for IPsec that will use this handle differently than current implementation. Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Boris Pismenny <borisp@mellanox.com> Reviewed-by: Huy Nguyen <huyn@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5e: IPSec, Expose IPsec HW stat only for supporting HWRaed Salem4-85/+57
The current HW counters are supported only by Innova, split the ipsec stats group into two groups, one for HW and one for SW. And expose the HW counters to ethtool only if Innova HW is used for IPsec offload. Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Huy Nguyen <huyn@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: Refactor mlx5_accel_esp_create_hw_context parameter listRaed Salem3-28/+25
Currently the FPGA IPsec is the only hw implementation of the IPsec acceleration api, and so the mlx5_accel_esp_create_hw_context was wrongly made to suit this HW api, among other in its parameter list and some of its parameter endianness. This implementation might not be suitable for different HW. Refactor by group and pass all function arguments of mlx5_accel_esp_create_hw_context in common mlx5_accel_esp_xfrm_attrs struct field of mlx5_accel_esp_xfrm struct and correct the endianness according to the HW being called. Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Boris Pismenny <borisp@mellanox.com> Reviewed-by: Huy Nguyen <huyn@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5e: en_accel, Add missing net/geneve.h includeRaed Salem1-0/+2
The cited commit relies on include <net/geneve.h> being included implicitly prior to include "en_accel/en_accel.h". This mandates that all files that needs to include en_accel.h to redantantly include net/geneve.h. Include net/geneve.h explicitly at "en_accel/en_accel.h" to avoid undesired constrain as above. Fixes: e3cfc7e6b7bd ("net/mlx5e: TX, Add geneve tunnel stateless offload support") Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20net/mlx5: Use the correct IPsec capability function for FPGA opsRaed Salem3-4/+18
Currently the IPsec acceleration capability function is also used at IPsec fpga capable device code. This could cause a future bug as the acceleration layer is agnostic to the device implementing its API. Fix by using the IPsec FPGA capability function instead of acceleration layer capability function in case of FPGA IPsec only related operations. Downstream patches will add support for Connect-X IPsec, this can avoid a future bug. Signed-off-by: Raed Salem <raeds@mellanox.com> Reviewed-by: Boris Pismenny <borisp@mellanox.com> Reviewed-by: Huy Nguyen <huyn@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2020-04-20cxgb4: fix large delays in PTP synchronizationRahul Lakkireddy2-21/+9
Fetching PTP sync information from mailbox is slow and can take up to 10 milliseconds. Reduce this unnecessary delay by directly reading the information from the corresponding registers. Fixes: 9c33e4208bce ("cxgb4: Add PTP Hardware Clock (PHC) support") Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20qed: use true,false for bool variablesJason Yan1-2/+2
Fix the following coccicheck warning: drivers/net/ethernet/qlogic/qed/qed_dev.c:4395:2-34: WARNING: Assignment of 0/1 to bool variable drivers/net/ethernet/qlogic/qed/qed_dev.c:1975:2-34: WARNING: Assignment of 0/1 to bool variable Signed-off-by: Jason Yan <yanaijie@huawei.com> Acked-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: hns3: add trace event support for PF/VF mailboxYufeng Mo6-0/+190
This patch adds trace event support for PF/VF mailbox. Signed-off-by: Yufeng Mo <moyufeng@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: hns3: add support for dumping MAC reg in debugfsYufeng Mo2-1/+114
This patch adds support for dumping MAC reg in debugfs, which will be helpful for debugging. Signed-off-by: Yufeng Mo <moyufeng@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: hns3: add debug information for flow table when failedGuojia Liao1-11/+34
Adds some debug information for failures of processing flow table, removes the redundant printing when hclge_fd_check_spec() returns error, and modifies the printing level for FD not enable error. Signed-off-by: Guojia Liao <liaoguojia@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-20net: hns3: clean up some coding style issueHuazhong Tan2-8/+4
This patch removes some unnecessary blank lines, redundant parentheses, and changes one tab to blank in hclge_dbg_dump_reg_common(). Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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