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path: root/drivers/net/ethernet
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2021-10-04net/mlx5: Bridge, mark reg_c1 when pushing VLANVlad Buslov2-1/+40
On ingress VLAN push also assign value 0x7FE to reg_c1 tunnel id+opts bits (tunnel id 0, which is not a valid tunnel id, and option 0x7FE which was reserved by one of previous patches in the series). In following patch the reg value is matched on egress miss to restore the packet to its original state by removing the VLAN before passing it to the software data path. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5: Bridge, extract VLAN pop code to dedicated functionsVlad Buslov1-12/+22
Following patches in series need to pop VLAN when packet misses on egress. To reuse existing bridge VLAN pop handling code, extract it to dedicated helpers mlx5_esw_bridge_pkt_reformat_vlan_pop_supported() and mlx5_esw_bridge_pkt_reformat_vlan_pop_create(). Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5: Bridge, refactor eswitch instance usageVlad Buslov1-11/+14
Several functions in bridge.c excessively obtain pointer to parent eswitch instance by dereferencing br_offloads->esw on every usage and following patches in this series add even more usages of eswitch. Introduce local variable 'esw' and use it instead. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Support accept actionVlad Buslov4-4/+17
Support TC generic 'accept' action in mlx5 by introducing MLX5_ESW_ATTR_FLAG_ACCEPT attribute flag. Flag has similar semantics to existing MLX5_ESW_ATTR_FLAG_SLOW_PATH flag, however, dedicated flag is required because existing 'slow path' flag can be flipped by tunneling subsystem when neighbor changes state. Introduce new helper function mlx5_esw_attr_flags_skip() to check whether attribute flags for 'slow path' or 'accept' action are set and use it in eswitch code instead of direct bit manipulation. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Specify out ifindex when looking up encap routeChris Mi3-0/+18
There is a use case that the local and remote VTEPs are in the same host. Currently, the out ifindex is not specified when looking up the encap route for offloads. So in this case, a local route is returned and the route dev is lo. Actual tunnel interface can be created with a parameter "dev" [1], which specifies the physical device to use for tunnel endpoint communication. Pass this parameter to driver when looking up encap route for offloads. So that a unicast route will be returned. [1] ip link add name vxlan1 type vxlan id 100 dev enp4s0f0 remote 1.1.1.1 dstport 4789 Signed-off-by: Chris Mi <cmi@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Reserve a value from TC tunnel options mappingVlad Buslov1-2/+4
Reserve one more value from TC tunnel options range to be used by bridge offload in following patches. Signed-off-by: Vlad Buslov <vladbu@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Move parse fdb check into actions_match_supported_fdb()Roi Dayan1-9/+11
The parse fdb/nic actions funcs parse the actions and then call actions_match_supported() for final check. Move related check in parse_tc_fdb_actions() into actions_match_supported_fdb() for more organized code. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Split actions_match_supported() into a sub functionRoi Dayan1-26/+39
There will probably be more checks, some for nic flows, some for fdb flows and some are shared checks. Split it for fdb and nic to avoid the function getting too big. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Move mod hdr allocation to a single placeRoi Dayan1-36/+51
Move mod hdr allocation chunk from parse_tc_fdb_actions() and parse_tc_nic_actions() to a shared function. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Maor Dickman <maord@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: TC, Refactor sample offload error flowRoi Dayan1-16/+5
Refactor sample unoffload to be symmetric to sample offload. Use the existing del_post_rule() to release the post rule. Also mlx5e_tc_sample_unoffload() should not return post_rule which is NULL when post actions are supported. Sample offload works with this NULL because many places of the code use IS_ERR() instead of IS_ERR_OR_NULL() to check rule is valid and when rule is detected as sample offload the code is not using the rule. Let's be persistent and avoid returning NULL anyway and return the pre rule, like in CT case, which is not NULL. Signed-off-by: Roi Dayan <roid@nvidia.com> Reviewed-by: Chris Mi <cmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Add TX max rate support for MQPRIO channel modeTariq Toukan4-6/+203
Add driver max_rate support for the MQPRIO bw_rlimit shaper in channel mode. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04net/mlx5e: Specify SQ stats struct for mlx5e_open_txqsq()Tariq Toukan3-8/+9
Let the caller of mlx5e_open_txqsq() directly pass the SQ stats structure pointer. This replaces logic involving the qos_queue_group_id parameter, and helps generalizing its role in the next patch. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Maxim Mikityanskiy <maximmi@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-10-04Merge tag 'v5.15-rc4' into rdma.get for-nextJason Gunthorpe42-210/+310
Merged due to dependencies in following patches. Conflict in drivers/infiniband/hw/hfi1/ipoib_tx.c resolved by hand to take the %p change and txq stats rename together. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-10-04net: ethernet: use phylink_set_10g_modes()Russell King (Oracle)3-18/+3
Update three drivers to use the new phylink_set_10g_modes() helper: Cadence macb, Freescale DPAA2 and Marvell PP2. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: fix ll2 establishment during load of RDMA driverManish Chopra1-5/+44
If stats ID of a LL2 (light l2) queue exceeds than the total amount of statistics counters, it may cause system crash upon enabling RDMA on all PFs. This patch makes sure that the stats ID of the LL2 queue doesn't exceed the max allowed value. Signed-off-by: Manish Chopra <manishc@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update the TCP active termination 2 MSL timer ("TIME_WAIT")Prabhakar Kushwaha1-0/+1
Initialize 2 MSL timeout value used for the TCP TIME_WAIT state to non-zero default. This patch also removes magic number from qedi/qedi_main.c. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update TCP silly-window-syndrome timeout for iwarp, scsiNikolay Assa1-0/+1
Update TCP silly-window-syndrome timeout, for the cases where initiator's small TCP window size prevents FW from transmitting packets on the connection. Timeout causes FW to retransmit window probes if needed, preventing I/O stall if initiator ignores first window probe. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Signed-off-by: Nikolay Assa <nassa@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update debug related changesPrabhakar Kushwaha8-505/+1031
qed_debug features are updated to support FW version 8.59.1.0 along with few enhancements. - Removal of _BB_K2 from register defines. - Add new condition cond14. - Add dump of new area sw-platform, epoch, iscsi_task_pages, fcoe_task_pages, roce_task_pages and eth_task_pages. - Introduced new functions qed_dbg_phy_size(). - Update in qed_mcp_nvm_rd_cmd() declaration. - Allow QED to control init/exit at pf level. - Dump partial "ILT-dump" if buffer size is not sufficient. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Add '_GTT' suffix to the IRO RAM macrosPrabhakar Kushwaha10-111/+143
GTT (Global translation table) is a fast-access window in the BAR into the register space, which only maps certain register addresses. This change helps enforce that only those addresses which are indeed mapped by the GTT are being accessed through it. Adding the '_GTT' suffix to the IRO FW memory (“RAM”) macros that access GTT-able region in FW memories (“RAM”) and use GTT macros to access RAM BAR from drivers. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update FW init functions to support FW 8.59.1.0Omkar Kulkarni6-200/+372
The qed_init_fw_func.c and qed_init_ops.c updated to support FW version 8.59.1.0. - Support 16-bit VPORT WFQ (weighted fair queueing) weights. - Support WFQ (weighted fair queueing) weight per VPORT + TC. - Support allocation of Tx PQs(physical queues) per PF,VF. - Modify Global RL (rate limiter) upper bound configuration. - Update FW operation functions. - Update iro_arr[] array. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Use enum as per FW 8.59.1.0 in qed_iro_hsi.hPrabhakar Kushwaha1-257/+390
qed_iro_hsi.h contains HSI changes related to storm memories access. Existing code is based on hard-coded index. Use enum as defined for FW HSI 8.59.1.0, instead of hard-coded index. This patch also removes unnecessary header file inclusion. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_hsi.h for fw 8.59.1.0Prabhakar Kushwaha10-307/+1587
The qed_hsi.h has been updated to support new FW version 8.59.1.0 with changes. - Updates FW HSI (Hardware Software interface) structures. - Addition/update in function declaration and defines as per HSI. - Add generic infrastructure for FW error reporting as part of common event queue handling. - Move malicious VF error reporting to FW error reporting infrastructure. - Move consolidation queue initialization from FW context to ramrod message. qed_hsi.h header file changes lead to change in many files to ensure compilation. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update qed_mfw_hsi.h for FW ver 8.59.1.0Prabhakar Kushwaha3-256/+793
The qed_mfw_hsi.h contains HSI (Hardware Software Interface) changes related to management firmware. It has been updated to support new FW version 8.59.1.0 with below changes. - New defines for VF bitmap. - fec_mode and extended_speed defines updated in struct eth_phy_cfg. - Updated structutres lldp_system_tlvs_buffer_s, public_global, public_port, public_func, drv_union_data, public_drv_mb with all dependent new structures. - Updates in NVM related structures and defines. - Msg defines are added in enum drv_msg_code and fw_msg_code. - Updated/added new defines. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Update common_hsi for FW ver 8.59.1.0Prabhakar Kushwaha1-1/+1
The common_hsi.h has been updated for FW version 8.59.1.0 with below changes. - FW and Tools version. - New structures related to search table, packet duplication. - Structure for doorbell address for legacy mode without DEM. - Enhanced union rdma_eqe_data for RoCE Suspend Event Data. - New defines. This patch also fixes the existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Split huge qed_hsi.h header fileOmkar Kulkarni23-3747/+3794
The qed_hsi.h is a huge header file containing HSI (Hardware Software Interface) definitions of storm memory access, debug related, general and management firmware specific. In order to have a better code-organization HSI definition, this patch split the code across multiple files, i.e. - storm memory access HSI : qed_iro_hsi.h - debug related HSI : qed_dbg_hsi.h - Management firmware HSI : qed_mfg_hsi.h - General HSI : qed_hsi.h In addition, this patch also fixes existing checkpatch warnings and few important checks. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Remove e4_ and _e4 from FW HSIShai Malin14-3451/+3444
The existing qed/qede/qedr/qedi/qedf code uses chip-specific naming in structures, functions, variables and defines in FW HSI (Hardware Software Interface). The new FW version introduced a generic naming convention in HSI in-which the same code will be used across different versions for simpler maintainability. It also eases in providing support for new features. With this patch every "_e4" or "e4_" prefix or suffix is not needed anymore and it will be removed. Reviewed-by: Manish Rangankar <mrangankar@marvell.com> Reviewed-by: Javed Hasan <jhasan@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04qed: Fix kernel-doc warningsPrabhakar Kushwaha16-1708/+1930
This patch fixes all the qed and qede kernel-doc warnings according to the guidelines that are described in Documentation/doc-guide/kernel-doc.rst. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-04net/mlx4_en: avoid one cache line miss to ring doorbellEric Dumazet2-2/+3
This patch caches doorbell address directly in struct mlx4_en_tx_ring. This removes the need to bring in cpu caches whole struct mlx4_uar in fast path. Note that mlx4_uar is not guaranteed to be on a local node, because mlx4_bf_alloc() uses a single free list (priv->bf_list) regardless of its node parameter. This kind of change does matter in presence of light/moderate traffic. In high stress, this read-only line would be kept hot in caches. Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ethernet: use eth_hw_addr_set() - castsJakub Kicinski3-3/+3
eth_hw_addr_set() takes a u8 pointer, like other etherdevice helpers. Convert the few drivers which require casts because they memcpy from "endian marked" types. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ethernet: s2io: use eth_hw_addr_set()Jakub Kicinski1-1/+1
Manual conversions because we need to get to the member which is inside an array to have a u8 pointer which eth_hw_addr_set() expects. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ethernet: chelsio: use eth_hw_addr_set()Jakub Kicinski5-6/+7
Convert chelsio drivers from memcpy() and ether_addr_copy() to eth_hw_addr_set(). They lack includes. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ethernet: use eth_hw_addr_set() instead of ether_addr_copy()Jakub Kicinski56-78/+76
Convert Ethernet from ether_addr_copy() to eth_hw_addr_set(): @@ expression dev, np; @@ - ether_addr_copy(dev->dev_addr, np) + eth_hw_addr_set(dev, np) Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ethernet: use eth_hw_addr_set()Jakub Kicinski62-84/+82
Convert all Ethernet drivers from memcpy(... ETH_ADDR) to eth_hw_addr_set(): @@ expression dev, np; @@ - memcpy(dev->dev_addr, np, ETH_ALEN) + eth_hw_addr_set(dev, np) Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02net: mscc: ocelot: write full VLAN TCI in the injection headerVladimir Oltean1-1/+1
The VLAN TCI contains more than the VLAN ID, it also has the VLAN PCP and Drop Eligibility Indicator. If the ocelot driver is going to write the VLAN header inside the DSA tag, it could just as well write the entire TCI. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02net: mscc: ocelot: support egress VLAN rewriting via VCAP ES0Vladimir Oltean1-20/+105
Currently the ocelot driver does support the 'vlan modify' action, but in the ingress chain, and it is offloaded to VCAP IS1. This action changes the classified VLAN before the packet enters the bridging service, and the bridging works with the classified VLAN modified by VCAP IS1. That is good for some use cases, but there are others where the VLAN must be modified at the stage of the egress port, after the packet has exited the bridging service. One example is simulating IEEE 802.1CB active stream identification filters ("active" means that not only the rule matches on a packet flow, but it is also able to change some headers). For example, a stream is replicated on two egress ports, but they must have different VLAN IDs on egress ports A and B. This seems like a task for the VCAP ES0, but that currently only supports pushing the ES0 tag A, which is specified in the rule. Pushing another VLAN header is not what we want, but rather overwriting the existing one. It looks like when we push the ES0 tag A, it is actually possible to not only take the ES0 tag A's value from the rule itself (VID_A_VAL), but derive it from the following formula: ES0_TAG_A = Classified VID + VID_A_VAL Otherwise said, ES0_TAG_A can be used to increment with a given value the VLAN ID that the packet was already classified to, and the packet will have this value as an outer VLAN tag. This new VLAN ID value then gets stripped on egress (or not) according to the value of the native VLAN from the bridging service. While the hardware will happily increment the classified VLAN ID for all packets that match the ES0 rule, in practice this would be rather insane, so we only allow this kind of ES0 action if the ES0 filter contains a VLAN ID too, so as to restrict the matching on a known classified VLAN. If we program VID_A_VAL with the delta between the desired final VLAN (ES0_TAG_A) and the classified VLAN, we obtain the desired behavior. It doesn't look like it is possible with the tc-vlan action to modify the VLAN ID but not the PCP. In hardware it is possible to leave the PCP to the classified value, but we unconditionally program it to overwrite it with the PCP value from the rule. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: add lif param to ionic_qcq_disableShannon Nelson1-12/+12
Add the lif parameter for use in an error message, and to better match the style of most of the functions calls. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: have ionic_qcq_disable decide on sending to hardwareShannon Nelson1-19/+20
Simplify the code a little by keeping the send_to_hw decision inside of ionic_qcq_disable rather than in the callers. Also, add ENXIO to the decision expression. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: add polling to adminq waitShannon Nelson2-6/+31
Split the adminq wait into smaller polling periods in order to watch for broken firmware and not have to wait for the full adminq devcmd_timeout. Generally, adminq commands take fewer than 2 msecs. If the FW is busy they can take longer, but usually still under 100 msecs. We set the polling period to 100 msecs in order to start snooping on FW status when a command is taking longer than usual. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: widen queue_lock use around lif init and deinitShannon Nelson1-3/+11
Widen the coverage of the queue_lock to be sure the lif init and lif deinit actions are protected. This addresses a hang seen when a Tx Timeout action was attempted at the same time as a FW Reset was started. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: move lif mutex setup and deleteShannon Nelson1-5/+10
Move creation and deletion of lif mutex a level out to lif creation and delete, rather than in init and deinit. This assures that nothing will get hung if anything is waiting on the mutex while the driver is clearing the lif while handling the fw_down/fw_up cycle. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: check for binary values in FW ver stringShannon Nelson1-3/+14
If the PCI connection is broken, reading the FW version string will only get 0xff bytes, which shouldn't get printed. This checks the first byte and prints only the first 4 bytes if non-ASCII. Also, add a limit to the string length printed when a valid string is found, just in case it is not properly terminated. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ionic: remove debug statsShannon Nelson7-225/+0
These debug stats are not really useful, their collection is likely detrimental to performance, and they suck up a lot of memory which never gets used if no one ever enables the priv-flag to print them, so just remove these bits. Signed-off-by: Shannon Nelson <snelson@pensando.io> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Initialize GbEthernet E-MACBiju Das2-13/+62
Initialize GbEthernet E-MAC found on RZ/G2L SoC. This patch also renames ravb_set_rate to ravb_set_rate_rcar and ravb_rcar_emac_init to ravb_emac_init_rcar to be consistent with the naming convention used in sh_eth driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Add half_duplex to struct ravb_hw_infoBiju Das2-8/+31
RZ/G2L supports half duplex mode. Add a half_duplex hw feature bit to struct ravb_hw_info for supporting half duplex mode for RZ/G2L. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Add magic_pkt to struct ravb_hw_infoBiju Das2-1/+5
E-MAC on R-Car supports magic packet detection, whereas RZ/G2L does not support this feature. Add magic_pkt to struct ravb_hw_info and enable this feature only for R-Car. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Add tsrq to struct ravb_hw_infoBiju Das2-2/+8
R-Car AVB-DMAC has 4 Transmit start request queues, whereas RZ/G2L has only 1 Transmit start request queue. Add a tsrq variable to struct ravb_hw_info to handle this difference. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Exclude gPTP feature support for RZ/G2LBiju Das1-36/+49
R-Car supports gPTP feature whereas RZ/G2L does not support it. This patch excludes gtp feature support for RZ/G2L. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Initialize GbEthernet DMACBiju Das2-2/+31
Initialize GbEthernet DMAC found on RZ/G2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Add support for RZ/G2L SoCBiju Das2-0/+64
RZ/G2L SoC has Gigabit Ethernet IP consisting of Ethernet controller (E-MAC), Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory access controller (DMAC). This patch adds compatible string for RZ/G2L and fills up the ravb_hw_info struct. Function stubs are added which will be used by gbeth_hw_info and will be filled incrementally. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-02ravb: Add nc_queue to struct ravb_hw_infoBiju Das2-49/+94
R-Car supports network control queue whereas RZ/G2L does not support it. Add nc_queue to struct ravb_hw_info, so that NC queue is handled only by R-Car. This patch also renames ravb_rcar_dmac_init to ravb_dmac_init_rcar to be consistent with the naming convention used in sh_eth driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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