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2021-05-29octeontx2-af: Update the default KPU profile and fixesGeorge Cherian2-848/+2908
Add support for parsing following 1. NGIO 2. PPPOE 3. 24 byte custom L2 header 4. CPT Header 5. Fragmented CPT packets 6. VLAN EXDSA Fix for 1. EDSA VLAN parsing 2. Enhance FDSA 3. CPT Header parsing Remove ITAG support Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-29octeontx2-af: support for coalescing KPU profilesHarman Kalra2-15/+79
Adding support to load a new type of KPU image, known as coalesced/ consolidated KPU image via firmware database. This image is a consolidation of multiple KPU profiles into a single image. During kernel bootup this coalesced image will be read via firmware database and only the relevant KPU profile will be loaded. Existing functionality of loading single KPU/MKEX profile is intact as the images are differentiated based on the image signature. Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-29octeontx2-af: adding new lt def registers supportHarman Kalra5-4/+112
CN10k introduces following new LT DEF registers: 1. APAD (alignment padding) LT DEF registers are enhancement to existing apad calculation algorithm where not just ipv4 and ipv6 but also other protocols can be matched and required alignment can be added by NIX. 2. ET LT DEF register defines layer information in NPC_RESULT_S to identify the Ethertype location in L2 header. Used for Ethertype overwriting in inline IPsec flow. This patch adds required structures and some header changes. Also strict version check (based on minor field) is imposed to highlight version mismatch between the kernel headers and KPU profile. Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com> Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-29octeontx2-af: load NPC profile via firmware databaseHarman Kalra2-17/+101
Currently NPC profile (KPU + MKEX) can be loaded using firmware binary in filesystem scheme. Enhancing the functionality to load NPC profile image from system firmware database. It uses the same technique as used for loading MKEX profile. Firstly firmware binary in kernel is checked for a valid image else tries to load NPC profile from firmware database and at last uses default profile if no proper image found. Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-29octeontx2-af: add support for custom KPU entriesStanislaw Kardach5-40/+286
Add ability to load a set of custom KPU entries. This allows for flexible support for custom protocol parsing. AF driver will attempt to load the profile and verify if it can fit hardware capabilities. If not, it will revert to the built-in profile. Next it will replace the first KPU_MAX_CST_LT (2) entries in each KPU in default profile with entries read from the profile image. The built-in profile should always contain KPU_MAX_CSR_LT first no-match entries and AF driver will disable those in the KPU unless custom profile is loaded. Profile file contains also a list of default protocol overrides to allow for custom protocols to be used there. Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28i40e: Register auxiliary devices to provide RDMAShiraz Saleem4-20/+114
Convert i40e to use the auxiliary bus infrastructure to export the RDMA functionality of the device to the RDMA driver. Register i40e client auxiliary RDMA device on the auxiliary bus per PCIe device function for the new auxiliary rdma driver (irdma) to attach to. The global i40e_register_client and i40e_unregister_client symbols will be obsoleted once irdma replaces i40iw in the kernel for the X722 device. Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-05-28ice: Register auxiliary device to provide RDMADave Ertman4-4/+87
Register ice client auxiliary RDMA device on the auxiliary bus per PCIe device function for the auxiliary driver (irdma) to attach to. It allows to realize a single RDMA driver (irdma) capable of working with multiple netdev drivers over multi-generation Intel HW supporting RDMA. There is no load ordering dependencies between ice and irdma. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-05-28ice: Implement iidc operationsDave Ertman13-24/+639
Add implementations for supporting iidc operations for device operation such as allocation of resources and event notifications. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-05-28ice: Initialize RDMA supportDave Ertman10-9/+183
Probe the device's capabilities to see if it supports RDMA. If so, allocate and reserve resources to support its operation; populate structures with initial values. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2021-05-28ehea: fix error return code in ehea_restart_qps()Zhen Lei1-4/+5
Fix to return -EFAULT from the error handling case instead of 0, as done elsewhere in this function. By the way, when get_zeroed_page() fails, directly return -ENOMEM to simplify code. Fixes: 2c69448bbced ("ehea: DLPAR memory add fix") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20210528085555.9390-1-thunder.leizhen@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28r8169: Fix fall-through warning for ClangGustavo A. R. Silva1-0/+1
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Acked-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://lore.kernel.org/r/20210528202327.GA39994@embeddedor Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: stmmac: the XPCS obscures a potential "PHY not found" errorVladimir Oltean1-6/+15
stmmac_mdio_register() has logic to search for PHYs on the MDIO bus and assign them IRQ lines, as well as to set priv->plat->phy_addr. If no PHY is found, the "found" variable remains set to 0 and the function errors out. After the introduction of commit f213bbe8a9d6 ("net: stmmac: Integrate it with DesignWare XPCS"), the "found" variable was immediately reused for searching for a PCS on the same MDIO bus. This can result in 2 types of potential problems (none of them seems to be seen on the only Intel system that sets has_xpcs = true, otherwise it would have been reported): 1. If a PCS is found but a PHY is not, then the code happily exits with no error. One might say "yes, but this is not possible, because of_mdiobus_register will probe a PHY for all MDIO addresses, including for the XPCS, so if an XPCS exists, then a PHY certainly exists too". Well, that is not true, see intel_mgbe_common_data(): /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; 2. A PHY is found but an MDIO device with the XPCS PHY ID isn't, and in that case, the error message will be "No PHY found". Confusing. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://lore.kernel.org/r/20210527155959.3270478-1-olteanv@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: remove unnecessary out of memory messagePeng Li1-3/+2
This patch removes unnecessary out of memory message, to fix the following checkpatch.pl warning: "WARNING: Possible unnecessary 'out of memory' message" Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: remove redundant braces {}Peng Li1-3/+3
This patch removes redundant braces {}, to fix the checkpatch.pl warning: "braces {} are not necessary for any arm of this statement" Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: add braces {} to all arms of the statementPeng Li1-4/+6
Braces {} should be used on all arms of this statement. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: remove space after '!'Peng Li1-2/+2
According to the chackpatch.pl, space prohibited after that '!'. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: code indent use tabs where possiblePeng Li1-4/+4
Code indent should use tabs where possible. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: move out assignment in if conditionPeng Li1-4/+8
Should not use assignment in if condition. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: add some required spacesPeng Li1-3/+4
Add spaces required after that close brace '}'. Add spaces required before the open parenthesis '('. Add spaces required after that ','. Add spaces required around that '='. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: fix an code style issue about "foo* bar"Peng Li1-2/+2
Fix the checkpatch error as "foo* bar" and should be "foo *bar", and "(foo*)" should be "(foo *)". Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: add blank line after declarationsPeng Li1-0/+3
This patch fixes the checkpatch error about missing a blank line after declarations. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-28net: hdlc_fr: remove redundant blank linesPeng Li1-42/+0
This patch removes some redundant blank lines. Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27Merge tag 'mlx5-updates-2021-05-26' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linuxJakub Kicinski17-186/+306
Saeed Mahameed says: ==================== mlx5-updates-2021-05-26 Misc update for mlx5 driver, 1) Clean up patches for lag and SF 2) Reserve bit 31 in steering register C1 for IPSec offload usage 3) Move steering tables pool logic into the steering core and increase the maximum table size to 2G entries when software steering is enabled. * tag 'mlx5-updates-2021-05-26' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5: Fix lag port remapping logic net/mlx5: Use boolean arithmetic to evaluate roce_lag net/mlx5: Remove unnecessary spin lock protection net/mlx5: Cap the maximum flow group size to 16M entries net/mlx5: DR, Set max table size to 2G entries net/mlx5: Move chains ft pool to be used by all firmware steering net/mlx5: Move table size calculation to steering cmd layer net/mlx5: Add case for FS_FT_NIC_TX FT in MLX5_CAP_FLOWTABLE_TYPE net/mlx5: DR, Remove unused field of send_ring struct net/mlx5e: RX, Remove unnecessary check in RX CQE compression handling net/mlx5e: IPsec/rep_tc: Fix rep_tc_update_skb drops IPsec packet net/mlx5e: TC: Reserved bit 31 of REG_C1 for IPsec offload net/mlx5e: TC: Use bit counts for register mapping net/mlx5: CT: Avoid reusing modify header context for natted entries net/mlx5e: CT, Remove newline from ct_dbg call ==================== Link: https://lore.kernel.org/r/20210527185624.694304-1-saeed@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27ixgbe: Fix out-bounds warning in ixgbe_host_interface_command()Gustavo A. R. Silva1-9/+7
Replace union with a couple of pointers in order to fix the following out-of-bounds warning: CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o drivers/net/ethernet/intel/ixgbe/ixgbe_common.c: In function ‘ixgbe_host_interface_command’: drivers/net/ethernet/intel/ixgbe/ixgbe_common.c:3729:13: warning: array subscript 1 is above array bounds of ‘u32[1]’ {aka ‘unsigned int[1]’} [-Warray-bounds] 3729 | bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); | ~~~~~~~~~~^~~~ drivers/net/ethernet/intel/ixgbe/ixgbe_common.c:3682:7: note: while referencing ‘u32arr’ 3682 | u32 u32arr[1]; | ^~~~~~ This helps with the ongoing efforts to globally enable -Warray-bounds. Link: https://github.com/KSPP/linux/issues/109 Co-developed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Tested-by: Dave Switzer <david.switzer@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Link: https://lore.kernel.org/r/20210527173424.362456-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27atl1c: add 4 RX/TX queue support for Mikrotik 10/25G NICGatis Peisenieks3-156/+289
More RX/TX queues on a network card help spread the CPU load among cores and achieve higher overall networking performance. The new Mikrotik 10/25G NIC supports 4 RX and 4 TX queues. TX queues are treated with equal priority. RX queue balancing is fixed based on L2/L3/L4 hash. This adds support for 4 RX/TX queues while maintaining backwards compatibility with older hardware. Simultaneous TX + RX performance on AMD Threadripper 3960X with Mikrotik 10/25G NIC improved from 1.6Mpps to 3.2Mpps per port. Backwards compatiblitiy was verified with AR8151 and AR8131 based NICs. Signed-off-by: Gatis Peisenieks <gatis@mikrotik.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27atl1c: prepare for multiple rx queuesGatis Peisenieks2-61/+57
Move napi and other per queue members into per rx queue struct. Allocate max rx queues that any hw supported by the driver might have. Patch that actually enables multiple rx queues will follow. Signed-off-by: Gatis Peisenieks <gatis@mikrotik.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27atl1c: move tx napi into tpd_ringGatis Peisenieks2-9/+13
To get more performance from using multiple tx queues one needs a per tx queue napi. Move tx napi from per adapter struct into per tx queue struct. Patch that actually enables multiple tx queues will follow. Signed-off-by: Gatis Peisenieks <gatis@mikrotik.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27atl1c: detect NIC type earlyGatis Peisenieks1-29/+27
To support NICs that allow for more than one tx queue it is required to detect NIC type early during probe. This is moves NIC type detection before netdev_alloc to prepare for that. Signed-off-by: Gatis Peisenieks <gatis@mikrotik.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27mlxsw: core: use PSID string define in devlink infoJiri Pirko1-1/+3
Instead of having the string spelled out in the driver, use the global define with the same value. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27mlxsw: core: Expose FW version over defined keywordJiri Pirko1-1/+3
To be aligned with the rest of the drivers, expose FW version under "fw" keyword in devlink dev info, in addition to the existing "fw.version", which is currently Mellanox-specific. devlink output before: running: fw.version 30.2008.2018 after: running: fw.version 30.2008.2018 fw 30.2008.2018 Signed-off-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27net/mlx5: Expose FW version over defined keywordJiri Pirko1-2/+8
To be aligned with the rest of the drivers, expose FW version under "fw" keyword in devlink dev info, in addition to the existing "fw.version", which is currently Mellanox-specific. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27Merge tag 'linux-can-next-for-5.14-20210527' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-nextJakub Kicinski12-144/+179
Marc Kleine-Budde says: ==================== can-next 2021-05-27 The first 2 patches are by Geert Uytterhoeven and convert the rcan_can and rcan_canfd device tree bindings to yaml. The next 2 patches are by Oliver Hartkopp and me and update the CAN uapi headers. zuoqilin's patch removes an unnecessary variable from the CAN proc code. Patrick Menschel contributes 3 patches for CAN ISOTP to enhance the error messages. Jiapeng Chong's patch removes two dead stores from the softing driver. The next 4 patches are by me and silence several warnings found by clang compiler. Jimmy Assarsson's patches for the kvaser_usb driver add support for the Kvaser hydra devices. Dario Binacchi provides 2 patches for the c_can driver, first removing an unused variable, then adding basic ethtool support to query driver and ring parameter info. The last 4 patches are by Torin Cooper-Bennun and clean up the m_can driver. * tag 'linux-can-next-for-5.14-20210527' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next: (21 commits) can: m_can: fix whitespace in a few comments can: m_can: make TXESC, RXESC config more explicit can: m_can: clean up CCCR reg defs, order by revs can: m_can: use bits.h macros for all regmasks can: c_can: add ethtool support can: c_can: remove unused variable struct c_can_priv::rxmasked can: kvaser_usb: Add new Kvaser hydra devices can: kvaser_usb: Rename define USB_HYBRID_{,PRO_}CANLIN_PRODUCT_ID can: at91_can: silence clang warning can: mcp251xfd: silence clang warning can: mcp251x: mcp251x_can_probe(): silence clang warning can: hi311x: hi3110_can_probe(): silence clang warning can: softing: Remove redundant variable ptr can: isotp: Add error message if txqueuelen is too small can: isotp: add symbolic error message to isotp_module_init() can: isotp: change error format from decimal to symbolic error names can: proc: remove unnecessary variables can: uapi: introduce CANFD_FDF flag for mixed content in struct canfd_frame can: uapi: update CAN-FD frame description dt-bindings: can: rcar_canfd: Convert to json-schema ... ==================== Link: https://lore.kernel.org/r/20210527084532.1384031-1-mkl@pengutronix.de Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27net/mlx5: Fix lag port remapping logicEli Cohen1-6/+13
Fix the logic so that if both ports netdevices are enabled or disabled, use the trivial mapping without swapping. If only one of the netdevice's tx is enabled, use it to remap traffic to that port. Signed-off-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Use boolean arithmetic to evaluate roce_lagEli Cohen1-2/+3
Avoid mixing boolean and bit arithmetic when evaluating validity of roce_lag. Signed-off-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Remove unnecessary spin lock protectionEli Cohen1-4/+0
Taking lag_lock to access ldev->tracker is meaningless in the context of do_bond() and mlx5_lag_netdev_event(). Signed-off-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Cap the maximum flow group size to 16M entriesPaul Blakey1-0/+5
The maximum number of large flow groups applies to both small and large tables. For very large tables (such as the 2G SW steering tables) this may create a small number of flow groups each with an unrealistic entries domain (> 16M). Set the maximum number of large flow groups to at least what user requested, but with a maximum per group size of 16M entries. For software steering, if user requested less than 128 large flow groups, it will gives us about 128 16M groups in a 2G entries tables. Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: DR, Set max table size to 2G entriesPaul Blakey1-1/+1
SW steering has no table size limitations. However, fs_core API is size aware. Set SW steering tables to the maximum possible table size (INT_MAX). Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Move chains ft pool to be used by all firmware steeringPaul Blakey6-98/+149
Firmware FT pool is per device, but the software tracking of this pool only services fs_chains users, and if another layer takes a flow table, the pool will not be updated, and fs_chains will fail creating a flow table, with no recovery till the flow table is returned. Move FT pool to be global per device, and stored at the cmd level, so all layers can use it. Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Move table size calculation to steering cmd layerPaul Blakey4-11/+15
Currently the table size is calculated by the fs_core layer. However, each steering cmd instance has a different allocation logic. FW steering uses a predefined pools of multiple sizes. SW steering doesn't have a pool, and can allocate any size of tables. Move the table size calculation to the steering cmd layer as a pre-step for moving fs_chains pool logic globally to firmware steering, and increasing table sizes for software steering. In addition, change the size parameter to absolute size to allow the special zero value to mean "get next available maximum size". Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: Add case for FS_FT_NIC_TX FT in MLX5_CAP_FLOWTABLE_TYPEPaul Blakey1-0/+1
Commit 16f1c5bb3ed7 ("net/mlx5: Check device capability for maximum flow counters") added MLX5_CAP_FLOWTABLE_TYPE but forgot to account for FS_FT_NIC_TX case in the expression. Although the expression will return 1 for this case instead of the actual cap, there isn't currently no known side affects of missing this case. Add the FS_FT_NIC_TX case. Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: DR, Remove unused field of send_ring structYevgeny Kliteynik1-1/+0
Remove unused field of struct mlx5dr_send_ring Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5e: RX, Remove unnecessary check in RX CQE compression handlingTariq Toukan1-1/+1
There are two reasons for exiting mlx5e_decompress_cqes_cont(): 1. The compression session is completed (cqd.left == 0). 2. The budget is exhausted (work_done == budget). If after calling mlx5e_decompress_cqes_cont() we have cqd.left > 0, it necessarily implies that budget is exhausted. The first part of the complex condition is covered by the second, hence we remove it here. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5e: IPsec/rep_tc: Fix rep_tc_update_skb drops IPsec packetHuy Nguyen1-2/+4
rep_tc copy REG_C1 to REG_B. IPsec crypto utilizes the whole REG_B register with BIT31 as IPsec marker. rep_tc_update_skb drops IPsec because it thought REG_B contains bad value. In previous patch, BIT 31 of REG_C1 is reserved for IPsec. Skip the rep_tc_update_skb if BIT31 of REG_B is set. Signed-off-by: Huy Nguyen <huyn@nvidia.com> Signed-off-by: Raed Salem <raeds@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5e: TC: Reserved bit 31 of REG_C1 for IPsec offloadHuy Nguyen2-2/+2
Currently ASAP features fully utilize all the bits of the CQE's flow tag and ft_metadata field. The flow tag field cannot be used because the flow table tagging in FTE does not allow partial write. We agree to reserve bit 31 of CQE's ft_metadata for IPsec to avoid ASAP CT from dropping IPsec offloaded packet Here is the new bit layout of REG_C1. Tunnel option id is reduced to 11 bits: < IPSEC MARKER (1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) > Signed-off-by: Huy Nguyen <huyn@nvidia.com> Signed-off-by: Raed Salem <raeds@nvidia.com> Reviewed-by: Paul Blakey <paulb@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Paul Blakey <paulb@nvidia.com>
2021-05-27net/mlx5e: TC: Use bit counts for register mappingPaul Blakey5-49/+77
To prepare for next patch where we will use a non-byte aligned mapping, change all byte counts in register mapping to bits. Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5: CT: Avoid reusing modify header context for natted entriesPaul Blakey1-12/+38
Currently the driver is designed to reuse header modify context entries. Natted entries will always have a unique modify header, as such the modify header hashtable lookup is introducing an overhead. When the hashtable size exceeded 200k entries the tested insertion rate dropped from ~10k entries/sec to ~300 entries/sec. Don't use the re-use mechanism when creating modify headers for natted tuples. Signed-off-by: Paul Blakey <paulb@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27net/mlx5e: CT, Remove newline from ct_dbg callRoi Dayan1-1/+1
ct_dbg() already adds a newline. Signed-off-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-05-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski86-519/+1266
cdc-wdm: s/kill_urbs/poison_urbs/ to fix build Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-05-27can: m_can: fix whitespace in a few commentsTorin Cooper-Bennun1-5/+5
Fixes whitespace in comments titling sections of register masks. Link: https://lore.kernel.org/r/20210504125123.500553-5-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2021-05-27can: m_can: make TXESC, RXESC config more explicitTorin Cooper-Bennun1-6/+12
Introduce masks for the three RXESC fields (RBDS, F1DS, F0DS) and the one TXESC field (TBDS). Update m_can_chip_config() to explicitly set all four fields to the 64-byte option (0x7) (and these defs are renamed to be more concise). This is an improvement in maintainability, and also makes it easier to implement more flexible configuration of the M_CAN buffers in the future. Link: https://lore.kernel.org/r/20210504125123.500553-4-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun <torin@maxiluxsystems.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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