aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pci/controller (follow)
AgeCommit message (Collapse)AuthorFilesLines
2019-05-14Merge tag 'pci-v5.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds28-594/+1280
Pull PCI updates from Bjorn Helgaas: "Enumeration changes: - Add _HPX Type 3 settings support, which gives firmware more influence over device configuration (Alexandru Gagniuc) - Support fixed bus numbers from bridge Enhanced Allocation capabilities (Subbaraya Sundeep) - Add "external-facing" DT property to identify cases where we require IOMMU protection against untrusted devices (Jean-Philippe Brucker) - Enable PCIe services for host controller drivers that use managed host bridge alloc (Jean-Philippe Brucker) - Log PCIe port service messages with pci_dev, not the pcie_device (Frederick Lawler) - Convert pciehp from pciehp_debug module parameter to generic dynamic debug (Frederick Lawler) Peer-to-peer DMA: - Add whitelist of Root Complexes that support peer-to-peer DMA between Root Ports (Christian König) Native controller drivers: - Add PCI host bridge DMA ranges for bridges that can't DMA everywhere, e.g., iProc (Srinath Mannam) - Add Amazon Annapurna Labs PCIe host controller driver (Jonathan Chocron) - Fix Tegra MSI target allocation so DMA doesn't generate unwanted MSIs (Vidya Sagar) - Fix of_node reference leaks (Wen Yang) - Fix Hyper-V module unload & device removal issues (Dexuan Cui) - Cleanup R-Car driver (Marek Vasut) - Cleanup Keystone driver (Kishon Vijay Abraham I) - Cleanup i.MX6 driver (Andrey Smirnov) Significant bug fixes: - Reset Lenovo ThinkPad P50 GPU so nouveau works after reboot (Lyude Paul) - Fix Switchtec firmware update performance issue (Wesley Sheng) - Work around Pericom switch link retraining erratum (Stefan Mätje)" * tag 'pci-v5.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (141 commits) MAINTAINERS: Add Karthikeyan Mitran and Hou Zhiqiang for Mobiveil PCI PCI: pciehp: Remove pointless MY_NAME definition PCI: pciehp: Remove pointless PCIE_MODULE_NAME definition PCI: pciehp: Remove unused dbg/err/info/warn() wrappers PCI: pciehp: Log messages with pci_dev, not pcie_device PCI: pciehp: Replace pciehp_debug module param with dyndbg PCI: pciehp: Remove pciehp_debug uses PCI/AER: Log messages with pci_dev, not pcie_device PCI/DPC: Log messages with pci_dev, not pcie_device PCI/PME: Replace dev_printk(KERN_DEBUG) with dev_info() PCI/AER: Replace dev_printk(KERN_DEBUG) with dev_info() PCI: Replace dev_printk(KERN_DEBUG) with dev_info(), etc PCI: Replace printk(KERN_INFO) with pr_info(), etc PCI: Use dev_printk() when possible PCI: Cleanup setup-bus.c comments and whitespace PCI: imx6: Allow asynchronous probing PCI: dwc: Save root bus for driver remove hooks PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code PCI: dwc: Free MSI in dw_pcie_host_init() error path PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi() ...
2019-05-13Merge branch 'pci/trivial'Bjorn Helgaas2-2/+2
- Cleanup PCI register definitions, typos, etc (Bjorn Helgaas) - Remove unnecessary use of user-space types in CPER (Bjorn Helgaas) - Cleanup setup-bus.c comments & whitespace (Nicholas Johnson) * pci/trivial: PCI: Cleanup setup-bus.c comments and whitespace CPER: Remove unnecessary use of user-space types CPER: Add UEFI spec references PCI: Fix comment typos PCI: Cleanup register definition width and whitespace # Conflicts: # drivers/pci/pci.c # drivers/pci/setup-bus.c
2019-05-13Merge branch 'pci/iova-dma-ranges'Bjorn Helgaas1-1/+43
- Add list of legal DMA address ranges to PCI host bridge (Srinath Mannam) - Reserve inaccessible DMA ranges so IOMMU doesn't allocate them (Srinath Mannam) - Parse iProc DT dma-ranges to learn what PCI devices can reach via DMA (Srinath Mannam) * pci/iova-dma-ranges: PCI: iproc: Add sorted dma ranges resource entries to host bridge iommu/dma: Reserve IOVA for PCIe inaccessible DMA address PCI: Add dma_ranges window list # Conflicts: # drivers/pci/probe.c
2019-05-13Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas7-10/+26
- Exit pcitest with error code when test fails (Jean-Jacques Hiblot) - Fix leaked of_node references in dra7xx, uniphier, layerscape, rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang) - Fix pcitest "help" option parsing (Kishon Vijay Abraham I) - Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay Abraham I) - Check for alloc_workqueue() failure in endpoint test driver (Kangjie Lu) * remotes/lorenzo/pci/misc: PCI: endpoint: Fix a potential NULL pointer dereference tools: PCI: Handle pcitest.sh independently from pcitest tools: PCI: Add 'h' in optstring of getopt() PCI: mediatek: Fix a leaked reference by adding missing of_node_put() PCI: iproc: Fix a leaked reference by adding missing of_node_put() PCI: aardvark: Fix a leaked reference by adding missing of_node_put() PCI: rockchip: Fix a leaked reference by adding missing of_node_put() PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put() PCI: uniphier: Fix a leaked reference by adding missing of_node_put() PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put() tools: PCI: Exit with error code when test fails
2019-05-13Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas1-2/+10
- Check for __get_free_pages() failure in xilinx (Kangjie Lu) * remotes/lorenzo/pci/xilinx: PCI: xilinx: Check for __get_free_pages() failure
2019-05-13Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-9/+28
- Use DMA-API to get tegra MSI address to prevent device DMA from generating unwanted MSIs (Vidya Sagar) * remotes/lorenzo/pci/tegra: PCI: tegra: Use the DMA-API to get the MSI address
2019-05-13Merge branch 'remotes/lorenzo/pci/rockchip'Bjorn Helgaas1-1/+1
- Fix rockchip bitwise operations that overflow type (Colin Ian King) * remotes/lorenzo/pci/rockchip: PCI: rockchip: Fix rockchip_pcie_ep_assert_intx() bitwise operations
2019-05-13Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas1-30/+34
- Use BIT() when appropriate in rcar (Marek Vasut) - Use u32 to match rcar hardware register widths (Marek Vasut) - Use BITS_PER_BYTE when appropriate in rcar (Marek Vasut) - Remove unnecessary casts in rcar (Marek Vasut) - Fix 64-bit MSI target addresses in rcar (Marek Vasut) - Check for __get_free_pages() failure in rcar (Kangjie Lu) - Fix shadowed rcar "irq" variable (Wolfram Sang) * remotes/lorenzo/pci/rcar: PCI: rcar: Do not shadow the 'irq' variable PCI: rcar: Fix a potential NULL pointer dereference PCI: rcar: Fix 64bit MSI message address handling PCI: rcar: Clean up debug messages PCI: rcar: Replace (8 * n) with (BITS_PER_BYTE * n) PCI: rcar: Replace various variable types with unsigned ones for register values PCI: rcar: Replace unsigned long with u32/unsigned int in register accessors PCI: rcar: Clean up remaining macros defining bits # Conflicts: # drivers/pci/controller/pcie-rcar.c
2019-05-13Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas1-35/+15
- Make mediatek clocks optional, not required (Chunfeng Yun) - Remove unused mediatek mt2712 "num-lanes" DT property (Honghui Zhang) * remotes/lorenzo/pci/mediatek: arm64: dts: mt2712: Remove un-used property for PCIe PCI: mediatek: Get optional clocks with devm_clk_get_optional()
2019-05-13Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas10-353/+835
- Move IRQ register address computation inside macros (Kishon Vijay Abraham I) - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I) - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham I) - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon Vijay Abraham I) - Add dwc support for platforms with custom MSI controllers (Kishon Vijay Abraham I) - Add keystone-specific MSI controller (Kishon Vijay Abraham I) - Remove dwc host_ops previously used for keystone-specific MSI (Kishon Vijay Abraham I) - Skip dwc default MSI init if platform has custom MSI controller (Kishon Vijay Abraham I) - Implement .start_link() and .stop_link() for keystone endpoint support (Kishon Vijay Abraham I) - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I) - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon Vijay Abraham I) - Get keystone register resources from DT by name, not index (Kishon Vijay Abraham I) - Get DT resources in .probe() to prepare for endpoint support (Kishon Vijay Abraham I) - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration (Kishon Vijay Abraham I) - Explicitly set keystone to host mode (Kishon Vijay Abraham I) - Document DT "atu" reg-names requirement for DesignWare core >= 4.80 (Kishon Vijay Abraham I) - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon Vijay Abraham I) - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon Vijay Abraham I) - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham I) - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham I) - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I) - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I) - Make of_pci_get_max_link_speed() available to endpoint drivers as well as host drivers (Kishon Vijay Abraham I) - Add keystone support for DT "max-link-speed" property (Kishon Vijay Abraham I) - Add endpoint library support for BAR buffer alignment (Kishon Vijay Abraham I) - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I) - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay Abraham I) - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon Vijay Abraham I) - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay Abraham I) - Configure designware endpoints to advertise smallest resizable BAR (1MB) (Kishon Vijay Abraham I) - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay Abraham I) - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I) - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test misc: pci_endpoint_test: Add support to test PCI EP in AM654x PCI: designware-ep: Use aligned ATU window for raising MSI interrupts PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size PCI: keystone: Add support for PCIe EP in AM654x Platforms dt-bindings: PCI: Add PCI EP DT binding documentation for AM654 PCI: dwc: Add callbacks for accessing dbi2 address space PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: endpoint: Add support to specify alignment for buffers allocated to BARs PCI: keystone: Add support to set the max link speed from DT PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Invoke phy_reset() API before enabling PHY PCI: keystone: Add support for PCIe RC in AM654x Platforms dt-bindings: PCI: Add PCI RC DT binding documentation for AM654 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: dwc: Enable iATU unroll for endpoint too dt-bindings: PCI: Document "atu" reg-names PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Move resources initialization to prepare for EP support PCI: keystone: Use platform_get_resource_byname() to get memory resources PCI: keystone: Perform host initialization in a single function dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Cleanup error_irq configuration PCI: keystone: Add start_link()/stop_link() dw_pcie_ops PCI: dwc: Remove default MSI initialization for platform specific MSI chips PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Cleanup ks_pcie_msi_irq_handler() PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Cleanup interrupt related macros # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h
2019-05-13Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas1-5/+41
- Work around iproc CRS completion issues (Srinath Mannam) - Allow smaller iproc outbound windows so driver can work on 32-bit systems (Srinath Mannam) - Use iproc-specific config read for PAXBv2 (not PAXB) (Srinath Mannam) * remotes/lorenzo/pci/iproc: PCI: iproc: Enable iProc config read for PAXBv2 PCI: iproc: Allow outbound configuration for 32-bit I/O region PCI: iproc: Add CRS check in config read
2019-05-13Merge branch 'remotes/lorenzo/pci/imx'Bjorn Helgaas3-96/+62
- Simplify imx7d_pcie_wait_for_phy_pll_lock() by using regmap_read_poll_timeout() (Andrey Smirnov) - Drop imx6_pcie_wait_for_link() in favor of the more generic dw_pcie_wait_for_link() (Andrey Smirnov) - Return -ETIMEDOUT instead of -EINVAL from imx6_pcie_wait_for_speed_change() (Andrey Smirnov) - Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov) - Use shared PHY debug register definitions in imx6 (Andrey Smirnov) - Use BIT() in imx6 (Andrey Smirnov) - Simplify imx6 PHY bit operations (Andrey Smirnov) - Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov) - Use data types that match actual imx6 PHY register width (Andrey Smirnov) - Mark imx6 suspend support with drvdata flags instead of checking variants (Andrey Smirnov) - Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov) * remotes/lorenzo/pci/imx: PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk() PCI: imx6: Use flags to indicate support for suspend PCI: imx6: Restrict PHY register data to 16-bit PCI: imx6: Simplify pcie_phy_poll_ack() PCI: imx6: Simplify bit operations in PHY functions PCI: imx6: Make use of BIT() in constant definitions PCI: dwc: imx6: Share PHY debug register definitions PCI: imx6: Remove PCIE_PL_PFLR_* constants PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() PCI: imx6: Drop imx6_pcie_wait_for_link() PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
2019-05-13Merge branch 'pci/dwc'Bjorn Helgaas4-45/+41
- Use generic config space reader in qcom (Marc Gonzalez) - Stop calling IRQ handler cleanup in dwc driver for invalid MSI IRQs (Jisheng Zhang) - Free dwc MSI target page when freeing MSI (Jisheng Zhang) - Fix dwc MSI leak in host init error path (Jisheng Zhang) - Use managed host bridge alloc to simplify dwc (Jisheng Zhang) - Save dwc root pci_bus pointer for use by .remove() methods (Jisheng Zhang) - Allow imx6 asynchronous probing (Lucas Stach) * pci/dwc: PCI: imx6: Allow asynchronous probing PCI: dwc: Save root bus for driver remove hooks PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify code PCI: dwc: Free MSI in dw_pcie_host_init() error path PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi() PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalid PCI: qcom: Use default config space read function
2019-05-13Merge branch 'remotes/lorenzo/pci/controller-fixes'Bjorn Helgaas2-0/+44
- Restore R-Car PCIe link early in resume (Kazufumi Ikeda) - Fix Hyper-V PCI ejection memory leak (Dexuan Cui) - Cleanup Hyper-V PCI slots on module unload (Dexuan Cui) - Cleanup Hyper-V PCI slot on device removal to address a race (Dexuan Cui) * remotes/lorenzo/pci/controller-fixes: PCI: hv: Add pci_destroy_slot() in pci_devices_present_work(), if necessary PCI: hv: Add hv_pci_remove_slots() when we unload the driver PCI: hv: Fix a memory leak in hv_eject_device_work() PCI: rcar: Add the initialization of PCIe link in resume_noirq()
2019-05-13Merge branch 'pci/host/al'Bjorn Helgaas2-0/+94
- Add Amazon Annapurna Labs PCIe host controller driver (Jonathan Chocron) * pci/host/al: PCI: al: Add Amazon Annapurna Labs PCIe host controller driver
2019-05-07PCI: imx6: Allow asynchronous probingLucas Stach1-0/+1
Establishing a PCIe link can take a while; allow asynchronous probing so that link establishment can happen in the background while other devices are being probed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-05-07PCI: dwc: Save root bus for driver remove hooksJisheng Zhang2-6/+7
Currently DWC host does not support the remove callback, but nothing prevents us from supporting it. Save the root bus for clean up work in driver remove code paths to allow DWC host drivers to implement their remove hook as, eg: static int foo_pcie_remove(struct platform_device *pdev) { ... pci_stop_root_bus(pp->root_bus); pci_remove_root_bus(pp->root_bus); dw_pcie_free_msi(pp); ... } Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Use devm_pci_alloc_host_bridge() to simplify codeJisheng Zhang1-13/+8
Use devm_pci_alloc_host_bridge() to simplify the error code path. This also fixes a leak in the dw_pcie_host_init() error path. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> CC: stable@vger.kernel.org # v4.13+
2019-05-07PCI: dwc: Free MSI in dw_pcie_host_init() error pathJisheng Zhang1-3/+6
If we ever did MSI-related initializations, we need to call dw_pcie_free_msi() in the error code path. Remove the IS_ENABLED(CONFIG_PCI_MSI) check for MSI init because pci_msi_enabled() already has a stub for !CONFIG_PCI_MSI. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Free MSI IRQ page in dw_pcie_free_msi()Jisheng Zhang2-4/+9
To avoid a memory leak, free the page allocated for MSI IRQ in dw_pcie_free_msi(). Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: dwc: Fix dw_pcie_free_msi() if msi_irq is invalidJisheng Zhang1-2/+4
Check msi_irq variable before calling irq_set_chained_handler() and irq_set_handler_data(), lest we call those functions for an invalid MSI IRQ. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2019-05-07PCI: qcom: Use default config space read functionMarc Gonzalez1-17/+6
Move the device class fudge to a proper fixup function, and remove qcom_pcie_rd_own_conf() which has become useless. dw_pcie_setup_rc() already did the right thing, but it's broken on older qcom chips, such as 8064. Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2019-05-06PCI: iproc: Add sorted dma ranges resource entries to host bridgeSrinath Mannam1-1/+43
The iProc host controller allows only a subset of physical address space as target of inbound PCI memory transaction addresses. PCI device memory transactions targeting memory regions that are not allowed for inbound transactions in the host controller are rejected by the host controller and cannot reach the upstream buses. The firmware device tree description defines the DMA ranges that are addressable by devices DMA transactions; parse the device tree dma-ranges property and add its ranges to the PCI host bridge dma_ranges list; the iova_reserve_pci_windows() call executed at iommu_dma_init_domain() will reserve the IOVA address ranges that are not addressable (ie memory holes in the dma-ranges set) so that they are not allocated to PCI devices for DMA transfers. All allowed address ranges are listed in the dma-ranges DT parameter. For example: dma-ranges = < \ 0x43000000 0x00 0x80000000 0x00 0x80000000 0x00 0x80000000 \ 0x43000000 0x08 0x00000000 0x08 0x00000000 0x08 0x00000000 \ 0x43000000 0x80 0x00000000 0x80 0x00000000 0x40 0x00000000> In the above example of dma-ranges, memory address from 0x0 - 0x80000000, 0x100000000 - 0x800000000, 0x1000000000 - 0x8000000000 and 0x10000000000 - 0xffffffffffffffff. are not allowed to be used as inbound addresses. Based-on-a-patch-by: Oza Pawandeep <oza.oza@broadcom.com> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: fix function prototype style] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org> Reviewed-by: Eric Auger <eric.auger@redhat.com>
2019-05-01PCI: designware-ep: Use aligned ATU window for raising MSI interruptsKishon Vijay Abraham I1-2/+5
Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configure an aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-05-01PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest sizeKishon Vijay Abraham I1-0/+34
Configure the Resizable BAR capability to advertise the smallest size (1MB) for a couple of reasons: - Host side resource allocation of BAR fails for larger sizes - Endpoint function driver does not allocate memory for all supported sizes in the Resizable BAR capability. If and when there is a usecase required to add more flexibility using the Resizable BAR capability, this can be revisited. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-05-01PCI: keystone: Add support for PCIe EP in AM654x PlatformsKishon Vijay Abraham I2-37/+240
Add PCIe EP support for AM654x Platforms in pci-keystone.c Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-05-01PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()Andrey Smirnov1-1/+1
imx6_pcie_enable_ref_clk() is never called in atomic context, so there's no need to use udelay(). Replace it with usleep_range(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Use flags to indicate support for suspendAndrey Smirnov1-9/+6
Now that driver data has flags variable that can be used to indicate quirks/features supported we can switch the code to use it instead of having a special function that does so based on variant alone. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Restrict PHY register data to 16-bitAndrey Smirnov1-7/+6
PHY registers on i.MX6 are 16-bit wide, so we can get rid of explicit masking if we restrict pcie_phy_read()/pcie_phy_write() to use 'u16' instead of 'int'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Simplify pcie_phy_poll_ack()Andrey Smirnov1-13/+13
Simplify pcie_phy_poll_ack() by incorporating shifting into constant definition and convert the code to use 'bool'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Simplify bit operations in PHY functionsAndrey Smirnov1-14/+14
Simplify the code by incorporating left shifts into constant definitions as well as using FIELD_PREP/GENMASK. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Make use of BIT() in constant definitionsAndrey Smirnov1-4/+4
Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: dwc: imx6: Share PHY debug register definitionsAndrey Smirnov3-13/+8
Both pcie-designware.c and pci-imx6.c contain custom definitions for PHY debug registers R0/R1 and on top of that there's already a definition for R0 in pcie-designware.h. Move all of the definitions to pcie-designware.h. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Remove PCIE_PL_PFLR_* constantsAndrey Smirnov1-3/+0
Code using these constants was removed in commit a71280722eeb ("PCI: imx6: Remove LTSSM disable workaround"). No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()Andrey Smirnov1-1/+1
Change error code from -EINVAL to -ETIMEDOUT in imx6_pcie_wait_for_speed_change() since that error code seems more appropriate. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Drop imx6_pcie_wait_for_link()Andrey Smirnov1-17/+2
All calls to imx6_pcie_wait_for_link() share the same error path and the state of PHY debug registers will already be printed there, so there's no real reason we can't just use dw_pcie_wait_for_link(). Drop imx6_pcie_wait_for_link() and replace it with dw_pcie_wait_for_link(). Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-05-01PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()Andrey Smirnov1-14/+7
Make use of regmap_read_poll_timeout() to simplify imx7d_pcie_wait_for_phy_pll_lock(). No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
2019-04-30PCI: iproc: Enable iProc config read for PAXBv2Srinath Mannam1-1/+1
iProc config read flag has to be enabled for PAXBv2 instead of PAXB. Fixes: f78e60a29d4f ("PCI: iproc: Reject unconfigured physical functions from PAXC") Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
2019-04-25PCI: al: Add Amazon Annapurna Labs PCIe host controller driverJonathan Chocron2-0/+94
Add driver for Amazon's Annapurna Labs PCIe host controller. The controller is based on DesignWare's IP. The controller doesn't support accessing the Root Port's config space via ECAM, so we obtain its base address via an AMZN0001 device. Furthermore, the DesignWare PCIe controller doesn't filter out config transactions sent to devices 1 and up on its bus, so they are filtered by the driver. All subordinate buses do support ECAM access. Implementing specific PCI config access functions involves: - Adding an init function to obtain the Root Port's base address from an AMZN0001 device. - Adding a new entry in the MCFG quirk array. [bhelgaas: Note that there is no Kconfig option for this driver because it is only intended for use with the generic ACPI host bridge driver. This driver is only needed because the DesignWare IP doesn't completely support ECAM access to the root bus.] Link: https://lore.kernel.org/lkml/1553774276-24675-1-git-send-email-jonnyc@amazon.com Co-developed-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Vladimir Aerov <vaerov@amazon.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-24x86/pci: Clean up usage of X86_DEV_DMA_OPSChristoph Hellwig2-7/+1
We have supported per-device dma_map_ops in generic code for a long time, and this symbol just guards the inclusion of the dma_map_ops registry used for vmd. Stop enabling it for anything but vmd. No change in functionality intended. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20190410080220.21705-3-hch@lst.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-16PCI: tegra: Use the DMA-API to get the MSI addressVidya Sagar1-9/+28
Since the upstream MSI memory writes are generated by downstream devices, it is logically correct to have MSI target memory coming from the DMA pool reserved for PCIe than from the general memory pool reserved for CPU access to avoid PCIe DMA addresses coinciding with MSI target address thereby raising unwanted MSI interrupts. Enforce this behaviour by retrieving the MSI address through the DMA API. Limit the MSI target address to 32-bits to make it work for PCIe endpoints that support only 32-bit MSI target address; endpoints that support 64-bit MSI target address work with 32-bit MSI target address too. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2019-04-16PCI: dwc: Add callbacks for accessing dbi2 address spaceKishon Vijay Abraham I2-2/+41
Certain platforms like TI's AM654 do not have aseparate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-16PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offsetKishon Vijay Abraham I1-5/+5
commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability() and __dw_pcie_ep_find_next_cap() for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present because of incorrect ordering of the "next_cap_ptr" check. Fix it. Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I5-5/+5
Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: keystone: Add support to set the max link speed from DTKishon Vijay Abraham I1-0/+35
PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe does not work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" DT property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: keystone: Invoke phy_reset() API before enabling PHYKishon Vijay Abraham I1-0/+4
SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke the phy_reset() API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: keystone: Add support for PCIe RC in AM654x PlatformsKishon Vijay Abraham I2-15/+148
Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64Kishon Vijay Abraham I1-0/+4
hook_fault_code() is an ARM32 specific API for hooking into data abort. AM65X platforms (that integrate ARM v8 cores and select CONFIG_ARM64 as arch) rely on pci-keystone.c but on them the enumeration of a non-present BDF does not trigger a bus error, so the fixup exception provided by calling hook_fault_code() is not needed and can be guarded with CONFIG_ARM. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: dwc: Fix ATU identification for designware version >= 4.80Kishon Vijay Abraham I2-6/+9
Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which have not populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2019-04-15PCI: dwc: Enable iATU unroll for endpoint tooKishon Vijay Abraham I3-23/+19
iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup() which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.