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2017-07-02PCI: rockchip: Check for clk_prepare_enable() errors during resumeArvind Yadav1-6/+28
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02PCI: rockchip: Configure RC's MPS settingShawn Lin1-0/+8
The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Reconfigure configuration space header typeShawn Lin1-0/+14
Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1 configuration space header should be used when accessing PCIe switch. So we need to reconfigure the header according to the bus number we are accessing. Otherwise we could not visit the buses behind the switch. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()Shawn Lin1-10/+25
We need to reconfigure the header type later, so split out a new function. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()Shawn Lin1-10/+11
Configuration accesses is also part of ATU settings, so let's keep all of them inside rockchip_pcie_cfg_atu(). Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu()Shawn Lin1-3/+3
Rename rockchip_cfg_atu() to keep the name consistent with other functions in pcie-rockchip.c. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: rockchip: Control vpcie0v9 for system PMShawn Lin1-0/+11
vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to work then in S3 if folks assign it DT. But we should note that there is a side effect that we could not support beacon wakeup if we disable vpcie0v9 for aggressive power-saving. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Brian Norris <briannorris@chromium.org> Cc: Jeffy Chen <jeffy.chen@rock-chips.com>
2017-07-02PCI: rcar-gen2: Make of_device_ids constArvind Yadav1-1/+1
of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-02PCI: qcom: Limit TLP size to 2K to work around hardware issueSrinivas Kandagatla1-0/+13
Limit TLP size to 2K to work around a hardware bug in the v0 version of PCIe IP. When using default TLP size of 4K, the internal buffer gets corrupted due to this hardware bug. This bug was originally noticed during ssh session between APQ8064-based board and PC. Network packets got corrupted randomly and terminated the ssh session due to this bug. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: qcom: Fix spelling mistake: "asser" -> "assert"Colin Ian King1-1/+1
Trivial fix to spelling mistake in dev_err message. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: qcom: Reorder to put v0 functions together, v1 functions together, etcBjorn Helgaas1-61/+61
Previously the v0, v1, and v2 functions were not grouped together in a consistent order. Reorder them to make them consistent. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: qcom: Add support for IPQ4019 PCIe controllerJohn Crispin1-0/+306
Add support for the IPQ4019 PCIe controller. IPQ4019 supports Gen 1/2, one lane, one PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the same as for the MSM8996, however the clocks and reset lines differ. [bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile issues] Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Rob Herring <robh@kernel.org> # binding
2017-07-02PCI: mediatek: Add MediaTek PCIe host controller supportRyder Lee3-0/+566
Add support for the MediaTek PCIe Gen2 controller which can be found on MT7623 series SoCs. [bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from http://lkml.kernel.org/r/1496644078-27122-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/1497588789-28607-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from http://lkml.kernel.org/r/1498555451-55073-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in powerup fixes from http://lkml.kernel.org/r/1497866400-41844-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in poweroff when link down fixes from http://lkml.kernel.org/r/1497866400-41844-3-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in optional property fixes from http://lkml.kernel.org/r/1497866400-41844-4-git-send-email-ryder.lee@mediatek.com] [bhelgaas: set host->map_irq and host->swizzle_irq and drop pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up() to mtk_pcie_link_up() for consistency, add local struct device pointer] [bhelgaas: fold in pci_add_flags() removal from http://lkml.kernel.org/r/1499061300-55951-1-git-send-email-ryder.lee@mediatek.com] Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driverXiaowei Song3-0/+528
Hisilicon PCIe driver shares the common functions for PCIe dw-host. The poweron functions are developed on hi3660 SoC, while other functions are common for Kirin series SoCs. Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature are not supported currently. Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/20170704021516.96575-1-songxiaowei@hisilicon.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Cc: Guodong Xu <guodong.xu@linaro.org>
2017-07-02PCI: imx6: Add regulator supportQuentin Schulz1-1/+36
Some boards might require to control a regulator to power the PCIe port. Add support for an optional regulator defined in Device Tree linked in the PCIe controller under `vpcie-supply`. If present, the regulator will be disabled and then enabled as part of the PCIe host initialization process and will be disabled when shutting down. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> [bhelgaas: use dev_err() instead of pr_err() in imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2017-07-02PCI: hv: Use vPCI protocol version 1.2Jork Loeser1-54/+246
Update the Hyper-V vPCI driver to use the Server-2016 version of the vPCI protocol, fixing MSI creation and retargeting issues. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-07-02PCI: hv: Add vPCI version protocol negotiationJork Loeser1-19/+53
Hyper-V vPCI offers different protocol versions. Add the infra for negotiating the one to use. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-07-02PCI: hv: Temporary own CPU-number-to-vCPU-number infraJork Loeser1-2/+50
To ease parallel effort to centralize CPU-number-to-vCPU-number conversion, temporarily stand up own version, file-local hv_tmp_cpu_nr_to_vp_nr(). Once the changes have merged, this work-around can be removed, and the calls replaced with hv_cpu_number_to_vp_number(). Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-07-02PCI: hv: Use page allocation for hbus structureJork Loeser1-3/+12
The hv_pcibus_device structure contains an in-memory hypercall argument that must not cross a page boundary. Allocate the structure as a page to ensure that. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-07-02PCI: hv: Fix comment formatting and use proper integer fieldsJork Loeser1-5/+5
Fix comment formatting and use proper integer fields. Signed-off-by: Jork Loeser <jloeser@microsoft.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: K. Y. Srinivasan <kys@microsoft.com> Acked-by: K. Y. Srinivasan <kys@microsoft.com>
2017-07-02PCI: faraday: Add clock handlingLinus Walleij1-0/+56
Add some optional clock handling to the Faraday FTPCI100. We just get and prepare+enable the clocks right now, if they exist. We can add more elaborate clock handling later. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [bhelgaas: folded in "Make clocks compulsory" fix from http://lkml.kernel.org/r/20170621085730.28804-1-linus.walleij@linaro.org Also folded in the clock max/cur speed fixes from http://lkml.kernel.org/r/20170621162651.25315-1-linus.walleij@linaro.org] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAINArvind Yadav1-2/+2
Previously, we tried to clear interrupt requests by clearing bits in the PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN registers. But per the TRM, these fields are RW1C, so we must *set* bits to clear the interrupt bits. Fixes: 47ff3de911a7 ("PCI: dra7xx: Add TI DRA7xx PCIe driver") Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-02PCI: dwc: dra7xx: Depend on appropriate SoC or compile testPeter Robinson1-0/+1
The PCI controller attached to a SoC isn't much use if the core SoC isn't enabled, unless of course it's compile testing, so add appropriate dependency. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-02PCI: dwc: Constify dw_pcie_host_ops structuresJisheng Zhang11-13/+13
The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-07-02PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREADJisheng Zhang3-3/+6
Similar as commit 8ff0ef996ca0 ("PCI: host: Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD"), we should mark PCIe/PCI (MSI) IRQ cascade handlers in designware, qcom, and vmd as IRQF_NO_THREAD explicitly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Keith Busch <keith.busch@intel.com> # vmd Acked-by: Jingoo Han <jingoohan1@gmail.com> # pcie-designware-plat.c
2017-07-02PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functionsLorenzo Pieralisi1-0/+2
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ mapping can be done automatically by PCI core code through the pci_assign_irq() function instead of resorting to arch-specific implementation callbacks to carry out the same task which force PCI host bridge drivers implementation to implement per-arch kludges to carry out a task that is inherently architecture agnostic. Add map/swizzle IRQs hooks to the xilinx-nwl PCI host driver to move the IRQ allocation into core code and stop relying on arch-specific callbacks. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
2017-07-02PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functionsLorenzo Pieralisi1-0/+2
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ mapping can be done automatically by PCI core code through the pci_assign_irq() function instead of resorting to arch-specific implementation callbacks to carry out the same task which force PCI host bridge drivers implementation to implement per-arch kludges to carry out a task that is inherently architecture agnostic. Add map/swizzle IRQs hooks to the rockchip PCI host driver to move the IRQ allocation into core code and stop relying on arch-specific callbacks. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02PCI: xgene: Move to struct pci_host_bridge IRQ mapping functionsLorenzo Pieralisi1-0/+2
struct pci_host_bridge gained hooks to map/swizzle IRQs, so that the IRQ mapping can be done automatically by PCI core code through the pci_assign_irq() function instead of resorting to arch-specific implementation callbacks to carry out the same task which force PCI host bridge drivers implementation to implement per-arch kludges to carry out a task that is inherently architecture agnostic. Add map/swizzle IRQs hooks to the xgene PCI host driver to move the IRQ allocation into core code and stop relying on arch-specific callbacks. Tested-by: Khuong Dinh <kdinh@apm.com> # with e1000e Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tanmay Inamdar <tinamdar@apm.com>
2017-07-02PCI: altera: Drop pci_fixup_irqs()Lorenzo Pieralisi1-2/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI altera host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-07-02PCI: versatile: Drop pci_fixup_irqs()Lorenzo Pieralisi1-2/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI versatile host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: folded in typo fix from Arnd Bergmann <arnd@arndb.de>: http://lkml.kernel.org/r/20170621215323.3921382-4-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh@kernel.org>
2017-07-02PCI: generic: Drop pci_fixup_irqs()Lorenzo Pieralisi1-4/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI host-common bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
2017-07-02PCI: faraday: Drop pci_fixup_irqs()Lorenzo Pieralisi1-1/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI ftpci100 host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Linus Walleij <linus.walleij@linaro.org>
2017-07-02PCI: designware: Drop pci_fixup_irqs()Lorenzo Pieralisi1-5/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI designware host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
2017-07-02PCI: iproc: Drop pci_fixup_irqs()Lorenzo Pieralisi1-3/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI iproc host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
2017-07-02PCI: rcar: Drop pci_fixup_irqs()Lorenzo Pieralisi1-2/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI rcar host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Simon Horman <horms@verge.net.au>
2017-07-02PCI: xilinx: Drop pci_fixup_irqs()Lorenzo Pieralisi1-3/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation. Drop pci_fixup_irqs() usage from PCI xilinx host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Michal Simek <michal.simek@xilinx.com>
2017-07-02PCI: tegra: Drop pci_fixup_irqs()Lorenzo Pieralisi1-1/+2
Since, through struct pci_host_bridge.map/swizzle_irq hooks, IRQs are now allocated in the pci_assign_irq() callback automatically, PCI host bridge drivers can stop relying on pci_fixup_irqs() for IRQ allocation Drop pci_fixup_irqs() usage from PCI tegra host bridge driver. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com>
2017-07-02PCI: Add a call to pci_assign_irq() in pci_device_probe()Matthew Minter1-0/+2
The pci_assign_irq() function allows assignment of an IRQ to devices during device enable time rather than only at boot. Therefore call it in the pci_device_probe() function during the enable device code path so this assignment can be performed. This patch will do nothing on arches which do not set the IRQ mapping function pointers and is therefore currently a nop, however as support for these function pointers is added to arch-specific code this will cause IRQ assignment to migrate to device enable time allowing the new code paths to be used. Signed-off-by: Matthew Minter <matt@masarand.com> [lorenzo.pieralisi@arm.com: moved pci_assign_irq() call site] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use itMatthew Minter1-10/+35
Here we delete the static pdev_fixup_irq() function which is currently what pci_fixup_irqs() uses to actually assign the IRQs and replace it with the pci_assign_irq() function which changes the interface and uses the new function pointers stored in the host bridge structure. Eventually this will allow pci_fixup_irqs() to be removed entirely and the new deferred assignment code path will call pci_assign_irq() directly. However to ensure current users continue to work, a new implementation of pci_fixup_irqs() is introduced which simply wraps the functionality of pci_assign_irq(). Signed-off-by: Matthew Minter <matt@masarand.com> [lorenzo.pieralisi@arm.com: reworked comments/log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: Build setup-irq.o on all archesMatthew Minter1-15/+2
The functions included in setup-irq.o currently apply only to a selection of architectures which share common IRQ assignment code. However this code needs to be generalised for all arches to allow deferred IRQ assignment. So the first step is to build it on all architectures. Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: Remove pci_scan_root_bus_msi()Lorenzo Pieralisi1-22/+5
The pci_scan_root_bus_bridge() function allows passing a parameterized struct pci_host_bridge and scanning the resulting PCI bus; since the struct msi_controller is part of the struct pci_host_bridge and the struct pci_host_bridge can now be passed to pci_scan_root_bus_bridge() explicitly, there is no need for a scan interface with a MSI controller parameter. With all PCI host controller drivers and platform code relying on pci_scan_root_bus_msi() converted over to pci_scan_root_bus_bridge() the pci_scan_root_bus_msi() becomes obsolete and can be removed. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-07-02PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-10/+18
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx-nwl host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
2017-07-02PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-6/+16
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI rockchip host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Wenrui Li <wenrui.li@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
2017-07-02PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-5/+18
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI host-common code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will.deacon@arm.com>
2017-07-02PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-6/+15
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xgene host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Tested-by: Khuong Dinh <kdinh@apm.com> # with e1000e Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Tanmay Inamdar <tinamdar@apm.com>
2017-07-02PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-10/+19
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI xilinx host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Michal Simek <michal.simek@xilinx.com>
2017-07-02PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-6/+16
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI altera host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-07-02PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-3/+17
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI versatile host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: folded in fix from Arnd Bergmann <arnd@arndb.de>: http://lkml.kernel.org/r/20170621215323.3921382-3-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rob Herring <robh@kernel.org>
2017-07-02PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi3-22/+30
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI iproc host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
2017-07-02PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi1-14/+24
The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI rcar host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Simon Horman <horms@verge.net.au>
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