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2017-09-12pinctrl: armada-37xx: Fix gpio interrupt setupGregory CLEMENT1-19/+22
Since commit dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs dynamically"), the irqs for gpio are not statically allocated during in gpiochip_irqchip_add. This driver was based on this assumption for initializing the mask associated to each interrupt this led to a NULL pointer crash in the kernel: Unable to handle kernel NULL pointer dereference at virtual address 00000000 Mem abort info: Exception class = DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 Data abort info: ISV = 0, ISS = 0x00000068 CM = 0, WnR = 1 [0000000000000000] user address but active_mm is swapper Internal error: Oops: 96000044 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-06657-g3b9f8ed25dbe #576 Hardware name: Marvell Armada 3720 Development Board DB-88F3720-DDR3 (DT) task: ffff80001d908000 task.stack: ffff000008068000 PC is at armada_37xx_pinctrl_probe+0x5f8/0x670 LR is at armada_37xx_pinctrl_probe+0x5e8/0x670 pc : [<ffff000008e25cdc>] lr : [<ffff000008e25ccc>] pstate: 60000045 sp : ffff00000806bb80 x29: ffff00000806bb80 x28: 0000000000000024 x27: 000000000000000c x26: 0000000000000001 x25: ffff80001efee760 x24: 0000000000000000 x23: ffff80001db6f570 x22: ffff80001db6f438 x21: 0000000000000000 x20: ffff80001d9f4810 x19: ffff80001db6f418 x18: 0000000000000000 x17: 0000000000000001 x16: 0000000000000019 x15: ffffffffffffffff x14: 0140000000000000 x13: 0000000000000000 x12: 0000000000000030 x11: 0101010101010101 x10: 0000000000000040 x9 : ffff000009923580 x8 : ffff80001d400248 x7 : ffff80001d400270 x6 : 0000000000000000 x5 : ffff80001d400248 x4 : ffff80001d400270 x3 : 0000000000000000 x2 : 0000000000000001 x1 : 0000000000000001 x0 : 0000000000000000 Process swapper/0 (pid: 1, stack limit = 0xffff000008068000) Call trace: Exception stack(0xffff00000806ba40 to 0xffff00000806bb80) ba40: 0000000000000000 0000000000000001 0000000000000001 0000000000000000 ba60: ffff80001d400270 ffff80001d400248 0000000000000000 ffff80001d400270 ba80: ffff80001d400248 ffff000009923580 0000000000000040 0101010101010101 baa0: 0000000000000030 0000000000000000 0140000000000000 ffffffffffffffff bac0: 0000000000000019 0000000000000001 0000000000000000 ffff80001db6f418 bae0: ffff80001d9f4810 0000000000000000 ffff80001db6f438 ffff80001db6f570 bb00: 0000000000000000 ffff80001efee760 0000000000000001 000000000000000c bb20: 0000000000000024 ffff00000806bb80 ffff000008e25ccc ffff00000806bb80 bb40: ffff000008e25cdc 0000000060000045 ffff00000806bb60 ffff0000081189b8 bb60: ffffffffffffffff ffff00000811cf1c ffff00000806bb80 ffff000008e25cdc [<ffff000008e25cdc>] armada_37xx_pinctrl_probe+0x5f8/0x670 [<ffff00000859d8c8>] platform_drv_probe+0x58/0xb8 [<ffff00000859bb44>] driver_probe_device+0x22c/0x2d8 [<ffff00000859bcac>] __driver_attach+0xbc/0xc0 [<ffff000008599c84>] bus_for_each_dev+0x4c/0x98 [<ffff00000859b440>] driver_attach+0x20/0x28 [<ffff00000859af90>] bus_add_driver+0x1b8/0x228 [<ffff00000859c648>] driver_register+0x60/0xf8 [<ffff00000859df64>] __platform_driver_probe+0x74/0x130 [<ffff000008e256dc>] armada_37xx_pinctrl_driver_init+0x20/0x28 [<ffff000008083980>] do_one_initcall+0x38/0x128 [<ffff000008e00cf4>] kernel_init_freeable+0x188/0x22c [<ffff0000089b56e8>] kernel_init+0x10/0x100 [<ffff000008084bb0>] ret_from_fork+0x10/0x18 Code: f9403fa2 12001341 1100075a 9ac12041 (b9000001) ---[ end trace 8b0f4e05e1603208 ]--- This patch moves the initialization of the mask field in the irq_startup function. However some callbacks such as irq_set_type and irq_set_wake could be called before irq_startup. For those functions the mask is computed at each call which is not a issue as these functions are not located in a hot path but are used sporadically for configuration. Fixes: dc749a09ea5e ("gpiolib: allow gpio irqchip to map irqs dynamically") Cc: <stable@vger.kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: armada-37xx: constify pinconf_ops, pinctrl_ops, and pinmux_ops structuresJulia Lawall1-1/+1
This pinconf_ops structure is only stored in the const pinconf_ops field of a pinctrl_desc structure. Make the pinconf_ops structure const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-14pinctrl: armada-37xx: add static to local dataMasahiro Yamada1-2/+2
Detected by sparse. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-07pinctrl: armada-37xx: Fix number of pin in south bridgeGregory CLEMENT1-1/+1
On the south bridge we have pin from to 29, so it gives 30 pins (and not 29). Without this patch the kernel complain with the following traces: cat /sys/kernel/debug/pinctrl/d0018800.pinctrl/pingroups [ 154.530205] armada-37xx-pinctrl d0018800.pinctrl: failed to get pin(29) name [ 154.537567] ------------[ cut here ]------------ [ 154.542348] WARNING: CPU: 1 PID: 1347 at /home/gclement/open/kernel/marvell-mainline-linux/drivers/pinctrl/core.c:1610 pinctrl_groups_show+0x15c/0x1a0 [ 154.555918] Modules linked in: [ 154.558890] CPU: 1 PID: 1347 Comm: cat Tainted: G W 4.13.0-rc1-00001-g19e1b9fa219d #525 [ 154.568316] Hardware name: Marvell Armada 3720 Development Board DB-88F3720-DDR3 (DT) [ 154.576311] task: ffff80001d32d100 task.stack: ffff80001bdc0000 [ 154.583048] PC is at pinctrl_groups_show+0x15c/0x1a0 [ 154.587816] LR is at pinctrl_groups_show+0x148/0x1a0 [ 154.592847] pc : [<ffff0000083e3adc>] lr : [<ffff0000083e3ac8>] pstate: 00000145 [ 154.600840] sp : ffff80001bdc3c80 [ 154.604255] x29: ffff80001bdc3c80 x28: 00000000f7750000 [ 154.609825] x27: ffff80001d05d198 x26: 0000000000000009 [ 154.615224] x25: ffff0000089ead20 x24: 0000000000000002 [ 154.620705] x23: ffff000008c8e1d0 x22: ffff80001be55700 [ 154.626187] x21: ffff80001d05d100 x20: 0000000000000005 [ 154.631667] x19: 0000000000000006 x18: 0000000000000010 [ 154.637238] x17: 0000000000000000 x16: ffff0000081fc4b8 [ 154.642726] x15: 0000000000000006 x14: ffff0000899e537f [ 154.648214] x13: ffff0000099e538d x12: 206f742064656c69 [ 154.653613] x11: 6166203a6c727463 x10: 0000000005f5e0ff [ 154.659094] x9 : ffff80001bdc38c0 x8 : 286e697020746567 [ 154.664576] x7 : ffff000008551870 x6 : 000000000000011b [ 154.670146] x5 : 0000000000000000 x4 : 0000000000000000 [ 154.675544] x3 : 0000000000000000 x2 : 0000000000000000 [ 154.681025] x1 : ffff000008c8e1d0 x0 : ffff80001be55700 [ 154.686507] Call trace: [ 154.688668] Exception stack(0xffff80001bdc3ab0 to 0xffff80001bdc3be0) [ 154.695224] 3aa0: 0000000000000006 0001000000000000 [ 154.703310] 3ac0: ffff80001bdc3c80 ffff0000083e3adc ffff80001bdc3bb0 00000000ffffffd8 [ 154.711304] 3ae0: 4554535953425553 6f6674616c703d4d 4349564544006d72 6674616c702b3d45 [ 154.719478] 3b00: 313030643a6d726f 6e69702e30303838 ffff80006c727463 ffff0000089635d8 [ 154.727562] 3b20: ffff80001d1ca0cb ffff000008af0fa4 ffff80001bdc3b40 ffff000008c8e1dc [ 154.735648] 3b40: ffff80001bdc3bc0 ffff000008223174 ffff80001be55700 ffff000008c8e1d0 [ 154.743731] 3b60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ 154.752354] 3b80: 000000000000011b ffff000008551870 286e697020746567 ffff80001bdc38c0 [ 154.760446] 3ba0: 0000000005f5e0ff 6166203a6c727463 206f742064656c69 ffff0000099e538d [ 154.767910] 3bc0: ffff0000899e537f 0000000000000006 ffff0000081fc4b8 0000000000000000 [ 154.776085] [<ffff0000083e3adc>] pinctrl_groups_show+0x15c/0x1a0 [ 154.782823] [<ffff000008222abc>] seq_read+0x184/0x460 [ 154.787505] [<ffff000008344120>] full_proxy_read+0x60/0xa8 [ 154.793431] [<ffff0000081f9bec>] __vfs_read+0x1c/0x110 [ 154.799001] [<ffff0000081faff4>] vfs_read+0x84/0x140 [ 154.803860] [<ffff0000081fc4fc>] SyS_read+0x44/0xa0 [ 154.808983] [<ffff000008082f30>] el0_svc_naked+0x24/0x28 [ 154.814459] ---[ end trace 4cbb00a92d616b95 ]--- Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-07pinctrl: armada-37xx: Fix the pin 23 on south bridgeGregory CLEMENT1-6/+17
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible with the merge of the commit 07d065abf93d "arm64: dts: marvell: armada-3720-db: Add vqmmc regulator for SD slot", the gpio regulator used the gpio 23, due to this the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Cc: stable@vger.kernel.org Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-29pinctrl: armada-37xx: Fix number of pin in sdio_sbGregory CLEMENT1-2/+2
The sdio_sb group is composed of 6 pins and not 5. Reported-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-29pinctrl: armada-37xx: Fix uart2 group selection register maskKen Ma1-2/+3
If north bridge selection register bit1 is clear, pins [10:8] are for SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn and CTSn, so bit1 should be added to uart2 group and it must be set for both "gpio" and "uart" functions of uart2 group. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-16pinctrl: mvebu: add driver for Armada CP110 pinctrlHanna Hawa3-0/+692
This commit adds a pinctrl driver for the CP110 part of the Marvell Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all the MPP pins are available. On the other side, the Armada 8K has two CP110, and the available MPPs are split between the master CP110 (MPPs 32 to 62) and the slave CP110 (MPPs 0 to 31). The register interface to control the MPPs is however the same as all other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic. Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl and 4.9 changes: - converted to simple_mmio - converted to syscon/regmap - removed unimplemented .remove function - dropped DTS changes - defered gpio ranges to DT - fixed warning - properly set soc->nmodes -- rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> [ add missing MPP[61:56] function 14 (SDIO) -- Konstantin Porotchkin] Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [ allow to properly register more then one instance of this driver -- Grzegorz Jaszczyk] Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> [ - rebased on 4.12-rc1 - fixed the 80 character limit for mvebu_mpp_mode array - aligned the compatible name on the ones already used - fixed the MPP table for CP110: some MPP are not available on Armada 7K -- Gregory CLEMENT] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-16pinctrl: mvebu: add driver for Armada AP806 pinctrlHanna Hawa3-0/+145
This commit adds a pinctrl driver for the pin-muxing controller found in the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register interface is compatible with the one used by previous mvebu pin controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c is used. Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Shadi Ammouri <shadi@marvell.com> [updated for mvebu pinctrl changes - converted to simple_mmio - removed unimplemented .remove function - removed DTS description - converted to use syscon/regmap --rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-16pinctrl: avoid PLAT_ORION dependencyRussell King1-4/+0
Armada 8040 also needs orion pinctrl, and as these symbols are only selected, there's no need to make them depend on PLAT_ORION. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-16pinctrl: mvebu: remove the offset property for regmapGregory CLEMENT2-6/+2
The offset property of the pinctrl node, when a regmap is used in the device tree, was never used nor documented in the binding. Moreover, the compatible string is enough to let the driver know which offset using. So this patch removes the property and move the information at the driver level. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-22pinctrl: armada-37xx: Add irqchip supportGregory CLEMENT1-0/+229
The Armada 37xx SoCs can handle interrupt through GPIO. However it can only manage the edge ones. The way the interrupt are managed is classical so we can use the generic interrupt chip model. The only unusual "feature" is that many interrupts are connected to the parent interrupt controller. But we do not take advantage of this and use the chained irq with all of them. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: armada-37xx: Add gpio supportGregory CLEMENT1-14/+114
GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpiolib and the pinctrl drivers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: armada-37xx: Add pin controller support for Armada 37xxGregory CLEMENT3-1/+657
The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-13pinctrl: mvebu: make bool drivers explicitly non-modularPaul Gortmaker9-65/+9
None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get the exact same change, so they are handled in batch. Changes are (1) use builtin_platform_driver, (2) dont use module.h (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE, and (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags. For the dove driver we explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. We deleted the MODULE_LICENSE etc. tags since all that information is already contained at the top of the file in the comments. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-30Merge branch 'ib-mvebu-98dx3236' into develLinus Walleij1-0/+156
2017-01-30pinctrl: mvebu: pinctrl driver for 98DX3236 SoCKalyan Kinthada1-0/+156
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-26pinctrl: mvebu: remove unused variableArnd Bergmann1-1/+0
A cleanup caused a harmless warning: drivers/pinctrl/mvebu/pinctrl-kirkwood.c: In function 'kirkwood_pinctrl_probe': drivers/pinctrl/mvebu/pinctrl-kirkwood.c:460:19: error: unused variable 'res' [-Werror=unused-variable] The obvious fix is to remove the declaration of the now unused variable. Fixes: ad9ec4ecee68 ("pinctrl: mvebu: switch drivers to generic simple mmio") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-18pinctrl: mvebu: add simple regmap based pinctrl implementationRussell King2-1/+75
Add a simple regmap based pinctrl implementation for mvebu, for syscon based regmap drivers. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-18pinctrl: mvebu: switch drivers to generic simple mmioRussell King8-186/+45
Move the mvebu pinctrl drivers over to the generic simple mmio implementation, saving a substantial number of lines of code in the process. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-18pinctrl: mvebu: provide generic simple mmio-based implementationRussell King2-0/+63
Provide a generic simple mmio-based probe function and methods, which pinctrl drivers can use to initialise the mvebu pinctrl subsystem. Most mvebu pinctrl drivers can use this. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-18pinctrl: mvebu: provide per-control private dataRussell King10-39/+88
Provide per-control private data into each mvebu pinctrl method, which will allow us to provide some completely generic helpers without the global variable and per-instance function definitions that would be required when we have multiple pin controllers on a SoC. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-18pinctrl: mvebu: constify mvebu_mpp_ctrl structuresRussell King10-16/+16
As the mvebu_mpp_ctrl structures contain function pointers, it is preferable for these to be made read-only to prevent the function pointers being modified. So make these const. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-17pinctrl: mvebu: Use seq_putc() in mvebu_pinconf_group_dbg_show()Markus Elfring1-8/+8
Single characters should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-17pinctrl: mvebu: Use seq_puts() in mvebu_pinconf_group_dbg_show()Markus Elfring1-4/+5
Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-17pinctrl: mvebu: Delete an unnecessary return statement in mvebu_pinconf_group_dbg_show()Markus Elfring1-1/+0
The script "checkpatch.pl" pointed information out like the following. WARNING: void function return statements are not generally useful Thus remove such a statement in the affected function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-17pinctrl: mvebu: Delete an error message for a failed memory allocation in three functionsMarkus Elfring1-11/+3
The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-17pinctrl: mvebu: Use kmalloc_array() in mvebu_pinctrl_dt_node_to_map()Markus Elfring1-1/+1
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kmalloc_array". This issue was detected by using the Coccinelle software. * Replace the specification of a data structure by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-21pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181Jamie Lentin1-11/+12
As far as I'm aware the mv88f5181-b1 and mv88f5181l are the same at the pinctrl level, so re-use the definitions for both. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin <jm@lentin.co.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-07-24pinctrl: fix pincontrol definition for marvellAndreas Klinger1-42/+43
On Marvell mv88f6180 with pin control driver one can not use multi purpose pins 35 through 44. I'm using this controller on an embedded board and i found that the pin multiplexing is not the same as in the hardware spezification. This patch alters the pin description so that mpp pins 0 to 19 as well as 35 to 44 are usable. Pin settings i used can be found here: http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf Signed-off-by: Andreas Klinger <ak@it-klinger.de> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-04-21pinctrl: mvebu: Use devm_pinctrl_register() for pinctrl registrationLaxman Dewangan10-55/+2
Use devm_pinctrl_register() for pin control registration and remove need of .remove callback. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: Fabian Frederick <fabf@skynet.be> Cc: Andrew Andrianov <andrew@ncrmnt.org> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-13pinctrl: mvebu: fix num_settings in mpp group assignmentSebastian Hesselbarth1-3/+6
When assigning mpp settings from static mpp modes to mpp groups, we do not want any groups that have no supported setting for a specific Kirkwood variant. However, when there is at least a single supported setting, we need to assign the number of all settings in this mode to grp->num_settings as we are reusing the static modes table. Fixes: 0581b16b1840 ("pinctrl: mvebu: complain about missing group after checking variant") Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-09pinctrl: mvebu: complain about missing group after checking variantSebastian Hesselbarth1-13/+16
Common MVEBU pinctrl driver core gets an array of controls to modify a specific set of registers and an array of modes for each pingroup from each of the different SoC families of MVEBU. Some SoC families comprise different variants that differ in available pingroups and also controls, but to ease driver development, we can pass a variant mask to disable specific pingroups for some variants. However, controls are limited to the true number of pinctrl groups avaiable on a variant. Now, when pinctrl core driver parses over above arrays, it tries to match modes with available controls and complains about missing controls for modes that are passed to the core but actually are not avaiable on a variant with: kirkwood-pinctrl f1010000.pin-controller: unknown pinctrl group 36 This warning is a false-positive and annoying, so move the warning after we checked the variant mask for each mode setting. Also, if there is no supported setting for this variant, do not complain at all. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reported-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-01pinctrl: mvebu: guard sub-directory with CONFIG_PINCTRL_MVEBUMasahiro Yamada1-1/+1
CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION to guard the drivers/pinctrl/mvebu/ directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-24Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds6-203/+222
Pull pin control updates from Linus Walleij: "Here is the bulk of pin control changes for the v4.2 series: Quite a lot of new SoC subdrivers and two new main drivers this time, apart from that business as usual. Details: Core functionality: - Enable exclusive pin ownership: it is possible to flag a pin controller so that GPIO and other functions cannot use a single pin simultaneously. New drivers: - NXP LPC18xx System Control Unit pin controller - Imagination Pistachio SoC pin controller New subdrivers: - Freescale i.MX7d SoC - Intel Sunrisepoint-H PCH - Renesas PFC R8A7793 - Renesas PFC R8A7794 - Mediatek MT6397, MT8127 - SiRF Atlas 7 - Allwinner A33 - Qualcomm MSM8660 - Marvell Armada 395 - Rockchip RK3368 Cleanups: - A big cleanup of the Marvell MVEBU driver rectifying it to correspond to reality - Drop platform device probing from the SH PFC driver, we are now a DT only shop for SuperH - Drop obsolte multi-platform check for SH PFC - Various janitorial: constification, grammar etc Improvements: - The AT91 GPIO portions now supports the set_multiple() feature - Split out SPI pins on the Xilinx Zynq - Support DTs without specific function nodes in the i.MX driver" * tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: rockchip: add support for the rk3368 pinctrl: rockchip: generalize perpin driver-strength setting pinctrl: sh-pfc: r8a7794: add SDHI pin groups pinctrl: sh-pfc: r8a7794: add MMCIF pin groups pinctrl: sh-pfc: add R8A7794 PFC support pinctrl: make pinctrl_register() return proper error code pinctrl: mvebu: armada-39x: add support for Armada 395 variant pinctrl: mvebu: armada-39x: add missing SATA functions pinctrl: mvebu: armada-39x: add missing PCIe functions pinctrl: mvebu: armada-38x: add ptp functions pinctrl: mvebu: armada-38x: add ua1 functions pinctrl: mvebu: armada-38x: add nand functions pinctrl: mvebu: armada-38x: add sata functions pinctrl: mvebu: armada-xp: add dram functions pinctrl: mvebu: armada-xp: add nand rb function pinctrl: mvebu: armada-xp: add spi1 function pinctrl: mvebu: armada-39x: normalize ref clock naming pinctrl: mvebu: armada-xp: rename spi to spi0 pinctrl: mvebu: armada-370: align spi1 clock pin naming pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet ...
2015-06-10pinctrl: make pinctrl_register() return proper error codeMasahiro Yamada1-2/+2
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Ray Jui <rjui@broadcom.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add support for Armada 395 variantThomas Petazzoni1-17/+23
The Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add missing SATA functionsThomas Petazzoni1-0/+9
The latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add missing PCIe functionsThomas Petazzoni1-0/+2
The latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add ptp functionsThomas Petazzoni1-3/+6
The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add ua1 functionsThomas Petazzoni1-6/+12
The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add nand functionsThomas Petazzoni1-2/+4
The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add sata functionsThomas Petazzoni1-2/+4
The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add dram functionsThomas Petazzoni1-2/+5
The latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add nand rb functionThomas Petazzoni1-1/+2
The latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add spi1 functionThomas Petazzoni1-7/+18
The latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: normalize ref clock namingThomas Petazzoni1-4/+4
This commit normalizes the subnames of the reference clock MPP pins in the Armada 39x pinctrl driver to match with the name used on other SoCs. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: rename spi to spi0Thomas Petazzoni1-11/+11
After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'. In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'. This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-370: align spi1 clock pin namingThomas Petazzoni1-1/+1
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly. Since this commit only changes the subname, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheetThomas Petazzoni1-1/+1
For consistency with the datasheet, this commit renames the VDD function of the MPP4 pin. While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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