linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2013-02-05	pinctrl: sunxi: add of_xlate function	Maxime Ripard	1	-0/+20
	Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01	ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10	Maxime Ripard	1	-0/+554
	Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01	pinctrl: sunxi: Document sun5i pins functions	Maxime Ripard	1	-4/+4
	Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-29	ARM: sunxi: gpio: Add Allwinner SoCs GPIO drivers	Maxime Ripard	1	-2/+132
	The IP responsible for the muxing on the Allwinner SoCs are also handling the GPIOs on the system. This patch adds the needed driver that relies on the pinctrl driver for most of its operations. The number of pins available for GPIOs operations are already declared in the pinctrl driver, we only need to probe a generic driver to handle the banks available for each SoC. This driver has been tested on a A13-Olinuxino. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22	ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i	Maxime Ripard	1	-0/+253
	Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22	ARM: sunxi: Add pinctrl driver for Allwinner SoCs	Maxime Ripard	1	-0/+548
	The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>