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path: root/drivers/pinctrl/sh-pfc/pfc-r8a7791.c (follow)
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2018-09-28pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotiveGeert Uytterhoeven1-8/+8
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several automotive-specific peripherals. Currently pin groups and functions for automotive-specific peripherals are grouped in arrays named after the automative SoC part numbers. Rename them to "automotive" for clarity and consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-19pinctrl: sh-pfc: r8a7791: Add r8a7744 supportBiju Das1-0/+22
Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3) and RZ/G1M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto1-4/+1
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-19pinctrl: sh-pfc: r8a7791: Add tpu groups and functionFabrizio Castro1-2/+40
This patch adds tpu groups and function to r8a7743/r8a7791/r8a7793. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05pinctrl: sh-pfc: r8a7791: Add can_clk functionFabrizio Castro1-1/+21
This patch adds can_clk function to r8a7743/r8a7791 which is cleaner, and allows for independent configuration. We keep the can_clk* pins definitions from within can0_groups and can1_groups for uniformity and backwards compatibility. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-07-17pinctrl: sh-pfc: r8a7791: Add missing mmc_data8_b pin groupGeert Uytterhoeven1-1/+14
Pins D6 and D7 of the MMC interface can be muxed to two different sets of pins, but currently only one set is supported. Add a pin group for the alternative set to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Tested-by: Chris Paterson <chris.paterson2@renesas.com>
2017-05-16pinctrl: sh-pfc: r8a7791: Add R8A7743 supportSergei Shtylyov1-420/+460
Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3), however it doesn't have several automotive specific peripherals. Annotate all the items that only exist on the R-Car SoCs and only supply the pin groups/functions existing on a given SoC... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> [geert: Drop annotations, as they are implied by pin groups/functions] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-05-15pinctrl: sh-pfc: r8a7791: Grand I2C renameSergei Shtylyov1-227/+234
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which called all the I2C signals {SCL|SDA}<n> and MOD_SEL register fields SEL_IIC<n> without making a difference between two types of the I2C controllers used. The recent manual calls the signals {I2C|IIC}<n>_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC}<n> finally making this difference. Follow the suit... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04pinctrl: sh-pfc: r8a7791: Fix IPSR comment typosSergei Shtylyov1-3/+3
The IPSR field names in the comments have been fat-fingered in a couple places -- fix those silly typos... Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04pinctrl: sh-pfc: r8a7791: Fix SCIF2 pinmux dataSergei Shtylyov1-1/+1
PINMUX_IPSR_MSEL() macro invocation for the TX2 signal has apparently wrong 1st argument -- most probably a result of cut&paste programming... Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signalSergei Shtylyov1-3/+4
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which omitted the DVC_MUTE signal altogether in the PFC section. The modern manual has the signal described, so just add the necassary data to the driver... Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-04-04pinctrl: sh-pfc: r8a7791: Add missing HSCIF1 pinmux dataSergei Shtylyov1-0/+3
The R8A7791 PFC driver was apparently based on the preliminary revisions of the user's manual, which omitted the HSCIF1 group E signals in the IPSR4 register description. This would cause HSCIF1's probe to fail with the messages like below: sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1989 sh-sci e62c8000.serial: Error applying setting, reverse things back sh-sci: probe of e62c8000.serial failed with error -22 Add the neceassary PINMUX_IPSR_MSEL() invocations for the HSCK1_E, HCTS1#_E, and HRTS1#_E signals... Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-20pinctrl: sh-pfc: r8a7791: Add ADI pinconf supportJacopo Mondi1-0/+86
Add pin configuration support for Gyro-ADC, named ADI on r8a7791 SoC. Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Tested-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-27pinctrl: sh-pfc: r8a7793: Implement voltage switching for SDHISimon Horman1-0/+1
Voltage switching is the same as on the r8a7791. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-14pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHISimon Horman1-1/+28
All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-06-21pinctrl: sh-pfc: Improve core and user API separationGeert Uytterhoeven1-1/+0
The Renesas Pin Function Controller uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Several SoC-specific drivers include core.h, as they need the sh_pfc structure, which is passed explicitly to the various SoC-specific callbacks, and used there. Hence move its definition from core.h to sh_pfc.h, and remove the inclusion of core.h from all SoC-specific files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-08pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()Geert Uytterhoeven1-312/+312
This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-12-16pinctrl: sh-pfc: r8a7791: add EtherAVB pin groupsSergei Shtylyov1-0/+93
Add the EtherAVB pin groups to the R8A7791 PFC driver. Also add the copyright for all the Cogent Embedded's past work on this file. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-08pinctrl: sh-pfc: r8a7791: Add SCIF_CLK supportGeert Uytterhoeven1-0/+25
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-30pinctrl: sh-pfc: Share/reuse same PORT_GP_x() macrosKuninori Morimoto1-15/+0
Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-11-30pinctrl: sh-pfc: r8a7791: Use PINMUX_SINGLE() instead of raw PINMUX_DATA()Geert Uytterhoeven1-17/+17
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20pinctrl: sh-pfc: Stop including <linux/platform_data/gpio-rcar.h>Geert Uytterhoeven1-1/+0
This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-10-20pinctrl: sh-pfc: Rename .gpio_data[] to .pinmux_data[]Geert Uytterhoeven1-4/+4
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-10-20pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header fileSergei Shtylyov1-18/+0
R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared header file... Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02pinctrl: sh-pfc: r8a7791: use PINMUX_IPSR_MSEL()Kuninori Morimoto1-538/+538
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-10-02pinctrl: sh-pfc: r8a7791/r8a7793: Correct SCIFB1_B SCK MOD_SEL valueGeert Uytterhoeven1-1/+1
When using serial port SCIFB1_B, transmit works, but nothing is received. Receive fails because the SCIFB1_SCK_B settings configure the wrong value for the sel_scifb1 field in the Module Select Register (MOD_SEL), due to an ambiguity in the R-Car M2-W and M2-N datasheets. Tested on r8a7791/koelsch using pins 53 (TXD) and 72 (RXD) on EXIO Connector A. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-16sh-pfc: r8a7791: remove non-existing GPIO pinsLaurent Pinchart1-2/+17
GPIO banks 1 and 7 are missing pins 26 to 31. Remove them. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-01pinctrl: Spelling s/reseved/reserved/Geert Uytterhoeven1-19/+19
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-19pinctrl: sh-pfc: r8a7791: Add PWM pin groups and functionsYoshihiro Shimoda1-0/+125
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-12pinctrl: sh-pfc: Add r8a7793 supportUlrich Hecht1-0/+23
Regarding pin control, r8a7791 and r8a7793 are identical, so it is sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7791: add MLB+ pin groupSergei Shtylyov1-0/+13
Add MLB+ 3-pin mode pin group to R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7791: fix typo in MLB_CLKSergei Shtylyov1-4/+4
The R8A7791 manual sometimes calls the signal MLB_CLK and sometimes MLB_CK; the latter can only be encountered in the PFC section and is probably just a typo (this signal is always called MLB_CLK in the R8A7790 manual). Fix occurences of MLB_CK throughout the R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17sh-pfc: r8a7791: fix CAN pin groupsSergei Shtylyov1-4/+4
I had made last-minute changes before submitting the patch "sh-pfc: r8a7791: add CAN pin groups"; now I'm seeing that they weren't complete: I had missed update to the pin group names in pin[01]_groups[]. Drop the "_a" suffixes there. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11sh-pfc: r8a7791: add CAN pin groupsSergei Shtylyov1-0/+167
Add CAN0/1 data/clock pin groups to R8A7791 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: sh-pfc: r8a7791: Add HSCIF pin supportNobuhiro Iwamatsu1-0/+250
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-03Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into nextLinus Torvalds1-10/+402
Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
2014-04-23sh-pfc: r8a7791: Fix definition of MOD_SEL3Phil Edworthy1-1/+1
There is a missing 0 entry from the MOD_SEL3 table. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add Audio pin supportKuninori Morimoto1-0/+61
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add SSI pin supportKuninori Morimoto1-0/+314
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groupsLaurent Pinchart1-10/+27
The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-01Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds1-0/+596
Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
2014-03-05pinctrl: sh-pfc: r8a7791: SD1_CLK fixMagnus Damm1-2/+4
Fix the SD1_CLK handling for r8a7791. Without this patch it is impossible to request all pins needed for SDHI1 on the Koelsch board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groupsGeert Uytterhoeven1-0/+469
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: pfc: r8a7791: add mux data for IIC(B) coresWolfram Sang1-0/+64
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: sh-pfc: r8a7791: Add QSPI pin groupsGeert Uytterhoeven1-0/+63
A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-01-07pinctrl: sh-pfc: r8a7791: Add I2C pinsValentine Barshak1-0/+196
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Add VIN pinsValentine Barshak1-0/+360
This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins togetherValentine Barshak1-28/+12
This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart1-2/+2
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10sh-pfc: r8a7791: Fix msiof groups to follow GROUPTakashi Yoshii1-6/+15
SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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