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path: root/drivers/pinctrl/sh-pfc/pfc-r8a77995.c (follow)
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2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven1-1/+1
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara1-6/+6
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car H3 ES1.x, V3M, V3H, and D3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven1-6/+7
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven1-42/+42
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Add missing #include <linux/errno.h>Geert Uytterhoeven1-0/+1
Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resumeMarek Vasut1-0/+10
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numberingTakeshi Kihara1-4/+7
MOD_SEL register bit numbering was different from R-Car D3 SoC and R-Car H3/M3-[WN] SoCs. MOD_SEL 1-bit H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'0 b'0 Set Value = H'1 b'1 b'1 MOD_SEL 2-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'00 b'00 Set Value = H'1 b'01 b'10 Set Value = H'2 b'10 b'01 Set Value = H'3 b'11 b'11 MOD_SEL 3-bits H3/M3-[WN] D3 =============== ========== ===== Set Value = H'0 b'000 b'000 Set Value = H'1 b'001 b'100 Set Value = H'2 b'010 b'010 Set Value = H'3 b'011 b'110 Set Value = H'4 b'100 b'001 Set Value = H'5 b'101 b'101 Set Value = H'6 b'110 b'011 Set Value = H'7 b'111 b'111 This patch replaces the #define name and value of MOD_SEL. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Fixes: 794a67117646 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") [shimoda: split a patch per SoC and revise the commit log] Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Use a macro to do the actual reordering] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77995: Remove bogus SEL_PWM[0-3]_3 configurationsGeert Uytterhoeven1-4/+4
While the SEL_PWM[0-3] fields in the Module Select Register 0 support 4 possible configurations per PWM pin, only the first 3 are valid. Replace the invalid and unused configurations for SEL_PWM[0-3]_3 by dummies. Fixes: 794a6711764658a1 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2,PHYS}()Geert Uytterhoeven1-6/+0
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and will conflict with generic macros that are to be added. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-11pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto1-4/+1
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functionsTakeshi Kihara1-0/+365
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [ykaneko0929@gmail.com: fix the order of definitions] Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21pinctrl: sh-pfc: r8a77995: Deduplicate VIN4 pin definitionsUlrich Hecht1-118/+36
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies in pin definitions. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21pinctrl: sh-pfc: r8a77995: Correct VIN4 18-bit pinsUlrich Hecht1-6/+6
RGB666 has a pin assignment that differs from the other formats. Fixes: fbd452aeb49e552e ("pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function") Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-21pinctrl: sh-pfc: r8a77995: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven1-4/+6
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: 66abd968d0ef3eb1 ("pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-02-26pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and functionUlrich Hecht1-0/+192
This patch adds VIN4 pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20pinctrl: sh-pfc: r8a77995: Add DU pins, groups and functionUlrich Hecht1-0/+101
This patch adds DU pins, groups and function for the R8A77995 (D3) SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05pinctrl: sh-pfc: r8a77995: Add CAN FD supportUlrich Hecht1-0/+27
This patch adds CAN FD[0-1] pinmux support to the r8a77995 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05pinctrl: sh-pfc: r8a77995: Add CAN supportUlrich Hecht1-0/+59
This patch adds CAN[0-1] pinmux support to the r8a77995 SoC. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-05pinctrl: sh-pfc: r8a77995: Add missing pins SCL0 and SDA0 to pinmux dataUlrich Hecht1-0/+2
Required for I2C0 operation. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-16pinctrl: sh-pfc: r8a77995: Remove USB0_IDIN and USB0_IDPU pinsGeert Uytterhoeven1-4/+2
R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017 removed the USB0_IDIN and USB0_IDPU pins on R-Car D3. This change has no functional impact, as these definitions were unused. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-11pinctrl: sh-pfc: r8a77995: Add Audio SSI pin supportKuninori Morimoto1-0/+60
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-11pinctrl: sh-pfc: r8a77995: Add Audio clock pin supportKuninori Morimoto1-0/+42
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-04pinctrl: sh-pfc: r8a77995: Add PWM pins, groups and functionsTakeshi Kihara1-0/+152
This patch adds support for PWM on r8a77995. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-09-19pinctrl: sh-pfc: r8a77995: Add USB2.0 host supportTakeshi Kihara1-0/+15
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-09-19pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functionsYoshihiro Shimoda1-0/+119
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add voltage switch operations for MMCTakeshi Kihara1-1/+18
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add MMC pins, groups and functionsTakeshi Kihara1-0/+50
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add I2C pins, groups and functionsTakeshi Kihara1-0/+71
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: r8a77995: Add SCIF pins, groups and functionsTakeshi Kihara1-0/+262
This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: Fix swapped RX3_B and SCK3_B pins] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-08-16pinctrl: sh-pfc: Initial R8A77995 PFC supportTakeshi Kihara1-0/+1412
This patch adds initial pinctrl driver to support for the R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: whitespace] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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