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2015-02-05sh-pfc: emev2 - Fix mangled author nameGeert Uytterhoeven1-1/+1
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-29pinctrl: sh-pfc: sh7372: Remove PFC supportMagnus Damm5-2661/+0
Remove sh7372 PFC support as part of the sh7372 and Mackerel legacy code removal. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-27sh-pfc: Add emev2 pinmux supportNiklas Söderlund5-0/+1727
Add PFC support for the EMMA Mobile EV2 SoC including pin groups for on-chip devices. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-27sh-pfc: add macro to define pinmux without functionNiklas Söderlund1-0/+2
Used to define pinmux configurations where the pinmux function have no representation in the configuration registers but instead solely depends on a group selection. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7790: add MLB+ pin groupSergei Shtylyov1-0/+13
Add MLB+ 3-pin mode pin group to R8A7790 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7791: add MLB+ pin groupSergei Shtylyov1-0/+13
Add MLB+ 3-pin mode pin group to R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-15sh-pfc: r8a7791: fix typo in MLB_CLKSergei Shtylyov1-4/+4
The R8A7791 manual sometimes calls the signal MLB_CLK and sometimes MLB_CK; the latter can only be encountered in the PFC section and is probably just a typo (this signal is always called MLB_CLK in the R8A7790 manual). Fix occurences of MLB_CK throughout the R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-11pinctrl: pinconf-generic: Allow driver to specify DT paramsSoren Brinkmann1-1/+1
Additionally to the generic DT parameters, allow drivers to provide driver-specific DT parameters to be used with the generic parser infrastructure. To achieve this 'struct pinctrl_desc' is extended to pass custom pinconf option to the core. In order to pass this kind of information, the related data structures - 'struct pinconf_generic_dt_params', 'pin_config_item' - are moved from pinconf internals to the pinconf-generic header. Additionally pinconfg-generic is refactored to not only iterate over the generic pinconf parameters but also take the parameters into account that are provided through the driver's 'struct pinctrl_desc'. In particular 'pinconf_generic_parse_dt_config()' and 'pinconf_generic_dump' helpers are split into two parts each. In order to have a more generic helper that can be used to process the generic parameters as well as the driver-specific ones. v2: - fix typo - add missing documentation for @conf_items member in struct - rebase to pinctrl/devel: conflict in abx500 - rename _pinconf_generic_dump() to pinconf_generic_dump_one() - removed '_' from _parse_dt_cfg() - removed BUG_ONs, error condition is handled in if statements - removed pinconf_generic_dump_group() & pinconf_generic_dump_pin helpers - fixed up corresponding call sites - renamed pinconf_generic_dump() to pinconf_generic_dump_pins() - added kernel-doc to pinconf_generic_dump_pins() - add kernel-doc - more verbose commit message Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-20pinctrl: sh-pfc: drop owner assignment from platform_driversWolfram Sang1-1/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-07Merge tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds8-37/+16
Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.18 development series: - New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin controllers. - Incremental new features on the Rockchip, atlas 6, OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik. - Push Freescale drivers down into their own subdirectory. - Assorted sprays of syntax and semantic fixes" * tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: specify bindings for pins and groups pinctrl: nomadik: improve GPIO debug prints pinctrl: abx500: refactor DT parser to take two paths pinctrl: abx500: use helpers for map allocation/free pinctrl: alter device tree bindings for functions pinctrl: nomadik: refactor DT parser to take two paths pinctrl: nomadik: use utils map free function pinctrl: nomadik: use util function to reserve maps pinctrl: qcom: use restart_notifier mechanism for ps_hold pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation pinctrl: berlin: fix the dt_free_map function pinctrl: at91: disable PD or PU before enabling PU or PD pinctrl: st: remove gpiochip in failure cases pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add pinctrl: at91: Fix failure path in at91_gpio_probe path pinctrl: lantiq: Release gpiochip resources in fail case pinctrl: imx: detect uninitialized pins pinctrl: tegra: Add MIPI pad control pinctrl: at91: Switch to using managed clk_get pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges ...
2014-09-23pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocationLaurent Pinchart4-26/+5
The SoC data structure allocated at init time only holds a regulator pointer that is only used in the init function. Replace it with a local variable and get rid of the SoC data structure allocation altogether. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04pinctrl: sh-pfc: rename confusing pinmux ops variableLinus Walleij4-8/+8
The vtable named *pinmux_ops in the affected files are not really about pin multiplexing, but a struct related to some PFC-specific operations, inclusing pin config (bias setting). Rename the variable so as to avoid confusions. Acked-by: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-09-04pinctrl: clean up after enable refactoringLinus Walleij1-3/+3
commit 2243a87d90b42eb38bc281957df3e57c712b5e56 "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Fan Wu <fwu@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-08-17sh-pfc: r8a7791: fix CAN pin groupsSergei Shtylyov1-4/+4
I had made last-minute changes before submitting the patch "sh-pfc: r8a7791: add CAN pin groups"; now I'm seeing that they weren't complete: I had missed update to the pin group names in pin[01]_groups[]. Drop the "_a" suffixes there. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-22pinctrl: remove all usage of gpio_remove ret val in driver/pinctlabdoulaye berthe1-6/+3
Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11sh-pfc: sh73a0: Introduce the use of devm_regulator_registerHimangi Saraogi1-9/+2
This patch moves data allocated using regulator_register to devm_regulator_register and does away the calls to regulator_unregister. The sh73a0_pinmux_soc_exit function is no longer needed and is removed. Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Acked-by: Julia Lawall <julia.lawall@lip6.fr> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11sh-pfc: r8a7791: add CAN pin groupsSergei Shtylyov1-0/+167
Add CAN0/1 data/clock pin groups to R8A7791 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: avoid duplicated calling enable_pinmux_setting for a pinFan Wu1-22/+0
What the patch does: 1. Call pinmux_disable_setting ahead of pinmux_enable_setting each time pinctrl_select_state is called 2. Remove the HW disable operation in pinmux_disable_setting function. 3. Remove the disable ops in struct pinmux_ops 4. Remove all the disable ops users in current code base. Notes: 1. Great thanks for the suggestion from Linus, Tony Lindgren and Stephen Warren and Everyone that shared comments on this patch. 2. The patch also includes comment fixes from Stephen Warren. The reason why we do this: 1. To avoid duplicated calling of the enable_setting operation without disabling operation inbetween which will let the pin descriptor desc->mux_usecount increase monotonously. 2. The HW pin disable operation is not useful for any of the existing platforms. And this can be used to avoid the HW glitch after using the item #1 modification. In the following case, the issue can be reproduced: 1. There is a driver that need to switch pin state dynamically, e.g. between "sleep" and "default" state 2. The pin setting configuration in a DTS node may be like this: component a { pinctrl-names = "default", "sleep"; pinctrl-0 = <&a_grp_setting &c_grp_setting>; pinctrl-1 = <&b_grp_setting &c_grp_setting>; } The "c_grp_setting" config node is totally identical, maybe like following one: c_grp_setting: c_grp_setting { pinctrl-single,pins = <GPIO48 AF6>; } 3. When switching the pin state in the following official pinctrl sequence: pin = pinctrl_get(); state = pinctrl_lookup_state(wanted_state); pinctrl_select_state(state); pinctrl_put(); Test Result: 1. The switch is completed as expected, that is: the device's pin configuration is changed according to the description in the "wanted_state" group setting 2. The "desc->mux_usecount" of the corresponding pins in "c_group" is increased without being decreased, because the "desc" is for each physical pin while the setting is for each setting node in the DTS. Thus, if the "c_grp_setting" in pinctrl-0 is not disabled ahead of enabling "c_grp_setting" in pinctrl-1, the desc->mux_usecount will keep increasing without any chance to be decreased. According to the comments in the original code, only the setting, in old state but not in new state, will be "disabled" (calling pinmux_disable_setting), which is correct logic but not intact. We still need consider case that the setting is in both old state and new state. We can do this in the following two ways: 1. Avoid to "enable"(calling pinmux_enable_setting) the "same pin setting" repeatedly 2. "Disable"(calling pinmux_disable_setting) the "same pin setting", actually two setting instances, ahead of enabling them. Analysis: 1. The solution #2 is better because it can avoid too much iteration. 2. If we disable all of the settings in the old state and one of the setting(s) exist in the new state, the pins mux function change may happen when some SoC vendors defined the "pinctrl-single,function-off" in their DTS file. old_setting => disabled_setting => new_setting. 3. In the pinmux framework, when a pin state is switched, the setting in the old state should be marked as "disabled". Conclusion: 1. To Remove the HW disabling operation to above the glitch mentioned above. 2. Handle the issue mentioned above by disabling all of the settings in old state and then enable the all of the settings in new state. Signed-off-by: Fan Wu <fwu@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-11pinctrl: sh-pfc: r8a7791: Add HSCIF pin supportNobuhiro Iwamatsu1-0/+250
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-03Merge tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into nextLinus Torvalds6-12/+550
Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.16 development cycle: - Antoine Tenart made the get_group_pins() vtable entry optional. - Antoine also provides an entirely new driver for the Marvell Berlin SoC. This is unrelated to the existing MVEBU hardware driver and warrants its own separate driver. - reflected from the GPIO subsystem there is a number of refactorings to make pin control drivers with gpiochips use the new gpiolib irqchip helpers. The following drivers were converted to use the new infrastructure: * ST Microelectronics STiH416 and friends * The Atmel AT91 * The CSR SiRF (Prima2) * The Qualcomm MSM series - massive improvements in the Qualcomm MSM driver from Bjorn Andersson, Andy Gross and Kumar Gala. Among those new support for the IPQ8064 and MSM8x74 SoC variants. - support for the Freescale i.MX6 SoloX SoC variant. - massive improvements in the Allwinner sunxi driver from Boris Brezillon, Maxime Ripard and Chen-Yu Tsai. - Renesas PFC updates from Laurent Pinchart, Kuninori Morimoto, Wolfram Sang and Magnus Damm. - Cleanups and refactorings of the nVidia Tegra driver from Stepgen Warren. - the Exynos driver now supports the Exynos3250 SoC. - Intel BayTrail updates from Jin Yao, Mika Westerberg. - the MVEBU driver now supports the Orion5x SoC variants, which is part of the effort of getting rid of the old Marvell kludges in arch/arm/mach-orion5x - Rockchip driver updates from Heiko Stuebner. - a ton of cleanups and janitorial patches from Axel Lin. - some minor fixes and improvements here and there" * tag 'pinctrl-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: sirf: fix a bad conflict resolution pinctrl: msm: Add more MSM8X74 pin definitions pinctrl: qcom: ipq8064: Fix naming convention pinctrl: msm: Add missing sdc1 and sdc3 groups pinctrl: sirf: switch to using allocated state container pinctrl: Enable "power-source" to be extracted from DT files pinctrl: sunxi: create irq/pin mapping during init pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy pinctrl: berlin: Use devm_ioremap_resource() pinctrl: sirf: fix typo for GPIO bank number pinctrl: sunxi: depend on RESET_CONTROLLER pinctrl: sunxi: fix pin numbers passed to register offset helpers pinctrl: add pinctrl driver for imx6sx pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs pinctrl: msm: switch to using generic GPIO irqchip helpers pinctrl: sunxi: Fix multiple registration issue pinctrl: sunxi: Fix recursive dependency pinctrl: berlin: add the BG2CD pinctrl driver pinctrl: berlin: add the BG2 pinctrl driver pinctrl: berlin: add the BG2Q pinctrl driver ...
2014-05-23pinctrl: sh-pfc: r8a73a4: Allow Multiplatform BuildMagnus Damm1-0/+3
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed to enable r8a73a4 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23pinctrl: sh-pfc: sh73a0: Allow Multiplatform BuildMagnus Damm1-0/+2
Add #ifdefs to allow sh73a0 Multiplatform build. Needed to enable sh73a0 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23pinctrl: sh-pfc: r8a7740: Allow Multiplatform BuildMagnus Damm1-0/+2
Add #ifdefs to allow r8a7740 Multiplatform build. Needed to enable r8a7740 Multiplatform support. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatformLaurent Pinchart1-0/+5
In the multiplatform kernel case the IRQs associated with the PFC GPIOs are specified through DT. The pinmux_irq irq field is thus ignored by the code, and doesn't need to be set. This will allow removing the mach/irq.h include from pfc-*.c files that was required for the irq_pin() macro used to initialize the irq field. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23sh-pfc: r8a7791: Fix definition of MOD_SEL3Phil Edworthy1-1/+1
There is a missing 0 entry from the MOD_SEL3 table. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23sh-pfc: r8a7790: Fix definition of IPSR5Guido Piasenza1-2/+1
The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add mux data for IIC(B) coresWolfram Sang1-2/+116
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add i2c0 muxingWolfram Sang1-1/+21
Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add Audio pin supportKuninori Morimoto1-0/+61
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add SSI pin supportKuninori Morimoto1-0/+314
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groupsLaurent Pinchart1-10/+27
The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-01Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds2-0/+767
Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
2014-03-05pinctrl: sh-pfc: r8a7791: SD1_CLK fixMagnus Damm1-2/+4
Fix the SD1_CLK handling for r8a7791. Without this patch it is impossible to request all pins needed for SDHI1 on the Koelsch board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7791: Add alternative MSIOF pin groupsGeert Uytterhoeven1-0/+469
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-05pinctrl: sh-pfc: r8a7790: Add alternative MSIOF pin groupsGeert Uytterhoeven1-0/+129
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: pfc: r8a7791: add mux data for IIC(B) coresWolfram Sang1-0/+64
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-25pinctrl: sh-pfc: r8a7790: Add QSPI pin groupsGeert Uytterhoeven1-0/+33
A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-11pinctrl: sh-pfc: r8a7790: Break out USB0 OVC/VBUSMagnus Damm1-0/+9
Create a new group for the USB0 OVC/VBUS pin by itself. This allows us to monitor PWEN as GPIO on the Lager board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-10pinctrl: sh-pfc: r8a7791: Add QSPI pin groupsGeert Uytterhoeven1-0/+63
A QSPI function set consists of 3 groups: - qspi_ctrl (2 control wires) - qspi_data2 (2 data wires, for Single/Dual SPI) - qspi_data4 (4 data wires, for Quad SPI) Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-01-21Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds24-232/+1438
Pull bulk pin control changes from Linus Walleij: "This has been queued and tested for a while. Lots of action here, like in the GPIO tree, embedded stuff like this is really hot now it seems. Details in the signed tag. I'm especially happy about the Qualcomm driver as it is used in such a huge subset of mobile handsets out there, and these platforms in general need better upstream support - New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual" * tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sunxi: Honor GPIO output initial vaules pinctrl: capri: add dependency on OF ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Add pinctrl binding for Broadcom Capri SoCs pinctrl: Add void * to pinctrl_pin_desc pinctrl: st: Fix a typo in probe pinctrl: Fix some typos and grammar issues in the documentation pinctrl: sirf: lock IRQs when starting them pinctrl: sirf: put gpio interrupt pin into input status automatically pinctrl: sirf: use only one irq_domain for the whole device node pinctrl: single: fix infinite loop caused by bad mask pinctrl: single: fix pcs_disable with bits_per_mux pinctrl: single: fix DT bindings documentation pinctrl: as3722: Set pin to output mode for some function pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync pinctrl: sirf: fix the pins of sdmmc5 connected with TriG pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6 pinctrl: sunxi: Add Allwinner A20 clock output pin functions pinctrl/lantiq: fix typo ...
2014-01-07pinctrl: sh-pfc: r8a7791: Add I2C pinsValentine Barshak1-0/+196
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Add VIN pinsValentine Barshak1-0/+360
This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins togetherValentine Barshak1-28/+12
This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux arrayValentine Barshak1-1/+1
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart8-11/+11
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: sh: Constify pins and cfg_regs arraysLaurent Pinchart12-12/+12
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: Constify IRQ GPIOs arraysLaurent Pinchart2-3/+3
The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literalsLaurent Pinchart1-4/+5
The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Support GPIO to IRQ mapping specified IRQ resourcesLaurent Pinchart3-17/+68
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Rename sh_pfc window field to windowsLaurent Pinchart7-20/+21
There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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