aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl (follow)
AgeCommit message (Collapse)AuthorFilesLines
2015-07-01Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds7-17/+15
Pull irq fixes from Thomas Gleixner: "This contains: - a series of fixes for interrupt drivers to prevent a potential race when installing a chained interrupt handler - a fix for cpumask pointer misuse - a fix for using the wrong interrupt number from struct irq_data - removal of unused code and outdated comments - a few new helper functions which allow us to cleanup the interrupt handling code further in 4.3 I decided against doing the cleanup at the end of this merge window and rather do the preparatory steps for 4.3, so we can run the final ABI change at the end of the 4.3 merge window with less risk" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits) ARM/LPC32xx: Use irq not hwirq for __irq_set_handler_locked() genirq: Implement irq_set_handler_locked()/irq_set_chip_handler_name_locked() genirq: Introduce helper irq_desc_get_irq() genirq: Remove irq_node() genirq: Clean up outdated comments related to include/linux/irqdesc.h mn10300: Fix incorrect use of irq_data->affinity MIPS/ralink: Fix race in installing chained IRQ handler MIPS/pci: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler m68k/psc: Fix race in installing chained IRQ handler avr32/at32ap: Fix race in installing chained IRQ handler sh/intc: Fix race in installing chained IRQ handler sh/intc: Fix potential race in installing chained IRQ handler pinctrl/sun4i: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/exynos: Fix race in installing chained IRQ handler pinctrl/st: Fix race in installing chained IRQ handler pinctrl/adi2: Fix race in installing chained IRQ handler ...
2015-06-26Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds4-75/+12
Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ...
2015-06-25pinctrl/sun4i: Fix race in installing chained IRQ handlerThomas Gleixner1-3/+3
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Fan Wu <fwu@marvell.com> Cc: abdoulaye berthe <berthe.ab@gmail.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org
2015-06-25pinctrl/samsung: Fix race in installing chained IRQ handlerThomas Gleixner1-4/+4
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org
2015-06-25pinctrl/samsung: Fix race in installing chained IRQ handlerThomas Gleixner1-2/+1
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org
2015-06-25pinctrl/exynos: Fix race in installing chained IRQ handlerThomas Gleixner1-2/+2
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-gpio@vger.kernel.org
2015-06-25pinctrl/st: Fix race in installing chained IRQ handlerThomas Gleixner1-2/+2
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> Cc: Maxime Coquelin <maxime.coquelin@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Cc: kernel@stlinux.com Cc: linux-gpio@vger.kernel.org
2015-06-25pinctrl/adi2: Fix race in installing chained IRQ handlerThomas Gleixner1-2/+2
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org
2015-06-25pinctrl/mediatek: Fix race in installing chained IRQ handlerThomas Gleixner1-2/+1
Fix a race where a pending interrupt could be received and the handler called before the handler's data has been setup, by converting to irq_set_chained_handler_and_data(). Search and conversion was done with coccinelle: @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); | -irq_set_chained_handler(E1, E3); ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); @@ expression E1, E2, E3; @@ ( -if (irq_set_chained_handler(E1, E3) != 0) - BUG(); ... | -irq_set_chained_handler(E1, E3); ... ) -irq_set_handler_data(E1, E2); +irq_set_chained_handler_and_data(E1, E3, E2); Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: Axel Lin <axel.lin@ingics.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Maoguang Meng <maoguang.meng@mediatek.com> Cc: Colin Ian King <colin.king@canonical.com> Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org
2015-06-24Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds87-687/+17296
Pull pin control updates from Linus Walleij: "Here is the bulk of pin control changes for the v4.2 series: Quite a lot of new SoC subdrivers and two new main drivers this time, apart from that business as usual. Details: Core functionality: - Enable exclusive pin ownership: it is possible to flag a pin controller so that GPIO and other functions cannot use a single pin simultaneously. New drivers: - NXP LPC18xx System Control Unit pin controller - Imagination Pistachio SoC pin controller New subdrivers: - Freescale i.MX7d SoC - Intel Sunrisepoint-H PCH - Renesas PFC R8A7793 - Renesas PFC R8A7794 - Mediatek MT6397, MT8127 - SiRF Atlas 7 - Allwinner A33 - Qualcomm MSM8660 - Marvell Armada 395 - Rockchip RK3368 Cleanups: - A big cleanup of the Marvell MVEBU driver rectifying it to correspond to reality - Drop platform device probing from the SH PFC driver, we are now a DT only shop for SuperH - Drop obsolte multi-platform check for SH PFC - Various janitorial: constification, grammar etc Improvements: - The AT91 GPIO portions now supports the set_multiple() feature - Split out SPI pins on the Xilinx Zynq - Support DTs without specific function nodes in the i.MX driver" * tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: rockchip: add support for the rk3368 pinctrl: rockchip: generalize perpin driver-strength setting pinctrl: sh-pfc: r8a7794: add SDHI pin groups pinctrl: sh-pfc: r8a7794: add MMCIF pin groups pinctrl: sh-pfc: add R8A7794 PFC support pinctrl: make pinctrl_register() return proper error code pinctrl: mvebu: armada-39x: add support for Armada 395 variant pinctrl: mvebu: armada-39x: add missing SATA functions pinctrl: mvebu: armada-39x: add missing PCIe functions pinctrl: mvebu: armada-38x: add ptp functions pinctrl: mvebu: armada-38x: add ua1 functions pinctrl: mvebu: armada-38x: add nand functions pinctrl: mvebu: armada-38x: add sata functions pinctrl: mvebu: armada-xp: add dram functions pinctrl: mvebu: armada-xp: add nand rb function pinctrl: mvebu: armada-xp: add spi1 function pinctrl: mvebu: armada-39x: normalize ref clock naming pinctrl: mvebu: armada-xp: rename spi to spi0 pinctrl: mvebu: armada-370: align spi1 clock pin naming pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet ...
2015-06-17pinctrl: rockchip: add support for the rk3368Heiko Stübner1-0/+91
The rk3368 is the first ARM64 soc from Rockchip, but seems to share most peripherals with the ARM32 soc, including the pinctrl functionality. The only notable difference is - as with every Rockchip soc - that the offsets in the General Register Files moved around and a split of the pmu section of the rk3288 into pmu and pmugrf (pmu general register files) sections. The pinctrl driver of course only needs the pmugrf registers for controlling the pin settings. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-17pinctrl: rockchip: generalize perpin driver-strength settingHeiko Stübner1-13/+23
The upcoming support for the RK3368 ARM64 SoC also supports perpin drive strength settings (at different register positions), so generalize the register and offset calculation to easily support this one too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16pinctrl: sh-pfc: r8a7794: add SDHI pin groupsShinobu Uehara1-0/+153
Add SDHI0/1/2 pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: renamed SD data pins to match the driver, rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16pinctrl: sh-pfc: r8a7794: add MMCIF pin groupsShinobu Uehara1-0/+46
Add MMCIF pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-16pinctrl: sh-pfc: add R8A7794 PFC supportHisashi Nakamura5-0/+4021
Add PFC support for the R8A7794 SoC including pin groups for some on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF... Sergei: squashed together several patches, fixed the MLB_CLK typo, added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin group names, removed stray new line and fixed typos in the comments in the pinmux_config_regs[] initializer, removed the platform device ID, took into account limited number of signals in the GPIO1/5/6 controllers, added reasonable and removed unreasonable copyrights, modified the bindings document, renamed, added changelog. Changes in version 5: - resolved rejects, refreshed the patch; - added Laurent Pinchart's ACK. Changes in version 4: - reused the PORT_GP_26() macro to #define PORT_GP_28(). Changes in version 3: - removed the platform device ID; - added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the CPU_ALL_PORT() macro. Changes in version 2: - rebased the patch. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: make pinctrl_register() return proper error codeMasahiro Yamada45-95/+98
Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Ray Jui <rjui@broadcom.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add support for Armada 395 variantThomas Petazzoni1-17/+23
The Armada 39x SoC family has grown a new variant, the Armada 395, which sits between the Armada 390 and Armada 398 in terms of features. This commit adds support for this additional variant to the Armada 39x pinctrl driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add missing SATA functionsThomas Petazzoni1-0/+9
The latest version of the Armada 39x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: add missing PCIe functionsThomas Petazzoni1-0/+2
The latest version of the Armada 39x datasheet documents several new PCIe related functions on various MPP pins. This commit adds the description of these new functions to the Armada 39x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add ptp functionsThomas Petazzoni1-3/+6
The latest version of the Armada 38x datasheet documents several new PTP related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add ua1 functionsThomas Petazzoni1-6/+12
The latest version of the Armada 38x datasheet documents several new UART1 related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add nand functionsThomas Petazzoni1-2/+4
The latest version of the Armada 38x datasheet documents several new NAND related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: add sata functionsThomas Petazzoni1-2/+4
The latest version of the Armada 38x datasheet documents several new SATA related functions on various MPP pins. This commit adds the description of these new functions to the Armada 38x pinctrl driver as well as to its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add dram functionsThomas Petazzoni1-2/+5
The latest Armada XP datasheet documents several new DRAM related functions on various MPPs. This commit adds the description of these new functions in the Armada XP pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add nand rb functionThomas Petazzoni1-1/+2
The latest version of the Armada XP datasheet documents a new NAND-related MPP function on MPP48, for which this commit adds support. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: add spi1 functionThomas Petazzoni1-7/+18
The latest Armada XP datasheet documents that some of the MPP pins can be used to access the second SPI bus, labelled 'spi1'. This commit adds the corresponding pins in the pinctrl driver and its DT binding documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: normalize ref clock namingThomas Petazzoni1-4/+4
This commit normalizes the subnames of the reference clock MPP pins in the Armada 39x pinctrl driver to match with the name used on other SoCs. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: rename spi to spi0Thomas Petazzoni1-11/+11
After updating to the latest Armada XP datasheet, we discovered that there is a second SPI bus accessible from the MPP pins, called 'spi1'. In order to be consistent with other SoCs having two SPI busses, this commit renames the functions of the first SPI bus to 'spi0' instead of just 'spi'. This commit obviously breaks the DT backward compatibility for the people using the "spi" function name in their Device Tree. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-370: align spi1 clock pin namingThomas Petazzoni1-1/+1
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the 'sck' subname and not 'clk', so this commit adjusts the code and documentation accordingly. Since this commit only changes the subname, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheetThomas Petazzoni1-1/+1
For consistency with the datasheet, this commit renames the VDD function of the MPP4 pin. While this changes the DT compatibility, it is not considered to be a problem since this pin is unlikely to be used for anything but debugging purposes. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{370,xp}: normalize ethernet txclkout pinsThomas Petazzoni2-3/+3
This commit normalizes the naming of the Ethernet txclkout pin to be the same accross Marvell SoCs. It is worth mentioning that the DT binding documentation of the Armada XP was wrong for MPP12: it said the function was ge1(txd0), while it is in fact ge1(txclkout). It is however not really a fix worth sending to stable since it does not change the behavior, and the driver itself was correct. Since only the subnames are changed, DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{370,375}: normalize audio pinsThomas Petazzoni2-2/+2
This commit aligns the naming of the audio 'lrclk' pin accross Marvell SoCs. Since only the subname is changed, the DT backward compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{370,375}: normalize PCIe pinsThomas Petazzoni2-8/+8
This commit normalizes the naming of PCIe pins to use 'rstout' instead of 'rstoutn' or 'rst-out'. Since only the subnames are changed, DT compatibility is not affected. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{370,375,38x,39x,xp}: normalize TDM pinsThomas Petazzoni5-13/+13
This commit normalizes the naming of the TDM pins accross the different Marvell SoCs. Mainly it consists in: * Removing the 'n' from signal names: 'intn' becomes 'int' and 'rstn' becomes 'rst' * Renaming the main name 'tdm2c' to 'tdm' on Armada 38x. * Change the main name 'tdm-1' to 'tdm' for one of the pins of the Armada XP The last two changes affect DT compatibility, but since the TDM interface is nowhere near being supported in mainline, it should not be considered to be a serious problem at this point. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: align NAND pin namingThomas Petazzoni1-2/+2
All SoCs use "nand" to designate NAND pins, only Armada 39x is using "nd", which is not consistent. This commit fixes that by renaming the corresponding functions. It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the convention used everywhere that we don't encode the 'n' part of signal names. While this commit changes the main name of function, therefore potentially breaking the DT compatibility, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{370,375,38x,39x}: normalize dev pinsThomas Petazzoni4-15/+15
This commit modifies the definition of the Device Bus interface pins to be consistent accross SoCs. Especially, it removes the 'n' indicators that we don't encode in the subnames of pins: 'dev(wen0)' becomes 'dev(we0)' 'dev(wen1)' becomes 'dev(we1)' 'dev(oen)' becomes 'dev(oe)' etc. In addition, it fixes the Armada 375 DT binding documentation, which forgot to document the 'dev' function for MPP46, MPP57 and MPP63. Since only the subnames are changed, this commit does not affect DT compatibility. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: normalize SDIO pin namingThomas Petazzoni1-20/+20
In order to be consistent with the datasheet and some other SoCs, this commit renames the SDIO pins of the Armada 39x from "sd" to "sd0". While this changes the DT binding, this is not a problem since Armada 39x is a brand new SoC which isn't used in production yet (so now is the right time to fix such things). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: normalize SATA present functionality namingThomas Petazzoni1-12/+12
This commit makes the naming of SATA related MPP functions consistent accross SoCs by adjusting the Armada 39x definition to use "prsnt" instead of "present". Since only the subnames are changed, the DT binding is not modified at all. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{38x,39x,xp}: normalize naming of DRAM functionsThomas Petazzoni3-19/+19
This commit makes the dram functions naming (both the name and subname) consistent accross SoC, by using: dram(vttctrl) dram(deccerr) in all Marvell SoCs. Due to the change to the name, it changes the DT binding, but these functions are not used by any in-tree Device Tree file, and are very unlikely to be used by anyone. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-{375,38x,39x}: normalize naming of PTP subnamesThomas Petazzoni3-13/+13
The subnames are purely informative, but it's nicer when they match accross SoCs. This commit adjusts the Armada 375, Armada 38x and Armada 39x MPP definitions so that the subnames of the PTP pins match the ones used on Armada XP and Kirkwood. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOsThomas Petazzoni1-1/+1
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v4.1+ Fixes: ee086577abe7f ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOsThomas Petazzoni1-1/+1
The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and a second one of 27 GPIOs. However, since there is a total of 60 MPP pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-375: remove incorrect space in pin descriptionThomas Petazzoni1-1/+1
There was an incorrect space in the definition of the function of one pin in the Armada 375 pinctrl driver, which this commit fixes. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: fix functions of MPP48Thomas Petazzoni1-1/+1
There was a mistake in the definition of the functions for MPP48 on Marvell Armada XP. The second function is dev(clkout), and not tclk. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functionsThomas Petazzoni1-23/+10
The latest version of the Armada XP datasheet no longer documents the VDD cpu_pd functions, which might indicate they are not working and/or not supported. This commit ensures the pinctrl driver matches the datasheet. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-xp: remove non-existing NAND pinsThomas Petazzoni1-2/+0
After updating to a more recent version of the Armada XP datasheet, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-375: remove non-existing NAND re/we pinsThomas Petazzoni1-2/+0
After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-370: fix spi0 pin descriptionThomas Petazzoni1-2/+2
Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly named "spi0-1" instead of just "spi0". This commit fixes that. This DT binding change does not affect any of the in-tree users. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.7+ Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: mvebu: armada-38x: fix PCIe functionsThomas Petazzoni1-29/+20
A new revision of the Marvell Armada 38x hardware datasheet unveiled that the definition of some of the PCIe functions were not correct. This commit fixes the pinctrl driver accordingly. Some PCIe functions simply do not exist, some of the PCIe functions in fact were corresponding to other functions, and some PCIe functions have been added. Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: this function is in fact implemented on MPP43, instead of a PCIe function. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-06-10pinctrl: don't print unavailable function groupsLudovic Desroches1-1/+4
There is no reason to try to print groups associated to a function if get_function_groups returns an error. Moreover, it can lead to a NULL pointer dereference error. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.