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2014-05-03pinctrl: sunxi: Replace hardcoded pin defines by a macroMaxime Ripard2-1089/+729
We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directoryMaxime Ripard7-7/+12
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03pinctrl: sunxi: Drop unused structure membersMaxime Ripard1-2/+0
The ranges and nranges were never used. Remove them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03pinctrl: sunxi: Add const qualifier to the pin descriptorMaxime Ripard2-2/+2
The pins description structure were declared as const, but the of_device_id data magic was losing it silently. Make sure we have it on both sides. And now that we're using const, we can also remove the useless cast in probe. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-02pinctrl: qcom: Correct name for pin 0Andy Gross1-1/+1
Fix copy/paste error in pinctrl_pin_desc for pin 0. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-24pinctrl: mvebu: new driver for Orion platformsThomas Petazzoni3-0/+266
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handlingHeiko Stübner1-0/+40
In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: rockchip: return a complete config in pinconf_getHeiko Stübner1-2/+5
Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: sirf: switch driver to use gpiolib irqchip helpersLinus Walleij2-63/+27
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: sirf: wrap all gpio banks into one gpio_chipBarry Song1-126/+91
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: sirf: rename inlined accessorLinus Walleij1-7/+7
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23sh-pfc: r8a7791: Fix definition of MOD_SEL3Phil Edworthy1-1/+1
There is a missing 0 entry from the MOD_SEL3 table. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23sh-pfc: r8a7790: Fix definition of IPSR5Guido Piasenza1-2/+1
The extra entry in the table makes SCIFA0_B, and all peripherals after it, fail. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: qcom: Add definitions for IPQ8064Andy Gross3-0/+662
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <agross@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: single: Clear pin interrupts enabled by bootloaderTony Lindgren1-0/+13
Since we set up device wake-up interrupts as pinctrl-single interrupts, we now must use the standard request_irq and related functions to manage them. If the pin interrupts are enabled for some pins at boot, the wake-up events can show up as constantly pending at least on omaps and will hang the system unless the related device driver clears the event at the device. To fix this, let's clear the interrupt flags during init, and print out a warning so the board maintainers can update their drivers to do proper request_irq for the driver specific wake-up events. Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23pinctrl: exynos: Add driver data for Exynos3250Tomasz Figa3-0/+70
This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl/at91: Fix mask creation in at91_gpio_dbg_showAlexander Stein1-2/+1
pin_to_mask expects a bank pin number. So do not add the chip base. Without that patch cat /sys/kernel/debug/gpio looks like that: GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio: [spi32766.0] GPIOfffff200.gpio5: [gpio] set [ads7846_pendown] GPIOfffff200.gpio15: [gpio] set [ohci_vbus] GPIOfffff200.gpio21: [gpio] set [ohci_vbus] GPIOfffff200.gpio24: [gpio] set [button1] GPIOfffff200.gpio28: [gpio] clear [button2] GPIOfffff200.gpio29: [gpio] clear GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio: [sda] GPIOfffff400.gpio4: [periph A] [scl] GPIOfffff400.gpio5: [periph A] [spi32766.3] GPIOfffff400.gpio11: [periph A] [error] GPIOfffff400.gpio22: [periph A] [run] GPIOfffff400.gpio23: [periph A] GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio: [reset_pin] GPIOfffff600.gpio29: [periph A] GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio: [led1] GPIOfffff800.gpio5: [periph A] [led2] GPIOfffff800.gpio6: [periph A] [led3] GPIOfffff800.gpio7: [periph A] [led4] GPIOfffff800.gpio8: [periph A] GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio: [button3] GPIOfffffa00.gpio10: [periph A] [button4] GPIOfffffa00.gpio12: [periph A] Note that every bank despite bank 0 only shows "periph A" which are obviously used as GPIOs. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl/at91: convert driver to use gpiolib irqchipAlexander Stein2-105/+33
This converts the AT91 pin control driver to register its chained irq handler and irqchip using the helpers in the gpiolib core. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: as3722: fix handling of GPIO invert bitAndrew Bresticker1-6/+11
The AS3722_GPIO_INV bit will always be blindly overwritten by as3722_pinctrl_gpio_set_direction() and will be ignored when setting the value of the GPIO in as3722_gpio_set() since the enable_gpio_invert flag is never set. This will cause an initially inverted GPIO to toggle when requested as an output, which could be problematic if, for example, the GPIO controls a critical regulator. Instead of setting up the enable_gpio_invert flag, just leave the invert bit alone and check it before setting the GPIO value. Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: add missing kerneldocStephen Warren1-0/+4
The kerneldoc for struct tegra_pingroup didn't describe all of the fields in the struct. Add some extra kerneldoc to fix that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: print better error messagesStephen Warren1-3/+14
When an attempt is made to configure an unsupported option on a pin, print the DT property name of that option, so it's easier to debug what the problem is. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: reduce size of data table fieldsStephen Warren1-2/+2
The range of npins and function ID values is small enough to fit into a u8. Use this type rather than unsigned to shrink the pinmux data tables. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove fsafe from data tablesStephen Warren6-783/+772
The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove redundant data table fieldsStephen Warren6-197/+132
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add mux data for IIC(B) coresWolfram Sang1-2/+116
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pfc: r8a7790: add i2c0 muxingWolfram Sang1-1/+21
Add the muxing for the last missing i2c rcar core. Fix the sorting for SH_PFC_PIN_NAMED while we are here. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: pinctrl-imx: Print the mux_mode field in hex formatFabio Estevam1-1/+1
With debug enabled we get better readability dumps of the mux_mode register if we use hexadecimal format instead: imx6sl-pinctrl 20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add Audio pin supportKuninori Morimoto1-0/+61
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22sh-pfc: r8a7791: Add SSI pin supportKuninori Morimoto1-0/+314
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl/TB10x: Fix signedness bugChristian Ruppert1-2/+1
In the TB10x pin database, a port index of -1 is used to indicate unmuxed GPIO pin groups. This bug fixes a 'cast to unsigned' bug of this value. Thanks to Dan Carpenter for highlighting this. CC: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: fix typo in module author addressAntoine Ténart1-1/+1
According to the MODULE_AUTHOR() comments, the author name should be "Name <email>" or just "Name". Add the missing '>'. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: allows not to define the get_group_pins operationAntoine Ténart2-17/+23
When using a group only pinctrl driver, which does not have any information on the pins it is useless to define a get_group_pins always returning an empty list of pins. When not using get_group_pin[1], a driver must implement it so pins = NULL and num_pins = 0. This patch makes it the default behaviour if not defined in the pinctrl driver when used in pinmux enable and disable funtions and in pinctrl_groups_show. It also adds a check in pinctrl_get_group_pins and return -EINVAL if not defined. This function is called in the gpiolib when adding when pingroup range. It cannot be used if no group is defined, so this seams reasonable. [1] get_group_pin(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins); Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: add reset control supportBoris BREZILLON1-2/+14
The A31 SoC define a reset line for the R_PIO block which needs to be deasserted. Try to retrieve a reset control and deassert if one was found. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: define A31 R_PIO pin functionsBoris BREZILLON2-0/+75
The A31 SoC provides both PL and PM pio bank through the R_PIO block. These pins all support gpio function and can bbe assigned to system peripherals (like TWI, P2WI, JTAG, ...) Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: support multiple pin controllerBoris BREZILLON2-16/+15
Add support for multiple pin controller instances. First remove the static definition of the sunxi gpio chip struct and fill the dynamically struct instead. Then define a new pin_base field in the sunxi_pinctrl_desc which will be used to specify the gpiochip base pin. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: add PL and PM pin definitionsBoris BREZILLON1-0/+68
Define PL and PM pin macros. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: disable clk when failing to probe pin controllerBoris BREZILLON1-2/+4
Disable the clk when failing to probe the pin controller device. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sunxi: check clk_prepare_enable return valueBoris BREZILLON1-1/+3
Check the clk_prepare_enable return value to avoid false positive probe. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: st: Use ARRAY_SIZE for STiH415 dataMaxime COQUELIN1-2/+2
This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416 for setting ninput_delays and noutput_delays fields. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: st: Use const qualifier when requiredMaxime COQUELIN1-12/+12
This patch adds const qualifier where applicable. Reported-by: Joe Perches <joe@perches.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: lantiq: Fix header file include guardAxel Lin1-0/+1
Define __PINCTRL_LANTIQ_H to prevent multiple inclusion. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: adi2: Statize adi_gpio_irq_domain_opsAxel Lin1-1/+1
It's only referenced in this file, make it static. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groupsLaurent Pinchart1-10/+27
The DU parallel interface ODDF signal is optional, move it out of the HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are independent, split them to two different groups. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: msm8x74: make Kconfig dependency more strictUwe Kleine-König1-1/+1
This driver is only useful on MSM8x74, so let the driver depend on ARCH_QCOM but allow compile coverage testing. The main benefit is that the driver isn't available to be selected for machines that don't have the matching hardware. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: msm: Add definitions for the APQ8064 platformBjorn Andersson3-0/+575
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm APQ8064 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: msm: Make number of functions variableBjorn Andersson3-4/+6
The various pins may have different number of functions defined, so make this number definable per pin instead of just increasing it to the largest one for all of the platforms. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: st: use gpiolib irqchip helpersLinus Walleij2-81/+20
This lets the gpiolib core handle the irqchip set-up and chained IRQ on the primary (behind the mux) IRQ chip in the st pinctrl driver. Default irq type is set to level low at irqchip add time. The v1 was sent by Linus (https://lkml.org/lkml/2014/4/4/287). Two changes were necessary to make it to work properly on STiH416: 1 - dev reference was not passed to the gpio_chip struct, causing a panic. 2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as default type, which caused lot of warnings at init time. I choose IRQ_TYPE_LEVEL_LOW as default. Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
2014-04-22pinctrl: st: switch IRQ locking to resource callbacksLinus Walleij1-9/+7
In the mass-conversion to the new irqchip callbacks, this in-transit IRQ support was missed. Fix it. Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Cc: Maxime COQUELIN <maxime.coquelin@st.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14pinctrl: Rename Broadcom Capri pinctrl driverSherman Yin4-1459/+1466
To be consistent with other Broadcom drivers, the Broadcom Capri pinctrl driver and its related CONFIG option are renamed to bcm281xx. Devicetree compatible string and binding documentation use "brcm,bcm11351-pinctrl" to match the machine binding here: Documentation/devicetree/bindings/arm/bcm/bcm11351.txt This driver supports pinctrl on BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-14pinctrl: msm: Correct interrupt code for TLMM v2Bjorn Andersson2-1/+6
Acking interrupts are done differently between on v2 and v3, so add an extra attribute to the pingroup struct to let the platform definitions control this. Also make sure to start dual edge detection by detecting the rising edge. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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