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2021-07-27pinctrl: renesas: Fix pin control matching on R-Car H3e-2GGeert Uytterhoeven2-19/+14
As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
2021-07-23pinctrl: imx8ulp: Initialize pin_regFabio Estevam1-0/+4
The initialization of pin_reg is missing, causing the following build warning: drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized] Initialize pin_reg the same way as it is done on vf610 and imx7ulp to fix the problem. Fixes: 16b343e8e0ef ("pinctrl: imx8ulp: Add pinctrl driver support") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210723203242.88845-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom/pinctrl-spmi-gpio: Add compatible for pmic-gpio on SA8155p-adpBhupesh Sharma1-0/+1
SA8155p-adp PMIC (PMM8155AU) exposes 10 GPIOs. Add support for the same in the pinctrl driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210629123407.82561-5-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom/pinctrl-spmi-gpio: Arrange compatibles alphabeticallyBhupesh Sharma1-17/+17
Arrange the compatibles inside qcom pinctrl-spmi gpio driver alphabetically. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210629123407.82561-4-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: mediatek: fix platform_no_drv_owner.cocci warningskernel test robot1-1/+0
drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") CC: Fabien Parent <fparent@baylibre.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: imx8ulp: Add pinctrl driver supportAnson Huang3-0/+282
Add i.MX8ULP pinctrl driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210607061041.2654568-2-ping.bai@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: armada-37xx: Correct PWM pins definitionsMarek Behún1-8/+8
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Fixes: b835d6953009 ("pinctrl: armada-37xx: swap polarity on LED group") Signed-off-by: Marek Behún <kabel@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: bcm2835: Replace BUG with BUG_ONJason Wang1-2/+1
The if condition followed by BUG can be replaced to BUG_ON which is more compact and formal in linux source. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom: Add MDM9607 pinctrl driverKonrad Dybcio3-0/+1096
Add a pinctrl driver to allow for managing SoC pins. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210624191743.617073-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: mediatek: Fix fallback behavior for bias_set_comboHsin-Yi Wang1-5/+3
Some pin doesn't support PUPD register, if it fails and fallbacks with bias_set_combo case, it will call mtk_pinconf_bias_set_pupd_r1_r0() to modify the PUPD pin again. Since the general bias set are either PU/PD or PULLSEL/PULLEN, try bias_set or bias_set_rev1 for the other fallback case. If the pin doesn't support neither PU/PD nor PULLSEL/PULLEN, it will return -ENOTSUPP. Fixes: 81bd1579b43e ("pinctrl: mediatek: Fix fallback call path") Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210701080955.2660294-1-hsinyi@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom: fix GPIOLIB dependenciesArnd Bergmann1-32/+31
Enabling the PINCTRL_SM8350 symbol without GPIOLIB or SCM causes a build failure: WARNING: unmet direct dependencies detected for PINCTRL_MSM Depends on [m]: PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && (QCOM_SCM [=m] || !QCOM_SCM [=m]) Selected by [y]: - PINCTRL_SM8350 [=y] && PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && OF [=y] aarch64-linux-ld: drivers/pinctrl/qcom/pinctrl-msm.o: in function `msm_gpio_irq_set_type': pinctrl-msm.c:(.text.msm_gpio_irq_set_type+0x1c8): undefined reference to `qcom_scm_io_readl' The main problem here is the 'select PINCTRL_MSM', which needs to be a 'depends on' as it is for all the other front-ends. As the GPIOLIB dependency is now implied by that, symbol, remove the duplicate dependencies in the process. Fixes: d5d348a3271f ("pinctrl: qcom: Add SM8350 pinctrl driver") Fixes: 376f9e34c10f ("drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIB") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210723091400.1669716-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-13pinctrl: renesas: r8a77995: Add bias pinconf supportGeert Uytterhoeven3-9/+316
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: rcar: Avoid changing PUDn when disabling biasGeert Uytterhoeven1-7/+7
When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be
2021-07-01Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlLinus Torvalds62-283/+6315
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.14 kernel. Not so much going on. No core changes, just drivers. The most interesting would be that MIPS Ralink is migrating to pin control and we have some bindings but not yet code for the Apple M1 pin controller. New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well" * tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits) pinctrl: ralink: rt305x: add missing include pinctrl: stm32: check for IRQ MUX validity during alloc() pinctrl: zynqmp: some code cleanups drivers: qcom: pinctrl: Add pinctrl driver for sm6125 dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios pinctrl: mcp23s08: Add optional reset GPIO pinctrl: mediatek: fix mode encoding pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() pinctrl: bcm: Constify static pinmux_ops pinctrl: bcm: Constify static pinctrl_ops pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file pinctrl: ralink: move ralink architecture pinmux header into the driver pinctrl: single: config: enable the pin's input pinctrl: mtk: Fix mt8365 Kconfig dependency pinctrl: mcp23s08: fix race condition in irq handler ...
2021-06-30pinctrl: ralink: rt305x: add missing includeSergio Paracuellos1-0/+1
Header 'rt305x.h' is ralink architecture dependent file where other general definitions which are in 'ralink_regs.h' are being used. This 'rt305x.h' is only being included in two different files: 'rt305x.c' and 'pinctrl-rt305x.c'. When file 'pinctrl-rt305x.c' is being compiled definitions in 'ralink_regs.h' are need to build it properly. Hence, add missing include 'ralink_regs.h' in 'pinctrl-rt305x.c' source to avoid compilation problems. Fixes: 3a1b0ca5a83b ("pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210629143407.14703-1-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26pinctrl: stm32: check for IRQ MUX validity during alloc()Fabien Dessenne1-39/+40
Considering the following irq_domain_ops call chain: - .alloc() is called when a clients calls platform_get_irq() or gpiod_to_irq() - .activate() is called next, when the clients calls request_threaded_irq() Check for the IRQ MUX conflict during the first stage (alloc instead of activate). This avoids to provide the client with an IRQ that can't be used. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26pinctrl: zynqmp: some code cleanupsSai Krishna Potthuri2-30/+22
Some minor code cleanups and updates which includes - Mention module name under help in Kconfig. - Remove extra lines and duplicate Pin range checks. - Replace 'return ret' with 'return 0' in success path. - Copyright year update. - use devm_pinctrl_register() instead pinctrl_register() in probe. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18pinctrl: stm32: fix the reported number of GPIO lines per bankFabien Dessenne1-2/+7
Each GPIO bank supports a variable number of lines which is usually 16, but is less in some cases : this is specified by the last argument of the "gpio-ranges" bank node property. Report to the framework, the actual number of lines, so the libgpiod gpioinfo command lists the actually existing GPIO lines. Fixes: 1dc9d289154b ("pinctrl: stm32: add possibility to use gpio-ranges to declare bank range") Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210617144629.2557693-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18drivers: qcom: pinctrl: Add pinctrl driver for sm6125Martin Botka3-0/+1287
This patch adds pinctrl driver for sm6125. Signed-off-by: Martin Botka <martin.botka@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18pinctrl: microchip-sgpio: Put fwnode in error case during ->probe()Andy Shevchenko1-1/+3
device_for_each_child_node() bumps a reference counting of a returned variable. We have to balance it whenever we return to the caller. Fixes: 7e5ea974e61c ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") Cc: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210606191940.29312-1-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-12Merge tag 'renesas-pinctrl-for-v5.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into develLinus Walleij6-80/+1844
pinctrl: renesas: Updates for v5.14 (take two) - Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
2021-06-12pinctrl: mcp23s08: Add optional reset GPIOAndreas Kaessens2-0/+4
The MCP23x port expander RESET# line can be connected to a host GPIO. The optional reset-gpio must be set to LOW if the reset is asserted at probing time. On page 5 in the datasheet [0] the "Device Active After Reset high" time is specified at 0 µs. Therefore no waiting is needed after the reset transition. [0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf Signed-off-by: Andreas Kaessens <akaessens@gmail.com> Signed-off-by: Darian Biastoch <d.biastoch@gmail.com> Link: https://lore.kernel.org/r/20210610132438.3085841-1-akaessens@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09Merge tag 'intel-pinctrl-v5.14-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into develLinus Walleij1-0/+1
intel-pinctrl for v5.14-1 * Enabling pin controller on Intel Alder Lake-M The following is an automated git shortlog grouped by driver: tigerlake: - Add Alder Lake-M ACPI ID
2021-06-09pinctrl: mediatek: fix mode encodingMatthias Brugger1-2/+2
Pin modes are encoded in the SoC data structure. Use that value to set IES SMT. Cc: Fabien Parent <fparent@baylibre.com> Cc: Sean Wang <sean.wang@kernel.org> Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com> Cc: linux-mediatek@lists.infradead.org Fixes: 696beef77521 ("pinctrl: mediatek: move bit assignment") Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com> Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()Zou Wei1-1/+1
Add the missing unlock before return from function mcp23s08_irq() in the error handling case. v1-->v2: remove the "return IRQ_HANDLED" line Fixes: 897120d41e7a ("pinctrl: mcp23s08: fix race condition in irq handler") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1623134048-56051-1-git-send-email-zou_wei@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09pinctrl: qcom: Make it possible to select SC8180x TLMMBjorn Andersson1-1/+1
It's currently not possible to select the SC8180x TLMM driver, due to it selecting PINCTRL_MSM, rather than depending on the same. Fix this. Fixes: 97423113ec4b ("pinctrl: qcom: Add sc8180x TLMM driver") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210608180702.2064253-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09pinctrl: bcm: Constify static pinmux_opsRikard Falkeborn7-7/+7
These are only assigned, either directly or via the bcm63xx_pinctrl_soc struct, to the pmxops field in the pinctrl_desc struct and never modified, so make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210605185908.39982-3-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09pinctrl: bcm: Constify static pinctrl_opsRikard Falkeborn7-7/+7
These are only assigned, either directly or via the bcm63xx_pinctrl_soc struct, to the pctlops field in the pinctrl_desc struct and never modified, so make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210605185908.39982-2-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' fileSergio Paracuellos3-0/+66
Move all related code for SoC RT288X into a new driver located in 'pinctrl-rt288x.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-7-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' fileSergio Paracuellos3-0/+396
Move all related code for SoC MT7620 into a new driver located in 'pinctrl-mt7620.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-6-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' fileSergio Paracuellos3-0/+142
Move all related code for SoC RT305X into a new driver located in 'pinctrl-rt305x.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-5-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' fileSergio Paracuellos3-0/+113
Move all related code for SoC RT3883 into a new driver located in 'pinctrl-rt3883.c' source file Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-4-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' fileSergio Paracuellos3-0/+123
Move all related code for SoC MT7621 into a new driver located in 'pinctrl-mt7621.c' source file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-3-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: move ralink architecture pinmux header into the driverSergio Paracuellos2-25/+58
Ralink architecture is making use of the header located in 'arch/mips/include/asm/mach-ralink/pinmux.h' to stablish the mechanisms to make derived SoCs to set its pin functions and groups. In order to move all architecture pinmux into a more accurate place which is 'drivers/pinctrl/ralink' we have to first of all move this file also there with a small modification which creates 'rt2880_pinmux_init' function to allow SoCs pinctrl drivers to pass its configuration to the common code located in 'pinctrl-rt2880.c' file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604115159.8834-2-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: ralink: rt2880: avoid to error in calls is pin is already enabledSergio Paracuellos1-1/+1
In 'rt2880_pmx_group_enable' driver is printing an error and returning -EBUSY if a pin has been already enabled. This begets anoying messages in the caller when this happens like the following: rt2880-pinmux pinctrl: pcie is already enabled mt7621-pci 1e140000.pcie: Error applying setting, reverse things back To avoid this just print the already enabled message in the pinctrl driver and return 0 instead to not confuse the user with a real bad problem. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210604055337.20407-1-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: single: config: enable the pin's inputDario Binacchi1-0/+3
It enables / disables the input buffer. As explained in the description of 'enum pin_config_param' this does not affect the pin's ability to drive output. Signed-off-by: Dario Binacchi <dariobin@libero.it> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210602150420.18202-1-dariobin@libero.it Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: mtk: Fix mt8365 Kconfig dependencyLinus Walleij1-0/+1
This SoC needs to select PINCTRL_MTK or we can end up in kernel compiles that miss some symbols. Cc: Fabien Parent <fparent@baylibre.com> Reported-by: kernel test robot <lkp@intel.com> Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: mcp23s08: fix race condition in irq handlerRadim Pavlik1-5/+5
Checking value of MCP_INTF in mcp23s08_irq suggests that the handler may be called even when there is no interrupt pending. But the actual interrupt could happened between reading MCP_INTF and MCP_GPIO. In this situation we got nothing from MCP_INTF, but the event gets acknowledged on the expander by reading MCP_GPIO. This leads to losing events. Fix the problem by not reading any register until we see something in MCP_INTF. The error was reproduced and fix tested on MCP23017. Signed-off-by: Radim Pavlik <radim.pavlik@tbs-biometrics.com> Link: https://lore.kernel.org/r/AM7PR06MB6769E1183F68DEBB252F665ABA3E9@AM7PR06MB6769.eurprd06.prod.outlook.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-07pinctrl: qcom: Fix duplication in gpio_groupsManivannan Sadhasivam1-9/+9
"gpio52" and "gpio53" are duplicated in gpio_groups, fix them! Fixes: ac43c44a7a37 ("pinctrl: qcom: Add SDX55 pincontrol driver") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210526082857.174682-1-manivannan.sadhasivam@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-31pinctrl: renesas: r8a77980: Add bias pinconf supportGeert Uytterhoeven1-6/+203
Implement support for pull-up and pull-down handling for the R-Car V3H SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/448f47ccd89d9bc8621c7fda8c81508deb05cb82.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a77970: Add bias pinconf supportGeert Uytterhoeven1-6/+169
Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR) and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7794: Add bias pinconf supportGeert Uytterhoeven1-9/+351
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car E2 and RZ/G1E SoCs, using the common R-Car bias handling. Note that on RZ/G1E, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/f78da2ba937ce98ae9196f4ee54149a5214fd545.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7792: Add bias pinconf supportGeert Uytterhoeven1-12/+521
Implement support for pull-up (most pins) and pull-down (EDBGREQ) handling for the R-Car V2H SoC, using the common R-Car bias handling. Note that the R-Car V2H Hardware User's Manual Rev. 1.00 says that the LSI Pin Pull-Up Control Register 11 (PUPR11) controls pull-ups for the {SCK,WS,SDATA}[01] pins. These are assumed to be typos, as R-Car V2H has only Serial Sound Interface channels 3 and 4. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/48d2abdd63ee43ed99cb32ed4a5f4d76ba563162.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a7790: Add bias pinconf supportGeert Uytterhoeven1-7/+294
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias handling. Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be
2021-05-31pinctrl: renesas: r8a77470: Add bias pinconf supportGeert Uytterhoeven1-40/+306
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for the RZ/G1C SoC, using the common R-Car bias handling. Note that on RZ/G1C, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/18c8ebf9fa9e239253a723857e9dffeec775db7e.1619785375.git.geert+renesas@glider.be
2021-05-28Merge tag 'renesas-pinctrl-for-v5.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into develLinus Walleij5-56/+56
pinctrl: renesas: Updates for v5.14 - Minor fixes and improvements.
2021-05-28pinctrl: mediatek: move bit assignmentLinus Walleij1-1/+1
The bit needs offset to be defined which happens some lines below. Looks like a bug. The kernel test robot complains: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:137:12: warning: variable 'offset' is uninitialized when used here [-Wuninitialized] bit = BIT(offset & pctl->devdata->mode_mask); ^~~~~~ Fix it up by reverting to what was done before. Cc: Fabien Parent <fparent@baylibre.com> Cc: Sean Wang <sean.wang@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com> Cc: linux-mediatek@lists.infradead.org Fixes: 9f940d8ecf92 ("pinctrl: mediatek: don't hardcode mode encoding in common code") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28pinctrl: bcm2835: Accept fewer than expected IRQsPhil Elwell1-2/+6
The downstream .dts files only request two GPIO IRQs. Truncate the array of parent IRQs when irq_of_parse_and_map returns 0. Signed-off-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210521090158.26932-1-iivanov@suse.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28pinctrl: Fix kernel-docYang Li1-1/+1
Fix function name in pinctrl-single.c kernel-doc comment to remove a warning found by clang_w1. drivers/pinctrl/pinctrl-single.c:1523: warning: expecting prototype for pcs_irq_handle(). Prototype was for pcs_irq_chain_handler() instead. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1621998464-10918-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-05-28pinctrl: pinctrl-aspeed-g6: Add sgpio pinctrl settingsSteven Lee2-4/+29
AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. Current pinctrl driver only define the first sgpio master and slave interfaces. The second SGPIO master and slave interfaces should be added in pinctrl driver as well. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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