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2022-07-05pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC supportLUU HOAI5-0/+2479
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0) SoC, including bias, drive strength and voltage control. This patch was created based on the Rev.0.51 datasheet. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.] Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: Add PORT_GP_CFG_13 macrosKuninori Morimoto1-2/+6
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the r8a779g0 subdriver. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05pinctrl: renesas: Add RZ/V2M pin and gpio controller driverPhil Edworthy3-0/+1133
Add support for pin and gpio controller driver for RZ/V2M SoC. Based on the RZ/G2L driver. Note that the DETDO and DETMS dedicated pins are currently not documented in the HW manual as to which pin group they are in. HW team has since said that the output level of 1.8V I/O group 4 (for MD0-7, and debugger) is the same as the 1.8V I/O group 3. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-30pinctrl: intel: Add Intel Meteor Lake pin controller supportAndy Shevchenko3-0/+426
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-30pinctrl: axp209: Support the AXP221/AXP223/AXP809 variantSamuel Holland1-3/+11
These PMICs each have 2 GPIOs with the same register layout as AXP813, but without an ADC function. They all fall back to the AXP221 compatible string, so only that one needs to be listed in the driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20220621034224.38995-4-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-30pinctrl: qcom: sc7280: Fix compile bugSrinivasa Rao Mandadapu2-5/+1
Fix the compilation error, caused by updating constant variable. Hence remove redundant constant variable, which is no more useful as per new design. The issue is due to some unstaged changes. Fix it up. Fixes: 36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-29pinctrl: renesas: r8a779f0: Remove unused POC2Geert Uytterhoeven1-2/+0
The POWER Condition Control Register 2 (POC2) is unused, and the documentation does not define any valid bits. Remove it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d8a9ea39b49d24e39f4da3f00b64bce34016887d.1655301529.git.geert+renesas@glider.be
2022-06-28pinctrl: stm32: fix optional IRQ support to gpiosFabien Dessenne1-8/+12
To act as an interrupt controller, a gpio bank relies on the "interrupt-parent" of the pin controller. When this optional "interrupt-parent" misses, do not create any IRQ domain. This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when the interrupt-parent = <exti> property is not declared in the Device Tree. Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios") Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: samsung: do not use bindings header with constantsKrzysztof Kozlowski4-7/+14
The Samsung SoC pin controller driver uses only three defines from the bindings header with pin configuration register values, which proves the point that this header is not a proper bindings-type abstraction layer with IDs. Define the needed register values directly in the driver and stop using the bindings header. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220605160508.134075-8-krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20220624081022.32384-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: imx: Add the zero base flag for imx93Jacky Bai1-0/+1
On i.MX93, the pin mux reg offset is from 0x0, so need to add the 'ZERO_OFFSET_VALID' flag to make sure the pin at mux offset 0 can be found. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Link: https://lore.kernel.org/r/20220613031854.1571357-1-ping.bai@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: aspeed: Fix typo in commentXiang wangx1-1/+1
Delete the redundant word 'and'. Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com> Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Link: https://lore.kernel.org/r/20220618130854.12321-1-wangxiang@cdjrlc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: ingenic: Convert to immutable irq chipAidan MacDonald1-14/+27
Update the driver to use an immutable IRQ chip to fix this warning: "not an immutable chip, please consider fixing it!" Preserve per-chip labels by adding an ->irq_print_chip() callback. Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: ingenic: Use irqd_to_hwirq()Aidan MacDonald1-10/+13
Instead of accessing ->hwirq directly, use irqd_to_hwirq(). Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220622185010.2022515-2-aidanmacdonald.0x0@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: pinctrl-zynqmp: Fix kernel-doc warningSai Krishna Potthuri1-0/+2
Fix the below kernel-doc warning by adding the description for return value. "warning: No description found for return value of 'zynqmp_pmux_get_function_groups'". Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1655462819-28801-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedanceSai Krishna Potthuri1-0/+9
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. As part of the output-enable configuration, ZynqMP pinctrl driver takes care of removing the pins from tri-state. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1655462819-28801-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-28pinctrl: ocelot: allow building as a moduleClément Léger2-2/+4
Set PINCTRL_OCELOT config option as a tristate and add MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate information. Moreover, switch from builtin_platform_driver() to module_platform_driver(). Signed-off-by: Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-27pinctrl: sunxi: sunxi_pconf_set: use correct offsetAndrei Lalaev1-0/+2
Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO). Previous implementation used absolute pin numbering and it was incorrect for R_PIO pinctrl. It's necessary to take into account the base pin number. Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set") Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-27pinctrl: qcom: sc7280: Fix compile bugLinus Walleij1-1/+2
The idea was right but the code was breaking in next. I assume some unstaged commit was involed. Fix it up. Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Cc: Stephen Boyd <swboyd@chromium.org> Fixes: 36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-27Merge tag 'renesas-pinctrl-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into develLinus Walleij1-0/+2
pinctrl: renesas: Updates for v5.20 - Fix reporting of input disabled pins on RZ/G2L.
2022-06-27pinctrl: mediatek: mt8192: Fix compile warningsLinus Walleij1-9/+9
After applying patches I get these warnings: drivers/pinctrl/mediatek/pinctrl-mt8192.c:1302:56: warning: "/*" within comment [-Wcomment] drivers/pinctrl/mediatek/pinctrl-mt8192.c:1362:56: warning: "/*" within comment [-Wcomment] Something is wrong with the missing end-slashes. Add them. Cc: Guodong Liu <guodong.liu@mediatek.com> Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: mediatek: fix the pinconf definition of some GPIO pinsGuodong Liu1-60/+0
Remove pin definitions that do not support the R0 & R1 pinconfig property. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-6-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: mediatek: dropping original advanced drive configuration functionGuodong Liu1-2/+0
Function bias_combo getter/setters already handle all cases advanced drive configuration, include drive for I2C related pins. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-5-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: mediatek: add rsel setting on mt8192Guodong Liu1-0/+136
1. I2C pins's resistance value can be controlled by rsel register. This patch provides rsel (resistance selection) setting on mt8192. 2. Also add the missing pull type array for mt8192 to document the pull type of each pin and prevent invalid pull type settings. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-4-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: mediatek: add drive for I2C related pins on mt8192Guodong Liu1-70/+26
This patch provides the advanced drive raw data setting version for I2C used pins on mt8192. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-3-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: mediatek: add generic driving setup property on mt8192Guodong Liu1-2/+2
1. The dt-binding expects that drive-strength arguments be passed in mA, but the driver was expecting raw values. And that this commit changes the driver so that it is aligned with the binding. 2. This commit provides generic driving setup, which support 2/4/6/8/10/12/14/16mA driving, original driver just set raw data setup setting when use drive-strength property. Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-2-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: bcm2835: Make the irqchip immutableStefan Wahren1-3/+8
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. The bcm2835 pinctrl is also affected by this warning. Fix this by making the irqchip in the bcm2835 pinctrl driver immutable. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220614202831.236341-3-stefan.wahren@i2se.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: bcm2835: drop irq_enable/disable callbacksStefan Wahren1-6/+4
The commit b8a19382ac62 ("pinctrl: bcm2835: Fix support for threaded level triggered IRQs") assigned the irq_mask/unmask callbacks with the already existing functions for irq_enable/disable. The wasn't completely the right way (tm) to fix the issue, because these callbacks shouldn't be identical. So fix this by rename the functions to represent their intension and drop the unnecessary irq_enable/disable assigment. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220614202831.236341-2-stefan.wahren@i2se.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxedNikita Travkin1-2/+2
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the function was never assigned to the pingroup (even though the function exists already). Add this mode to the related pins. Fixes: 5373a2c5abb6 ("pinctrl: qcom: Add msm8916 pinctrl driver") Signed-off-by: Nikita Travkin <nikita@trvn.ru> Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ru Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-26pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targetsSrinivasa Rao Mandadapu2-1/+2
Update lpass lpi pin control driver, with clock optional check for ADSP disabled platforms. This check required for distingushing ADSP based platforms and ADSP bypass platforms. In case of ADSP enabled platforms, where audio is routed through ADSP macro and decodec GDSC Switches are triggered as clocks by pinctrl driver and ADSP firmware controls them. So It's mandatory to enable them in ADSP based solutions. In case of ADSP bypass platforms clock voting is optional as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1654921357-16400-3-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-20pinctrl: intel: Drop no more used members of struct intel_pingroupAndy Shevchenko1-9/+0
There are no more used members in the struct intel_pingroup, drop them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: intel: Switch to to embedded struct pingroupAndy Shevchenko1-7/+7
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: merrifield: Switch to to embedded struct pingroupAndy Shevchenko1-7/+7
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: lynxpoint: Switch to to embedded struct pingroupAndy Shevchenko1-5/+5
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: cherryview: Switch to to embedded struct pingroupAndy Shevchenko1-8/+8
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: baytrail: Switch to to embedded struct pingroupAndy Shevchenko1-9/+9
Since struct intel_pingroup got a new member, switch the driver to use it. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-20pinctrl: intel: Embed struct pingroup into struct intel_pingroupAndy Shevchenko1-8/+8
Add a new member to the struct intel_pingroup to cover generic pin control group parameters. The idea is to convert all users (one-by-one) to it and drop old members later on. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-06-15pinctrl: nomadik: Fix refcount leak in nmk_pinctrl_dt_subnode_to_mapMiaoqian Lin1-1/+3
of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak." Fixes: c2f6d059abfc ("pinctrl: nomadik: refactor DT parser to take two paths") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220607111602.57355-1-linmq006@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15Merge branch 'ib-v5.20-amd-pinctrl' into develLinus Walleij2-44/+1435
2022-06-15pinctrl: sunxi: Remove reset controller consumersSamuel Holland8-53/+2
None of the sunxi pin controllers have a module reset line. All of the SoC documentation, where available, agrees. The bits that would be used for the PIO reset (i.e. matching the order of the clock gate bits) are always reserved, both in the CCU and in the PRCM. And experiments on several SoCs, including the A33, confirm that those reserved bits indeed have no effect. Let's remove this superfluous code and dependency, and also remove the include statement that was copied to the other r_pio drivers. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220531053623.43851-2-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: amd: Implement pinmux functionalityBasavaraj Natikar2-1/+1403
Provide pinmux functionality by implementing pinmux_ops. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-7-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: amd: Add amd_get_iomux_res functionBasavaraj Natikar2-0/+26
Presently there is no way to change pinmux configuration run time. Hence add a function to get IOMUX resource which can be used to configure IOMUX GPIO pins run time. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-6-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: amd: Define and use AMD_PINS macroBasavaraj Natikar1-14/+7
AMD pingroup can be extended to support multi-function pins. Hence define and use a macro "AMD_PINS" to represent larger number of pins. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-5-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: amd: Use PINCTRL_PINGROUP to manage pingroupsBasavaraj Natikar1-30/+6
AMD pingroup can be extended to support multi-function pins. Hence use PINCTRL_PINGROUP to manage and represent larger number of pingroups inline. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-4-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: amd: Remove amd_pingroup and use pingroupBasavaraj Natikar1-8/+2
Remove 'struct amd_pingroup' and instead use 'struct pingroup'. Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-3-Basavaraj.Natikar@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: sunxi: a83t: Fix NAND function name for some pinsSamuel Holland1-5/+5
The other NAND pins on Port C use the "nand0" function name. "nand0" also matches all of the other Allwinner SoCs. Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support") Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-15pinctrl: aspeed: Fix potential NULL dereference in aspeed_pinmux_set_mux()Haowen Bai1-2/+2
pdesc could be null but still dereference pdesc->name and it will lead to a null pointer access. So we move a null check before dereference. Signed-off-by: Haowen Bai <baihaowen@meizu.com> Link: https://lore.kernel.org/r/1650508019-22554-1-git-send-email-baihaowen@meizu.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-10pinctrl: devicetree: Delete usage of driver_deferred_probe_check_state()Saravana Kannan1-1/+1
Now that fw_devlink=on by default and fw_devlink supports "pinctrl-[0-8]" property, the execution will never get to the point where driver_deferred_probe_check_state() is called before the supplier has probed successfully or before deferred probe timeout has expired. So, delete the call and replace it with -ENODEV. Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Saravana Kannan <saravanak@google.com> Link: https://lore.kernel.org/r/20220601070707.3946847-3-saravanak@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULEThomas Gleixner4-56/+4
Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111-1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 2)Thomas Gleixner5-54/+8
Based on the normalized pattern: this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <allison@lohutok.net> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-06pinctrl: renesas: rzg2l: Return -EINVAL for pins which have input disabledLad Prabhakar1-0/+2
Pin status reported by pinconf-pins file always reported pin status as "input enabled" even for pins which had input disabled. Fix this by returning -EINVAL for the pins which have input disabled. Fixes: c4c4637eb57f2 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Reported-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220511094057.3151-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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