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If a driver does not set interrupt triggering type when it calls
request_irq(), it means use the pin as the hardware/firmware has
configured it. There are some drivers doing this. One example is
drivers/input/serio/i8042.c that requests the interrupt like:
error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
"i8042", i8042_platform_device);
It assumes the interrupt is already properly configured. This is true in
case of interrupts connected to the IO-APIC. However, some Intel
Braswell/Cherryview based machines use a GPIO here instead for the internal
keyboard controller.
This is a problem because even if the pin/interrupt is properly configured,
the irqchip ->irq_set_type() will never be called as the triggering flags
are 0. Because of that we do not have correct interrupt flow handler set
for the interrupt.
Fix this by adding a custom ->irq_startup() that checks if the interrupt
has no triggering type set and in that case read the type directly from the
hardware and install correct flow handler along with the mapping.
Reported-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reported-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add a driver for the pin controller present on the IMG Pistachio SoC.
This driver provides pinmux and pinconfig operations as well as GPIO
and IRQ chips for the GPIO banks.
Changes from v4:
- Switched to using gpiochip_add_pin_range().
- Fixed up Kconfig entry.
Changes from v3:
- Addressed review comments from Ezequiel.
Changes from v2:
- Removed module stuff which would be compiled out.
Changes from v1:
- Addressed review comments from Linus.
- Changed compatible string to "img,pistachio-system-pinctrl".
- Look for GPIO sub-nodes by name.
- A couple of bug fixes.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based
on the pin number. Create a common helper function that both
functions can use that also handles the case where no pin number is
found in the pins array.
This also fixes a small bug in pconf_get_pin where pconf_get_i2c0
would use the pins array index rather than the pin number.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic ARM
multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set,
and the check can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Regarding pin control, r8a7791 and r8a7793 are identical, so it is
sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The last serial port is called "SCIFB", not "SCIFAB".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller
Hub). It has slightly different pin configuration compared to the LP
version. This patch adds support for Sunrisepoint-H to the existing
pinctrl-sunrisepoint.c driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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As of commit 9d07d414d4c33d86 ("ARM: shmobile: r8a73a4: ape6evm: Remove
legacy platform"), r8a73a4 is only supported in generic DT-only ARM
multi-platform builds. The driver doesn't need to match platform
devices by name anymore, hence remove the corresponding
platform_device_id entry.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Pull GPIO fixes from Linus Walleij:
"Here is a bunch of GPIO fixes that I collected since -rc1, nothing
controversial, nothing special:
- fix a memory leak for GPIO hotplug.
- fix a signedness bug in the ACPI GPIO pin validation.
- driver fixes: Qualcomm SPMI and OMAP MPUIO IRQ issues"
* tag 'gpio-v4.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: omap: Fix regression for MPUIO interrupts
gpio: sysfs: fix memory leaks and device hotplug
pinctrl: qcom-spmi-gpio: Fix input value report
pinctrl: qcom-spmi-gpio: Fix output type configuration
gpiolib: change gpio pin from unsigned to signed in acpi callback
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Way back, when the world was a simpler place and there was no war, no
evil, and no kernel bugs, there was just a single pinctrl lock. That
was how the world was when (57291ce pinctrl: core device tree mapping
table parsing support) was written. In that case, there were
instances where the pinctrl mutex was already held when
pinctrl_register_map() was called, hence a "locked" parameter was
passed to the function to indicate that the mutex was already locked
(so we shouldn't lock it again).
A few years ago in (42fed7b pinctrl: move subsystem mutex to
pinctrl_dev struct), we switched to a separate pinctrl_maps_mutex.
...but (oops) we forgot to re-think about the whole "locked" parameter
for pinctrl_register_map(). Basically the "locked" parameter appears
to still refer to whether the bigger pinctrl_dev mutex is locked, but
we're using it to skip locks of our (now separate) pinctrl_maps_mutex.
That's kind of a bad thing(TM). Probably nobody noticed because most
of the calls to pinctrl_register_map happen at boot time and we've got
synchronous device probing. ...and even cases where we're
asynchronous don't end up actually hitting the race too often. ...but
after banging my head against the wall for a bug that reproduced 1 out
of 1000 reboots and lots of looking through kgdb, I finally noticed
this.
Anyway, we can now safely remove the "locked" parameter and go back to
a war-free, evil-free, and kernel-bug-free world.
Fixes: 42fed7ba44e4 ("pinctrl: move subsystem mutex to pinctrl_dev struct")
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The irq_domain_ops are not modified by the driver and the irqdomain core
code accepts pointer to a const data.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The old format to define pinctrl settings for imx in DT has two
hierarchy levels. The first level are function device nodes. The second
level are pingroups which contain a property fsl,pins. The original
intention was to define all pin functions in a single dtsi file and just
reference the correct ones in the board files.
This idea was rejected some time ago leading to the current design to
have all the pinfunctions defined in the board files. So we don't need
the function device nodes anymore.
This patch changes the pinctrl driver to accept devicetrees which do not
have the first hierarchy level, function device nodes. For example
karo-tx25 already has such a devicetree. Old devicetrees are still
parsed and supported.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.
This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:
pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};
mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}
conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};
conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};
conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};
conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Assign GPIO chip and irqchip to the GPIO container dynamically,
so we can set a unique name for each GPIO irqchip and see what
chip the hwirq offset actually relates to.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This activates strict mode muxing for the Nomadik pin controllers,
as these do not allow GPIO and functions to use the same pin
simultaneously.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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While the pinmux_ops are ideally just a vtable for pin mux
calls, the "strict" setting belongs so intuitively with the
pin multiplexing that we should move it here anyway. Putting
it in the top pinctrl_desc makes no sense.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Disallow simultaneous use of the the GPIO and peripheral mux
functions by setting a flag "strict" in struct pinctrl_desc.
The blackfin pinmux and gpio controller doesn't allow user to
set up a pin for both GPIO and peripheral function. So, add flag
strict in struct pinctrl_desc to check both gpio_owner and
mux_owner before approving the pin request.
v2-changes:
- if strict flag is set, check gpio_owner and mux_onwer in if and
else clause
v3-changes:
- add kerneldoc for this struct
- augment Documentation/pinctrl.txt
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add i.MX7D pinctrl driver support
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.
Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the callback for set_multiple.
As this controller has a separate set and clear register, we
can't write directly to PIO_ODSR as this would required a cached
variable and would race with at91_gpio_set.
So build masks for the PIO_SODR and PIO_CODR registers and
write them together.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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cppcheck detected an uninitialized variable:
[drivers/pinctrl/mediatek/pinctrl-mtk-common.c:897]:
(error) Uninitialized variable: unmask
unmask should be initialized to zero to ensure unmasking
only occurs if a previous mask occurred. The current situation
is that the unmask variable could contain any random garbage
causing random unexpected unmasking.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Fix interpretation of the pmic_mpp_read() return code,
negative value means an error.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Read input buffer when input is enabled, not when it is
disabled. Also fix interpretation of the pmic_gpio_read()
return code, negative value means an error.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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GPIO output type configuration was incorrectly overwritten
by strength value. Fix this.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Pin direction configuration was incorrectly overwritten
by output and function values in set_mux(). Fix this.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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There was some mess in the dependencies in the pinctrl
Kconfig for compile tests under allmodconfig. Mea Culpa.
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Pull pincontrol updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.1 development
cycle. Nothing really exciting this time: we basically added a few
new drivers and subdrivers and stabilized them in linux-next. Some
cleanups too. With sunrisepoint Intel has a real fine fully featured
pin control driver for contemporary hardware, and the AMD driver is
also for large deployments. Most of the others are ARM devices.
New drivers:
- Intel Sunrisepoint
- AMD KERNCZ GPIO
- Broadcom Cygnus IOMUX
New subdrivers:
- Marvell MVEBU Armada 39x SoCs
- Samsung Exynos 5433
- nVidia Tegra 210
- Mediatek MT8135
- Mediatek MT8173
- AMLogic Meson8b
- Qualcomm PM8916
On top of this cleanups and development history for the above drivers
as issues were fixed after merging"
* tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
pinctrl: sirf: move sgpio lock into state container
pinctrl: Add support for PM8916 GPIO's and MPP's
pinctrl: bcm2835: Fix support for threaded level triggered IRQs
sh-pfc: r8a7790: add EtherAVB pin groups
pinctrl: Document "function" + "pins" pinmux binding
pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
pinctrl: fsl: imx: Check for 0 config register
pinctrl: Add support for Meson8b
documentation: Extend pinctrl docs for Meson8b
pinctrl: Cleanup Meson8 driver
Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion.
pinctrl: at91: convert __raw to endian agnostic IO
pinctrl: constify of_device_id array
pinctrl: pinconf-generic: add dt node names to error messages
pinctrl: pinconf-generic: scan also referenced phandle node
pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
pinctrl: st: Display pin's function when printing pinctrl debug information
pinctrl: st: Show correct pin direction also in GPIO mode
pinctrl: st: Supply a GPIO get_direction() call-back
pinctrl: st: Move st_get_pio_control() further up the source file
...
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Pull trivial tree from Jiri Kosina:
"Usual trivial tree updates. Nothing outstanding -- mostly printk()
and comment fixes and unused identifier removals"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
goldfish: goldfish_tty_probe() is not using 'i' any more
powerpc: Fix comment in smu.h
qla2xxx: Fix printks in ql_log message
lib: correct link to the original source for div64_u64
si2168, tda10071, m88ds3103: Fix firmware wording
usb: storage: Fix printk in isd200_log_config()
qla2xxx: Fix printk in qla25xx_setup_mode
init/main: fix reset_device comment
ipwireless: missing assignment
goldfish: remove unreachable line of code
coredump: Fix do_coredump() comment
stacktrace.h: remove duplicate declaration task_struct
smpboot.h: Remove unused function prototype
treewide: Fix typo in printk messages
treewide: Fix typo in printk messages
mod_devicetable: fix comment for match_flags
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Instead of referring to a global static variable for the sgpio
locking, use the state container to contain the lock.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add compatible string definitions and supported pin functions.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Currently, the driver uses handle_simple_irq for all IRQ types and hard
codes the acknowledge for different IRQ types into the handler. It is
better to use the IRQ core as intended and let it handle the differences
between the various types of IRQ. For example the current system does
not work for threaded level triggered IRQs as these need to be masked
until the threaded handler has run.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add EtherAVB pin groups to R8A7790 PFC driver.
Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).
The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardware that is
based on the same host controller design.
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0 is used in all pinfunction definitions when a config register is not
available, for example imx25-pinfunc.h. If a configuration value is used
for such a pinfunction the driver will always write it to the
configuration register if it is not -1. For a 0 configuration register
the configuration value is written to offset 0x0. This can lead to a
crashing/hanging system without any warning message.
This patch checks for 0 config register and sets the internal value to
-1. If the configuration value is not NO_PADCTL this leads to an error
message that applying the configuration failed.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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recognized by static analysis tool smatch. Declare constant
Variables with Sparse's suggestion.
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use endian agnostic _relaxed IO accessors instead of the __raw ones.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This makes the error message much more useful.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node
directly referenced by phandle, not only its child nodes.
The "parent scan" feature needs a few other changes:
* Move the pinconf_generic_dt_node_to_map() error handling code to a common
place, under the 'exit' label.
* Move the pins/groups strings count earlier in
pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when
these properties are missing or wrong
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This commit adds suspend/resume support to the Armada XP pinctrl
driver, by simply saving and restoring the MPP registers.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Great for easily determining which mode a pin is operating in.
This patch was particularly helpful when debugging a recent GPIO/
Pinctrl disparity issue.
Before:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
After [GPIO]:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
After [Alt]:
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Until now ST's pinconf_dbg_show() call-back has displayed the PIO
alternate function direction, which is only relevant if a pin is
operating in an alternate function mode i.e not GPIO mode. If a
pin is in GPIO mode its direction is both set and status is
obtained by a completely different/unrelated bunch of registers.
This change ensures that the correct pin direction is shown, even
if a pin is operating in GPIO mode.
Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ST's hardware differentiates between GPIO mode and Pinctrl alternate
functions. When a pin is in GPIO mode, there are dedicated registers
to set and obtain direction status. However, If a pin's alternate
function is in use then the direction is set and status is derived
from a bunch of syscon registers. The issue is; until now there was
a lack of parity between the two.
For example:
Catting the two following information sources could result in
conflicting information (output has been snipped for simplicity):
$ cat /sys/kernel/debug/gpio
GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4:
gpio-33 (? ) out hi
$ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
[retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]
In this example GPIO-33 is a GPIO controlled LED, which is set for
output, as you'd expect. However, when the same information is
drafted from Pinctrl, it clearly states that OE (Output Enable) is
not set i.e. the pin is set for input. This is because OE normally
only represents alternate functions and has no bearing on how the
pin operates when in Alt-0 (GPIO mode).
This patch changes the current semantics and provides a parity link
between the two subsystems. The get_direction() call-back firstly
determines which function a pin is operating in, then uses the
appropriate helpers for that mode.
Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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st_get_pio_control() will be used by subsequent calls which are
to be located above its original position. This is required to
prevent the need for an unnecessary forward-declaration/prototype.
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Mika Westerberg
Andrew Bresticker
Joachim Eastwood
Geert Uytterhoeven
Ulrich Hecht
Linus Torvalds
Doug Anderson
Krzysztof Kozlowski
Markus Pargmann
Helmut Buchsbaum
Linus Walleij
Sonic Zhang
Frank Li
Alexander Stein
Colin Ian King
Ivan T. Ivanov
Andrew Andrianov
Charles Keepax
Sergei Shtylyov
Carlo Caione
Ken Xue
Ben Dooks
Fabian Frederick
Baruch Siach
Thomas Petazzoni
Lee Jones